zynqmp-sck-kr-g-revA.dtso

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for KR260 revA Carrier Card
  4 *
  5 * (C) Copyright 2021, Xilinx, Inc.
  6 *
  7 * Michal Simek <michal.simek@amd.com>
  8 */
  9
 10#include <dt-bindings/gpio/gpio.h>
 11#include <dt-bindings/net/ti-dp83867.h>
 12#include <dt-bindings/phy/phy.h>
 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 14
 15/dts-v1/;
 16/plugin/;
 17
 18&{/} {
 19	compatible = "xlnx,zynqmp-sk-kr260-revA",
 20		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
 21	model = "ZynqMP KR260 revA";
 22
 23	aliases {
 24		ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */
 25		ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
 26	};
 27
 28	ina260-u14 {
 29		compatible = "iio-hwmon";
 30		io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
 31	};
 32
 33	clk_27: clock0 { /* u86 - DP */
 34		compatible = "fixed-clock";
 35		#clock-cells = <0>;
 36		clock-frequency = <27000000>;
 37	};
 38
 39	clk_125: si5332-0 { /* u17 - GEM0/1 */
 40		compatible = "fixed-clock";
 41		#clock-cells = <0>;
 42		clock-frequency = <125000000>;
 43	};
 44
 45	clk_74: si5332-5 { /* u17 - SLVC-EC */
 46		compatible = "fixed-clock";
 47		#clock-cells = <0>;
 48		clock-frequency = <74250000>;
 49	};
 50
 51	clk_26: si5332-2 { /* u17 - USB */
 52		compatible = "fixed-clock";
 53		#clock-cells = <0>;
 54		clock-frequency = <26000000>;
 55	};
 56
 57	clk_156: si5332-3 { /* u17 - SFP+ */
 58		compatible = "fixed-clock";
 59		#clock-cells = <0>;
 60		clock-frequency = <156250000>;
 61	};
 62
 63	clk_25_0: si5332-1 { /* u17 - GEM2 */
 64		compatible = "fixed-clock";
 65		#clock-cells = <0>;
 66		clock-frequency = <25000000>;
 67	};
 68
 69	clk_25_1: si5332-4 { /* u17 - GEM3 */
 70		compatible = "fixed-clock";
 71		#clock-cells = <0>;
 72		clock-frequency = <25000000>;
 73	};
 74	dpcon {
 75		compatible = "dp-connector";
 76		label = "P11";
 77		type = "full-size";
 78
 79		port {
 80			dpcon_in: endpoint {
 81				remote-endpoint = <&dpsub_dp_out>;
 82			};
 83		};
 84	};
 85};
 86
 87&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
 88	#address-cells = <1>;
 89	#size-cells = <0>;
 90	pinctrl-names = "default", "gpio";
 91	pinctrl-0 = <&pinctrl_i2c1_default>;
 92	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 93	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 94	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 95
 96	u14: ina260@40 { /* u14 */
 97		compatible = "ti,ina260";
 98		#io-channel-cells = <1>;
 99		label = "ina260-u14";
100		reg = <0x40>;
101	};
102
103	slg7xl45106: gpio@11 { /* u19 - reset logic */
104		compatible = "dlg,slg7xl45106";
105		reg = <0x11>;
106		label = "resetchip";
107		gpio-controller;
108		#gpio-cells = <2>;
109		gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
110				  "SD_RESET_B", "USB0_HUB_RESET_B",
111				  "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
112				  "PS_GEM1_RESET_B", "";
113	};
114
115	i2c-mux@74 { /* u18 */
116		compatible = "nxp,pca9546";
117		#address-cells = <1>;
118		#size-cells = <0>;
119		reg = <0x74>;
120		usbhub_i2c0: i2c@0 {
121			#address-cells = <1>;
122			#size-cells = <0>;
123			reg = <0>;
124			hub_1: usb-hub@2d {
125				compatible = "microchip,usb5744";
126				reg = <0x2d>;
127			};
128		};
129		usbhub_i2c1: i2c@1 {
130			#address-cells = <1>;
131			#size-cells = <0>;
132			reg = <1>;
133			hub_2: usb-hub@2d {
134				compatible = "microchip,usb5744";
135				reg = <0x2d>;
136			};
137		};
138		/* Bus 2/3 are not connected */
139	};
140
141	/* si5332@6a - u17 - clock-generator */
142};
143
144/* GEM SGMII/DP and USB 3.0 */
145&psgtr {
146	status = "okay";
147	/* gem0/1, dp, usb */
148	clocks = <&clk_125>, <&clk_27>, <&clk_26>;
149	clock-names = "ref0", "ref1", "ref2";
150};
151
152&zynqmp_dpsub {
153	status = "okay";
154	phy-names = "dp-phy0";
155	phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
156	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
157};
158
159&out_dp {
160	dpsub_dp_out: endpoint {
161		remote-endpoint = <&dpcon_in>;
162	};
163};
164
165&zynqmp_dpdma {
166	status = "okay";
167	assigned-clock-rates = <600000000>;
168};
169
170&usb0 { /* mio52 - mio63 */
171	status = "okay";
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_usb0_default>;
174	phy-names = "usb3-phy";
175	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
176	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
177	assigned-clock-rates = <250000000>, <20000000>;
178};
179
180&dwc3_0 {
181	status = "okay";
182	dr_mode = "host";
183	snps,usb3_lpm_capable;
184	maximum-speed = "super-speed";
185	#address-cells = <1>;
186	#size-cells = <0>;
187
188	/* 2.0 hub on port 1 */
189	hub_2_0: hub@1 {
190		compatible = "usb424,2744";
191		reg = <1>;
192		peer-hub = <&hub_3_0>;
193		i2c-bus = <&hub_1>;
194		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
195	};
196
197	/* 3.0 hub on port 2 */
198	hub_3_0: hub@2 {
199		compatible = "usb424,5744";
200		reg = <2>;
201		peer-hub = <&hub_2_0>;
202		i2c-bus = <&hub_1>;
203		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
204	};
205};
206
207&usb1 { /* mio64 - mio75 */
208	status = "okay";
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_usb1_default>;
211	phy-names = "usb3-phy";
212	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
213	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
214	assigned-clock-rates = <250000000>, <20000000>;
215};
216
217&dwc3_1 {
218	status = "okay";
219	dr_mode = "host";
220	snps,usb3_lpm_capable;
221	maximum-speed = "super-speed";
222	#address-cells = <1>;
223	#size-cells = <0>;
224
225	/* 2.0 hub on port 1 */
226	hub1_2_0: hub@1 {
227		compatible = "usb424,2744";
228		reg = <1>;
229		peer-hub = <&hub1_3_0>;
230		i2c-bus = <&hub_2>;
231		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
232	};
233
234	/* 3.0 hub on port 2 */
235	hub1_3_0: hub@2 {
236		compatible = "usb424,5744";
237		reg = <2>;
238		peer-hub = <&hub1_2_0>;
239		i2c-bus = <&hub_2>;
240		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
241	};
242};
243
244&gem0 { /* mdio mio50/51 */
245	status = "okay";
246	phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
247	phy-handle = <&phy0>;
248	phy-mode = "sgmii";
249	assigned-clock-rates = <250000000>;
250};
251
252&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
253	status = "okay";
254	pinctrl-names = "default";
255	pinctrl-0 = <&pinctrl_gem1_default>;
256	phy-handle = <&phy1>;
257	phy-mode = "rgmii-id";
258	assigned-clock-rates = <250000000>;
259
260	mdio: mdio {
261		#address-cells = <1>;
262		#size-cells = <0>;
263		phy0: ethernet-phy@4 { /* u81 */
264			#phy-cells = <1>;
265			compatible = "ethernet-phy-id2000.a231";
266			reg = <4>;
267			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
268			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
269			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
270			ti,dp83867-rxctrl-strap-quirk;
271			reset-assert-us = <300>;
272			reset-deassert-us = <280>;
273			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
274		};
275		phy1: ethernet-phy@8 { /* u36 */
276			#phy-cells = <1>;
277			compatible = "ethernet-phy-id2000.a231";
278			reg = <8>;
279			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
280			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
281			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
282			ti,dp83867-rxctrl-strap-quirk;
283			reset-assert-us = <100>;
284			reset-deassert-us = <280>;
285			reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
286		};
287	};
288};
289
290/* gem2/gem3 via PL with phys u79@2 and u80@3 */
291
292&pinctrl0 {
293	status = "okay";
294
295	pinctrl_uart1_default: uart1-default {
296		conf {
297			groups = "uart1_9_grp";
298			slew-rate = <SLEW_RATE_SLOW>;
299			power-source = <IO_STANDARD_LVCMOS18>;
300			drive-strength = <12>;
301		};
302
303		conf-rx {
304			pins = "MIO37";
305			bias-high-impedance;
306		};
307
308		conf-tx {
309			pins = "MIO36";
310			bias-disable;
311			output-enable;
312		};
313
314		mux {
315			groups = "uart1_9_grp";
316			function = "uart1";
317		};
318	};
319
320	pinctrl_i2c1_default: i2c1-default {
321		conf {
322			groups = "i2c1_6_grp";
323			bias-pull-up;
324			slew-rate = <SLEW_RATE_SLOW>;
325			power-source = <IO_STANDARD_LVCMOS18>;
326		};
327
328		mux {
329			groups = "i2c1_6_grp";
330			function = "i2c1";
331		};
332	};
333
334	pinctrl_i2c1_gpio: i2c1-gpio-grp {
335		conf {
336			groups = "gpio0_24_grp", "gpio0_25_grp";
337			slew-rate = <SLEW_RATE_SLOW>;
338			power-source = <IO_STANDARD_LVCMOS18>;
339		};
340
341		mux {
342			groups = "gpio0_24_grp", "gpio0_25_grp";
343			function = "gpio0";
344		};
345	};
346
347	pinctrl_gem1_default: gem1-default {
348		conf {
349			groups = "ethernet1_0_grp";
350			slew-rate = <SLEW_RATE_SLOW>;
351			power-source = <IO_STANDARD_LVCMOS18>;
352		};
353
354		conf-rx {
355			pins = "MIO44", "MIO46", "MIO48";
356			bias-high-impedance;
357			low-power-disable;
358		};
359
360		conf-bootstrap {
361			pins = "MIO45", "MIO47", "MIO49";
362			bias-disable;
363			output-enable;
364			low-power-disable;
365		};
366
367		conf-tx {
368			pins = "MIO38", "MIO39", "MIO40",
369				"MIO41", "MIO42", "MIO43";
370			bias-disable;
371			output-enable;
372			low-power-enable;
373		};
374
375		conf-mdio {
376			groups = "mdio1_0_grp";
377			slew-rate = <SLEW_RATE_SLOW>;
378			power-source = <IO_STANDARD_LVCMOS18>;
379			bias-disable;
380			output-enable;
381		};
382
383		mux-mdio {
384			function = "mdio1";
385			groups = "mdio1_0_grp";
386		};
387
388		mux {
389			function = "ethernet1";
390			groups = "ethernet1_0_grp";
391		};
392	};
393
394	pinctrl_usb0_default: usb0-default {
395		conf {
396			groups = "usb0_0_grp";
397			power-source = <IO_STANDARD_LVCMOS18>;
398		};
399
400		conf-rx {
401			pins = "MIO52", "MIO53", "MIO55";
402			bias-high-impedance;
403			drive-strength = <12>;
404			slew-rate = <SLEW_RATE_FAST>;
405		};
406
407		conf-tx {
408			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
409			"MIO60", "MIO61", "MIO62", "MIO63";
410			bias-disable;
411			output-enable;
412			drive-strength = <4>;
413			slew-rate = <SLEW_RATE_SLOW>;
414		};
415
416		mux {
417			groups = "usb0_0_grp";
418			function = "usb0";
419		};
420	};
421
422	pinctrl_usb1_default: usb1-default {
423		conf {
424			groups = "usb1_0_grp";
425			power-source = <IO_STANDARD_LVCMOS18>;
426		};
427
428		conf-rx {
429			pins = "MIO64", "MIO65", "MIO67";
430			bias-high-impedance;
431			drive-strength = <12>;
432			slew-rate = <SLEW_RATE_FAST>;
433		};
434
435		conf-tx {
436			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
437			"MIO72", "MIO73", "MIO74", "MIO75";
438			bias-disable;
439			output-enable;
440			drive-strength = <4>;
441			slew-rate = <SLEW_RATE_SLOW>;
442		};
443
444		mux {
445			groups = "usb1_0_grp";
446			function = "usb1";
447		};
448	};
449};
450
451&uart1 {
452	status = "okay";
453	pinctrl-names = "default";
454	pinctrl-0 = <&pinctrl_uart1_default>;
455};