zynqmp-sck-kd-g-revA.dtso

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for KD240 revA Carrier Card
  4 *
  5 * Copyright (C) 2021 - 2022, Xilinx, Inc.
  6 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
  7 *
  8 * Michal Simek <michal.simek@amd.com>
  9 */
 10
 11#include <dt-bindings/gpio/gpio.h>
 12#include <dt-bindings/phy/phy.h>
 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
 14
 15/dts-v1/;
 16/plugin/;
 17
 18&{/} {
 19	compatible = "xlnx,zynqmp-sk-kd240-rev1",
 20		     "xlnx,zynqmp-sk-kd240-revB",
 21		     "xlnx,zynqmp-sk-kd240-revA",
 22		     "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
 23	model = "ZynqMP KD240 revA/B/1";
 24
 25	aliases {
 26		ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
 27	};
 28
 29	ina260-u3 {
 30		compatible = "iio-hwmon";
 31		io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
 32	};
 33
 34	clk_26: clock2 { /* u17 - USB */
 35		compatible = "fixed-clock";
 36		#clock-cells = <0>;
 37		clock-frequency = <26000000>;
 38	};
 39
 40	clk_25_0: clock4 { /* u92/u91 - GEM2 */
 41		compatible = "fixed-clock";
 42		#clock-cells = <0>;
 43		clock-frequency = <25000000>;
 44	};
 45
 46	clk_25_1: clock5 { /* u92/u91 - GEM3 */
 47		compatible = "fixed-clock";
 48		#clock-cells = <0>;
 49		clock-frequency = <25000000>;
 50	};
 51};
 52
 53&can0 {
 54	status = "okay";
 55	pinctrl-names = "default";
 56	pinctrl-0 = <&pinctrl_can0_default>;
 57};
 58
 59&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
 60	#address-cells = <1>;
 61	#size-cells = <0>;
 62	pinctrl-names = "default", "gpio";
 63	pinctrl-0 = <&pinctrl_i2c1_default>;
 64	pinctrl-1 = <&pinctrl_i2c1_gpio>;
 65	scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 66	sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 67
 68	u3: ina260@40 { /* u3 */
 69		compatible = "ti,ina260";
 70		#io-channel-cells = <1>;
 71		label = "ina260-u14";
 72		reg = <0x40>;
 73	};
 74
 75	slg7xl45106: gpio@11 { /* u13 - reset logic */
 76		compatible = "dlg,slg7xl45106";
 77		reg = <0x11>;
 78		label = "resetchip";
 79		gpio-controller;
 80		#gpio-cells = <2>;
 81		gpio-line-names = "USB0_PHY_RESET_B", "",
 82				  "SD_RESET_B", "USB0_HUB_RESET_B",
 83				  "", "PS_GEM0_RESET_B",
 84				  "", "";
 85	};
 86
 87	hub: usb-hub@2d { /* u36 */
 88		compatible = "microchip,usb5744";
 89		reg = <0x2d>;
 90	};
 91};
 92
 93/* USB 3.0 */
 94&psgtr {
 95	status = "okay";
 96	/* usb */
 97	clocks = <&clk_26>;
 98	clock-names = "ref2";
 99};
100
101&usb0 { /* mio52 - mio63 */
102	status = "okay";
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_usb0_default>;
105	phy-names = "usb3-phy";
106	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
107	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
108	assigned-clock-rates = <250000000>, <20000000>;
109};
110
111&dwc3_0 {
112	status = "okay";
113	dr_mode = "host";
114	snps,usb3_lpm_capable;
115	maximum-speed = "super-speed";
116	#address-cells = <1>;
117	#size-cells = <0>;
118
119	/* 2.0 hub on port 1 */
120	hub_2_0: hub@1 {
121		compatible = "usb424,2744";
122		reg = <1>;
123		peer-hub = <&hub_3_0>;
124		i2c-bus = <&hub>;
125		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
126	};
127
128	/* 3.0 hub on port 2 */
129	hub_3_0: hub@2 {
130		compatible = "usb424,5744";
131		reg = <2>;
132		peer-hub = <&hub_2_0>;
133		i2c-bus = <&hub>;
134		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
135	};
136};
137
138&gem1 { /* mdio mio50/51 */
139	status = "okay";
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_gem1_default>;
142	assigned-clock-rates = <250000000>;
143
144	phy-handle = <&phy0>;
145	phy-mode = "rgmii-id";
146	mdio: mdio {
147		#address-cells = <1>;
148		#size-cells = <0>;
149		phy0: ethernet-phy@8 { /* Adin u31 */
150			#phy-cells = <1>;
151			compatible = "ethernet-phy-id0283.bc30";
152			reg = <8>;
153			adi,rx-internal-delay-ps = <2000>;
154			adi,tx-internal-delay-ps = <2000>;
155			adi,fifo-depth-bits = <8>;
156			reset-assert-us = <10>;
157			reset-deassert-us = <5000>;
158			reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
159		};
160	};
161};
162
163/* 2 more ethernet phys u32@2 and u34@3 */
164
165&pinctrl0 { /* required by spec */
166	status = "okay";
167
168	pinctrl_can0_default: can0-default {
169		mux {
170			function = "can0";
171			groups = "can0_16_grp";
172		};
173
174		conf {
175			groups = "can0_16_grp";
176			slew-rate = <SLEW_RATE_SLOW>;
177			power-source = <IO_STANDARD_LVCMOS18>;
178		};
179
180		conf-rx {
181			pins = "MIO66";
182			bias-pull-up;
183		};
184
185		conf-tx {
186			pins = "MIO67";
187			bias-pull-up;
188			drive-strength = <4>;
189		};
190	};
191
192	pinctrl_uart0_default: uart0-default {
193		conf {
194			groups = "uart0_17_grp";
195			slew-rate = <SLEW_RATE_SLOW>;
196			power-source = <IO_STANDARD_LVCMOS18>;
197			drive-strength = <12>;
198		};
199
200		conf-rx {
201			pins = "MIO70";
202			bias-high-impedance;
203		};
204
205		conf-tx {
206			pins = "MIO71";
207			bias-disable;
208		};
209
210		mux {
211			groups = "uart0_17_grp";
212			function = "uart0";
213		};
214	};
215
216	pinctrl_uart1_default: uart1-default {
217		conf {
218			groups = "uart1_9_grp";
219			slew-rate = <SLEW_RATE_SLOW>;
220			power-source = <IO_STANDARD_LVCMOS18>;
221			drive-strength = <12>;
222		};
223
224		conf-rx {
225			pins = "MIO37";
226			bias-high-impedance;
227		};
228
229		conf-tx {
230			pins = "MIO36";
231			bias-disable;
232			output-enable;
233		};
234
235		mux {
236			groups = "uart1_9_grp";
237			function = "uart1";
238		};
239	};
240
241	pinctrl_i2c1_default: i2c1-default {
242		conf {
243			groups = "i2c1_6_grp";
244			bias-pull-up;
245			slew-rate = <SLEW_RATE_SLOW>;
246			power-source = <IO_STANDARD_LVCMOS18>;
247		};
248
249		mux {
250			groups = "i2c1_6_grp";
251			function = "i2c1";
252		};
253	};
254
255	pinctrl_i2c1_gpio: i2c1-gpio-grp {
256		conf {
257			groups = "gpio0_24_grp", "gpio0_25_grp";
258			slew-rate = <SLEW_RATE_SLOW>;
259			power-source = <IO_STANDARD_LVCMOS18>;
260		};
261
262		mux {
263			groups = "gpio0_24_grp", "gpio0_25_grp";
264			function = "gpio0";
265		};
266	};
267
268	pinctrl_gem1_default: gem1-default {
269		conf {
270			groups = "ethernet1_0_grp";
271			slew-rate = <SLEW_RATE_SLOW>;
272			power-source = <IO_STANDARD_LVCMOS18>;
273		};
274
275		conf-rx {
276			pins = "MIO45", "MIO46", "MIO47", "MIO48";
277			bias-disable;
278			low-power-disable;
279		};
280
281		conf-bootstrap {
282			pins = "MIO44", "MIO49";
283			bias-disable;
284			output-enable;
285			low-power-disable;
286		};
287
288		conf-tx {
289			pins = "MIO38", "MIO39", "MIO40",
290				"MIO41", "MIO42", "MIO43";
291			bias-disable;
292			output-enable;
293			low-power-enable;
294		};
295
296		conf-mdio {
297			groups = "mdio1_0_grp";
298			slew-rate = <SLEW_RATE_SLOW>;
299			power-source = <IO_STANDARD_LVCMOS18>;
300			bias-disable;
301			output-enable;
302		};
303
304		mux-mdio {
305			function = "mdio1";
306			groups = "mdio1_0_grp";
307		};
308
309		mux {
310			function = "ethernet1";
311			groups = "ethernet1_0_grp";
312		};
313	};
314
315	pinctrl_usb0_default: usb0-default {
316		conf {
317			groups = "usb0_0_grp";
318			power-source = <IO_STANDARD_LVCMOS18>;
319		};
320
321		conf-rx {
322			pins = "MIO52", "MIO53", "MIO55";
323			bias-high-impedance;
324			drive-strength = <12>;
325			slew-rate = <SLEW_RATE_FAST>;
326		};
327
328		conf-tx {
329			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
330			"MIO60", "MIO61", "MIO62", "MIO63";
331			bias-disable;
332			output-enable;
333			drive-strength = <4>;
334			slew-rate = <SLEW_RATE_SLOW>;
335		};
336
337		mux {
338			groups = "usb0_0_grp";
339			function = "usb0";
340		};
341	};
342
343	pinctrl_usb1_default: usb1-default {
344		conf {
345			groups = "usb1_0_grp";
346			power-source = <IO_STANDARD_LVCMOS18>;
347		};
348
349		conf-rx {
350			pins = "MIO64", "MIO65", "MIO67";
351			bias-high-impedance;
352			drive-strength = <12>;
353			slew-rate = <SLEW_RATE_FAST>;
354		};
355
356		conf-tx {
357			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
358			"MIO72", "MIO73", "MIO74", "MIO75";
359			bias-disable;
360			output-enable;
361			drive-strength = <4>;
362			slew-rate = <SLEW_RATE_SLOW>;
363		};
364
365		mux {
366			groups = "usb1_0_grp";
367			function = "usb1";
368		};
369	};
370};
371
372&uart0 {
373	status = "okay";
374	rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
375	linux,rs485-enabled-at-boot-time;
376	rs485-rts-delay = <10 10>;
377	pinctrl-names = "default";
378	pinctrl-0 = <&pinctrl_uart0_default>;
379	assigned-clock-rates = <100000000>;
380};
381
382&uart1 {
383	status = "okay";
384	pinctrl-names = "default";
385	pinctrl-0 = <&pinctrl_uart1_default>;
386};
387
388&zynqmp_dpsub {
389	status = "disabled";
390};