zynqmp-clk-ccf.dtsi

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Clock specification for Xilinx ZynqMP
  4 *
  5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
  6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  7 *
  8 * Michal Simek <michal.simek@amd.com>
  9 */
 10
 11#include "xlnx-zynqmp-clk.h"
 12/ {
 13	pss_ref_clk: pss-ref-clk {
 14		bootph-all;
 15		compatible = "fixed-clock";
 16		#clock-cells = <0>;
 17		clock-frequency = <33333333>;
 18		clock-output-names = "pss_ref_clk";
 19	};
 20
 21	video_clk: video-clk {
 22		bootph-all;
 23		compatible = "fixed-clock";
 24		#clock-cells = <0>;
 25		clock-frequency = <27000000>;
 26		clock-output-names = "video_clk";
 27	};
 28
 29	pss_alt_ref_clk: pss-alt-ref-clk {
 30		bootph-all;
 31		compatible = "fixed-clock";
 32		#clock-cells = <0>;
 33		clock-frequency = <0>;
 34		clock-output-names = "pss_alt_ref_clk";
 35	};
 36
 37	gt_crx_ref_clk: gt-crx-ref-clk {
 38		bootph-all;
 39		compatible = "fixed-clock";
 40		#clock-cells = <0>;
 41		clock-frequency = <108000000>;
 42		clock-output-names = "gt_crx_ref_clk";
 43	};
 44
 45	aux_ref_clk: aux-ref-clk {
 46		bootph-all;
 47		compatible = "fixed-clock";
 48		#clock-cells = <0>;
 49		clock-frequency = <27000000>;
 50		clock-output-names = "aux_ref_clk";
 51	};
 52};
 53
 54&zynqmp_firmware {
 55	zynqmp_clk: clock-controller {
 56		bootph-all;
 57		#clock-cells = <1>;
 58		compatible = "xlnx,zynqmp-clk";
 59		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
 60			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
 61		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
 62			      "aux_ref_clk", "gt_crx_ref_clk";
 63	};
 64};
 65
 66&can0 {
 67	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
 68};
 69
 70&can1 {
 71	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
 72};
 73
 74&cpu0 {
 75	clocks = <&zynqmp_clk ACPU>;
 76};
 77
 78&cpu0_debug {
 79	clocks = <&zynqmp_clk DBF_FPD>;
 80};
 81
 82&cpu1_debug {
 83	clocks = <&zynqmp_clk DBF_FPD>;
 84};
 85
 86&cpu2_debug {
 87	clocks = <&zynqmp_clk DBF_FPD>;
 88};
 89
 90&cpu3_debug {
 91	clocks = <&zynqmp_clk DBF_FPD>;
 92};
 93
 94&fpd_dma_chan1 {
 95	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 96};
 97
 98&fpd_dma_chan2 {
 99	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
100};
101
102&fpd_dma_chan3 {
103	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
104};
105
106&fpd_dma_chan4 {
107	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
108};
109
110&fpd_dma_chan5 {
111	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
112};
113
114&fpd_dma_chan6 {
115	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
116};
117
118&fpd_dma_chan7 {
119	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
120};
121
122&fpd_dma_chan8 {
123	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
124};
125
126&gpu {
127	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
128};
129
130&lpd_dma_chan1 {
131	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
132};
133
134&lpd_dma_chan2 {
135	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
136};
137
138&lpd_dma_chan3 {
139	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
140};
141
142&lpd_dma_chan4 {
143	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
144};
145
146&lpd_dma_chan5 {
147	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
148};
149
150&lpd_dma_chan6 {
151	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
152};
153
154&lpd_dma_chan7 {
155	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
156};
157
158&lpd_dma_chan8 {
159	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
160};
161
162&nand0 {
163	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
164};
165
166&gem0 {
167	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
168		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
169		 <&zynqmp_clk GEM_TSU>;
170	assigned-clocks = <&zynqmp_clk GEM_TSU>;
171};
172
173&gem1 {
174	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
175		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
176		 <&zynqmp_clk GEM_TSU>;
177	assigned-clocks = <&zynqmp_clk GEM_TSU>;
178};
179
180&gem2 {
181	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
182		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
183		 <&zynqmp_clk GEM_TSU>;
184	assigned-clocks = <&zynqmp_clk GEM_TSU>;
185};
186
187&gem3 {
188	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
189		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
190		 <&zynqmp_clk GEM_TSU>;
191	assigned-clocks = <&zynqmp_clk GEM_TSU>;
192};
193
194&gpio {
195	clocks = <&zynqmp_clk LPD_LSBUS>;
196};
197
198&i2c0 {
199	clocks = <&zynqmp_clk I2C0_REF>;
200};
201
202&i2c1 {
203	clocks = <&zynqmp_clk I2C1_REF>;
204};
205
206&pcie {
207	clocks = <&zynqmp_clk PCIE_REF>;
208};
209
210&qspi {
211	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
212};
213
214&sata {
215	clocks = <&zynqmp_clk SATA_REF>;
216};
217
218&sdhci0 {
219	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
220	assigned-clocks = <&zynqmp_clk SDIO0_REF>;
221};
222
223&sdhci1 {
224	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
225	assigned-clocks = <&zynqmp_clk SDIO1_REF>;
226};
227
228&spi0 {
229	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
230};
231
232&spi1 {
233	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
234};
235
236&ttc0 {
237	clocks = <&zynqmp_clk LPD_LSBUS>;
238};
239
240&ttc1 {
241	clocks = <&zynqmp_clk LPD_LSBUS>;
242};
243
244&ttc2 {
245	clocks = <&zynqmp_clk LPD_LSBUS>;
246};
247
248&ttc3 {
249	clocks = <&zynqmp_clk LPD_LSBUS>;
250};
251
252&uart0 {
253	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
254	assigned-clocks = <&zynqmp_clk UART0_REF>;
255};
256
257&uart1 {
258	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
259	assigned-clocks = <&zynqmp_clk UART1_REF>;
260};
261
262&usb0 {
263	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
264	assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
265};
266
267&dwc3_0 {
268	clocks = <&zynqmp_clk USB3_DUAL_REF>;
269};
270
271&usb1 {
272	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
273	assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
274};
275
276&dwc3_1 {
277	clocks = <&zynqmp_clk USB3_DUAL_REF>;
278};
279
280&watchdog0 {
281	clocks = <&zynqmp_clk WDT>;
282};
283
284&lpd_watchdog {
285	clocks = <&zynqmp_clk LPD_WDT>;
286};
287
288&xilinx_ams {
289	clocks = <&zynqmp_clk AMS_REF>;
290};
291
292&zynqmp_dpdma {
293	clocks = <&zynqmp_clk DPDMA_REF>;
294	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
295};
296
297&zynqmp_dpsub {
298	clocks = <&zynqmp_clk TOPSW_LSBUS>,
299		 <&zynqmp_clk DP_AUDIO_REF>,
300		 <&zynqmp_clk DP_VIDEO_REF>;
301	assigned-clocks = <&zynqmp_clk DP_STC_REF>,
302			  <&zynqmp_clk DP_AUDIO_REF>,
303			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
304};