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versal-net.dtsi
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linux-6.19.14/arch/arm64/boot/dts/xilinx/versal-net.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal NET 4 * 5 * (C) Copyright 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 * 8 * Michal Simek <michal.simek@amd.com> 9 */ 10 11/dts-v1/; 12 13/ { 14 compatible = "xlnx,versal-net"; 15 model = "Xilinx Versal NET"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 options { 21 u-boot { 22 compatible = "u-boot,config"; 23 bootscr-address = /bits/ 64 <0x20000000>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 cpu-map { 31 cluster0 { 32 core0 { 33 cpu = <&cpu0>; 34 }; 35 core1 { 36 cpu = <&cpu100>; 37 }; 38 core2 { 39 cpu = <&cpu200>; 40 }; 41 core3 { 42 cpu = <&cpu300>; 43 }; 44 }; 45 46 cluster1 { 47 core0 { 48 cpu = <&cpu10000>; 49 }; 50 51 core1 { 52 cpu = <&cpu10100>; 53 }; 54 55 core2 { 56 cpu = <&cpu10200>; 57 }; 58 59 core3 { 60 cpu = <&cpu10300>; 61 }; 62 }; 63 cluster2 { 64 core0 { 65 cpu = <&cpu20000>; 66 }; 67 68 core1 { 69 cpu = <&cpu20100>; 70 }; 71 72 core2 { 73 cpu = <&cpu20200>; 74 }; 75 76 core3 { 77 cpu = <&cpu20300>; 78 }; 79 }; 80 cluster3 { 81 core0 { 82 cpu = <&cpu30000>; 83 }; 84 85 core1 { 86 cpu = <&cpu30100>; 87 }; 88 89 core2 { 90 cpu = <&cpu30200>; 91 }; 92 93 core3 { 94 cpu = <&cpu30300>; 95 }; 96 }; 97 98 }; 99 100 cpu0: cpu@0 { 101 compatible = "arm,cortex-a78"; 102 device_type = "cpu"; 103 enable-method = "psci"; 104 reg = <0>; 105 operating-points-v2 = <&cpu_opp_table>; 106 cpu-idle-states = <&CPU_SLEEP_0>; 107 d-cache-size = <0x10000>; /* 64kB */ 108 d-cache-line-size = <64>; 109 /* 4 ways set associativity */ 110 /* cache_size / (line_size / associativity) */ 111 d-cache-sets = <256>; 112 i-cache-size = <0x10000>; /* 64kB */ 113 i-cache-line-size = <64>; 114 /* 4 ways set associativity */ 115 /* cache_size / (line_size / associativity) */ 116 i-cache-sets = <256>; 117 next-level-cache = <&l2_00>; 118 l2_00: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-size = <0x80000>; /* 512kB */ 122 cache-line-size = <64>; 123 /* 8 ways set associativity */ 124 /* cache_size / (line_size/associativity) */ 125 cache-sets = <1024>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 cpu100: cpu@100 { 131 compatible = "arm,cortex-a78"; 132 device_type = "cpu"; 133 enable-method = "psci"; 134 reg = <0x100>; 135 operating-points-v2 = <&cpu_opp_table>; 136 cpu-idle-states = <&CPU_SLEEP_0>; 137 d-cache-size = <0x10000>; /* 64kB */ 138 d-cache-line-size = <64>; 139 /* 4 ways set associativity */ 140 /* cache_size / (line_size / associativity) */ 141 d-cache-sets = <256>; 142 i-cache-size = <0x10000>; /* 64kB */ 143 i-cache-line-size = <64>; 144 /* 4 ways set associativity */ 145 /* cache_size / (line_size / associativity) */ 146 i-cache-sets = <256>; 147 next-level-cache = <&l2_01>; 148 l2_01: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-size = <0x80000>; /* 512kB */ 152 cache-line-size = <64>; 153 /* 8 ways set associativity */ 154 /* cache_size / (line_size/associativity) */ 155 cache-sets = <1024>; 156 cache-unified; 157 next-level-cache = <&l3_0>; 158 }; 159 }; 160 cpu200: cpu@200 { 161 compatible = "arm,cortex-a78"; 162 device_type = "cpu"; 163 enable-method = "psci"; 164 reg = <0x200>; 165 operating-points-v2 = <&cpu_opp_table>; 166 cpu-idle-states = <&CPU_SLEEP_0>; 167 d-cache-size = <0x10000>; /* 64kB */ 168 d-cache-line-size = <64>; 169 /* 4 ways set associativity */ 170 /* cache_size / (line_size / associativity) */ 171 d-cache-sets = <256>; 172 i-cache-size = <0x10000>; /* 64kB */ 173 i-cache-line-size = <64>; 174 /* 4 ways set associativity */ 175 /* cache_size / (line_size / associativity) */ 176 i-cache-sets = <256>; 177 next-level-cache = <&l2_02>; 178 l2_02: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-size = <0x80000>; /* 512kB */ 182 cache-line-size = <64>; 183 /* 8 ways set associativity */ 184 /* cache_size / (line_size/associativity) */ 185 cache-sets = <1024>; 186 cache-unified; 187 next-level-cache = <&l3_0>; 188 }; 189 }; 190 cpu300: cpu@300 { 191 compatible = "arm,cortex-a78"; 192 device_type = "cpu"; 193 enable-method = "psci"; 194 reg = <0x300>; 195 operating-points-v2 = <&cpu_opp_table>; 196 cpu-idle-states = <&CPU_SLEEP_0>; 197 d-cache-size = <0x10000>; /* 64kB */ 198 d-cache-line-size = <64>; 199 /* 4 ways set associativity */ 200 /* cache_size / (line_size / associativity) */ 201 d-cache-sets = <256>; 202 i-cache-size = <0x10000>; /* 64kB */ 203 i-cache-line-size = <64>; 204 /* 4 ways set associativity */ 205 /* cache_size / (line_size / associativity) */ 206 i-cache-sets = <256>; 207 next-level-cache = <&l2_03>; 208 l2_03: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 cache-size = <0x80000>; /* 512kB */ 212 cache-line-size = <64>; 213 /* 8 ways set associativity */ 214 /* cache_size / (line_size/associativity) */ 215 cache-sets = <1024>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 cpu10000: cpu@10000 { 221 compatible = "arm,cortex-a78"; 222 device_type = "cpu"; 223 enable-method = "psci"; 224 reg = <0x10000>; 225 operating-points-v2 = <&cpu_opp_table>; 226 cpu-idle-states = <&CPU_SLEEP_0>; 227 d-cache-size = <0x10000>; /* 64kB */ 228 d-cache-line-size = <64>; 229 /* 4 ways set associativity */ 230 /* cache_size / (line_size / associativity) */ 231 d-cache-sets = <256>; 232 i-cache-size = <0x10000>; /* 64kB */ 233 i-cache-line-size = <64>; 234 /* 4 ways set associativity */ 235 /* cache_size / (line_size / associativity) */ 236 i-cache-sets = <256>; 237 next-level-cache = <&l2_10>; 238 l2_10: l2-cache { 239 compatible = "cache"; 240 cache-level = <2>; 241 cache-size = <0x80000>; /* 512kB */ 242 cache-line-size = <64>; 243 /* 8 ways set associativity */ 244 /* cache_size / (line_size/associativity) */ 245 cache-sets = <1024>; 246 cache-unified; 247 next-level-cache = <&l3_1>; 248 }; 249 }; 250 cpu10100: cpu@10100 { 251 compatible = "arm,cortex-a78"; 252 device_type = "cpu"; 253 enable-method = "psci"; 254 reg = <0x10100>; 255 operating-points-v2 = <&cpu_opp_table>; 256 cpu-idle-states = <&CPU_SLEEP_0>; 257 d-cache-size = <0x10000>; /* 64kB */ 258 d-cache-line-size = <64>; 259 /* 4 ways set associativity */ 260 /* cache_size / (line_size / associativity) */ 261 d-cache-sets = <256>; 262 i-cache-size = <0x10000>; /* 64kB */ 263 i-cache-line-size = <64>; 264 /* 4 ways set associativity */ 265 /* cache_size / (line_size / associativity) */ 266 i-cache-sets = <256>; 267 next-level-cache = <&l2_11>; 268 l2_11: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-size = <0x80000>; /* 512kB */ 272 cache-line-size = <64>; 273 /* 8 ways set associativity */ 274 /* cache_size / (line_size/associativity) */ 275 cache-sets = <1024>; 276 cache-unified; 277 next-level-cache = <&l3_1>; 278 }; 279 }; 280 cpu10200: cpu@10200 { 281 compatible = "arm,cortex-a78"; 282 device_type = "cpu"; 283 enable-method = "psci"; 284 reg = <0x10200>; 285 operating-points-v2 = <&cpu_opp_table>; 286 cpu-idle-states = <&CPU_SLEEP_0>; 287 d-cache-size = <0x10000>; /* 64kB */ 288 d-cache-line-size = <64>; 289 /* 4 ways set associativity */ 290 /* cache_size / (line_size / associativity) */ 291 d-cache-sets = <256>; 292 i-cache-size = <0x10000>; /* 64kB */ 293 i-cache-line-size = <64>; 294 /* 4 ways set associativity */ 295 /* cache_size / (line_size / associativity) */ 296 i-cache-sets = <256>; 297 next-level-cache = <&l2_12>; 298 l2_12: l2-cache { 299 compatible = "cache"; 300 cache-level = <2>; 301 cache-size = <0x80000>; /* 512kB */ 302 cache-line-size = <64>; 303 /* 8 ways set associativity */ 304 /* cache_size / (line_size/associativity) */ 305 cache-sets = <1024>; 306 cache-unified; 307 next-level-cache = <&l3_1>; 308 }; 309 }; 310 cpu10300: cpu@10300 { 311 compatible = "arm,cortex-a78"; 312 device_type = "cpu"; 313 enable-method = "psci"; 314 reg = <0x10300>; 315 operating-points-v2 = <&cpu_opp_table>; 316 cpu-idle-states = <&CPU_SLEEP_0>; 317 d-cache-size = <0x10000>; /* 64kB */ 318 d-cache-line-size = <64>; 319 /* 4 ways set associativity */ 320 /* cache_size / (line_size / associativity) */ 321 d-cache-sets = <256>; 322 i-cache-size = <0x10000>; /* 64kB */ 323 i-cache-line-size = <64>; 324 /* 4 ways set associativity */ 325 /* cache_size / (line_size / associativity) */ 326 i-cache-sets = <256>; 327 next-level-cache = <&l2_13>; 328 l2_13: l2-cache { 329 compatible = "cache"; 330 cache-level = <2>; 331 cache-size = <0x80000>; /* 512kB */ 332 cache-line-size = <64>; 333 /* 8 ways set associativity */ 334 /* cache_size / (line_size/associativity) */ 335 cache-sets = <1024>; 336 cache-unified; 337 next-level-cache = <&l3_1>; 338 }; 339 }; 340 cpu20000: cpu@20000 { 341 compatible = "arm,cortex-a78"; 342 device_type = "cpu"; 343 enable-method = "psci"; 344 reg = <0x20000>; 345 operating-points-v2 = <&cpu_opp_table>; 346 cpu-idle-states = <&CPU_SLEEP_0>; 347 d-cache-size = <0x10000>; /* 64kB */ 348 d-cache-line-size = <64>; 349 /* 4 ways set associativity */ 350 /* cache_size / (line_size / associativity) */ 351 d-cache-sets = <256>; 352 i-cache-size = <0x10000>; /* 64kB */ 353 i-cache-line-size = <64>; 354 /* 4 ways set associativity */ 355 /* cache_size / (line_size / associativity) */ 356 i-cache-sets = <256>; 357 next-level-cache = <&l2_20>; 358 l2_20: l2-cache { 359 compatible = "cache"; 360 cache-level = <2>; 361 cache-size = <0x80000>; /* 512kB */ 362 cache-line-size = <64>; 363 /* 8 ways set associativity */ 364 /* cache_size / (line_size/associativity) */ 365 cache-sets = <1024>; 366 cache-unified; 367 next-level-cache = <&l3_2>; 368 }; 369 }; 370 cpu20100: cpu@20100 { 371 compatible = "arm,cortex-a78"; 372 device_type = "cpu"; 373 enable-method = "psci"; 374 reg = <0x20100>; 375 operating-points-v2 = <&cpu_opp_table>; 376 cpu-idle-states = <&CPU_SLEEP_0>; 377 d-cache-size = <0x10000>; /* 64kB */ 378 d-cache-line-size = <64>; 379 /* 4 ways set associativity */ 380 /* cache_size / (line_size / associativity) */ 381 d-cache-sets = <256>; 382 i-cache-size = <0x10000>; /* 64kB */ 383 i-cache-line-size = <64>; 384 /* 4 ways set associativity */ 385 /* cache_size / (line_size / associativity) */ 386 i-cache-sets = <256>; 387 next-level-cache = <&l2_21>; 388 l2_21: l2-cache { 389 compatible = "cache"; 390 cache-level = <2>; 391 cache-size = <0x80000>; /* 512kB */ 392 cache-line-size = <64>; 393 /* 8 ways set associativity */ 394 /* cache_size / (line_size/associativity) */ 395 cache-sets = <1024>; 396 cache-unified; 397 next-level-cache = <&l3_2>; 398 }; 399 }; 400 cpu20200: cpu@20200 { 401 compatible = "arm,cortex-a78"; 402 device_type = "cpu"; 403 enable-method = "psci"; 404 reg = <0x20200>; 405 operating-points-v2 = <&cpu_opp_table>; 406 cpu-idle-states = <&CPU_SLEEP_0>; 407 d-cache-size = <0x10000>; /* 64kB */ 408 d-cache-line-size = <64>; 409 /* 4 ways set associativity */ 410 /* cache_size / (line_size / associativity) */ 411 d-cache-sets = <256>; 412 i-cache-size = <0x10000>; /* 64kB */ 413 i-cache-line-size = <64>; 414 /* 4 ways set associativity */ 415 /* cache_size / (line_size / associativity) */ 416 i-cache-sets = <256>; 417 next-level-cache = <&l2_22>; 418 l2_22: l2-cache { 419 compatible = "cache"; 420 cache-level = <2>; 421 cache-size = <0x80000>; /* 512kB */ 422 cache-line-size = <64>; 423 /* 8 ways set associativity */ 424 /* cache_size / (line_size/associativity) */ 425 cache-sets = <1024>; 426 cache-unified; 427 next-level-cache = <&l3_2>; 428 }; 429 }; 430 cpu20300: cpu@20300 { 431 compatible = "arm,cortex-a78"; 432 device_type = "cpu"; 433 enable-method = "psci"; 434 reg = <0x20300>; 435 operating-points-v2 = <&cpu_opp_table>; 436 cpu-idle-states = <&CPU_SLEEP_0>; 437 d-cache-size = <0x10000>; /* 64kB */ 438 d-cache-line-size = <64>; 439 /* 4 ways set associativity */ 440 /* cache_size / (line_size / associativity) */ 441 d-cache-sets = <256>; 442 i-cache-size = <0x10000>; /* 64kB */ 443 i-cache-line-size = <64>; 444 /* 4 ways set associativity */ 445 /* cache_size / (line_size / associativity) */ 446 i-cache-sets = <256>; 447 next-level-cache = <&l2_23>; 448 l2_23: l2-cache { 449 compatible = "cache"; 450 cache-level = <2>; 451 cache-size = <0x80000>; /* 512kB */ 452 cache-line-size = <64>; 453 /* 8 ways set associativity */ 454 /* cache_size / (line_size/associativity) */ 455 cache-sets = <1024>; 456 cache-unified; 457 next-level-cache = <&l3_2>; 458 }; 459 }; 460 cpu30000: cpu@30000 { 461 compatible = "arm,cortex-a78"; 462 device_type = "cpu"; 463 enable-method = "psci"; 464 reg = <0x30000>; 465 operating-points-v2 = <&cpu_opp_table>; 466 cpu-idle-states = <&CPU_SLEEP_0>; 467 d-cache-size = <0x10000>; /* 64kB */ 468 d-cache-line-size = <64>; 469 /* 4 ways set associativity */ 470 /* cache_size / (line_size / associativity) */ 471 d-cache-sets = <256>; 472 i-cache-size = <0x10000>; /* 64kB */ 473 i-cache-line-size = <64>; 474 /* 4 ways set associativity */ 475 /* cache_size / (line_size / associativity) */ 476 i-cache-sets = <256>; 477 next-level-cache = <&l2_30>; 478 l2_30: l2-cache { 479 compatible = "cache"; 480 cache-level = <2>; 481 cache-size = <0x80000>; /* 512kB */ 482 cache-line-size = <64>; 483 /* 8 ways set associativity */ 484 /* cache_size / (line_size/associativity) */ 485 cache-sets = <1024>; 486 cache-unified; 487 next-level-cache = <&l3_3>; 488 }; 489 }; 490 cpu30100: cpu@30100 { 491 compatible = "arm,cortex-a78"; 492 device_type = "cpu"; 493 enable-method = "psci"; 494 reg = <0x30100>; 495 operating-points-v2 = <&cpu_opp_table>; 496 cpu-idle-states = <&CPU_SLEEP_0>; 497 d-cache-size = <0x10000>; /* 64kB */ 498 d-cache-line-size = <64>; 499 /* 4 ways set associativity */ 500 /* cache_size / (line_size / associativity) */ 501 d-cache-sets = <256>; 502 i-cache-size = <0x10000>; /* 64kB */ 503 i-cache-line-size = <64>; 504 /* 4 ways set associativity */ 505 /* cache_size / (line_size / associativity) */ 506 i-cache-sets = <256>; 507 next-level-cache = <&l2_31>; 508 l2_31: l2-cache { 509 compatible = "cache"; 510 cache-level = <2>; 511 cache-size = <0x80000>; /* 512kB */ 512 cache-line-size = <64>; 513 /* 8 ways set associativity */ 514 /* cache_size / (line_size/associativity) */ 515 cache-sets = <1024>; 516 cache-unified; 517 next-level-cache = <&l3_3>; 518 }; 519 }; 520 cpu30200: cpu@30200 { 521 compatible = "arm,cortex-a78"; 522 device_type = "cpu"; 523 enable-method = "psci"; 524 reg = <0x30200>; 525 operating-points-v2 = <&cpu_opp_table>; 526 cpu-idle-states = <&CPU_SLEEP_0>; 527 d-cache-size = <0x10000>; /* 64kB */ 528 d-cache-line-size = <64>; 529 /* 4 ways set associativity */ 530 /* cache_size / (line_size / associativity) */ 531 d-cache-sets = <256>; 532 i-cache-size = <0x10000>; /* 64kB */ 533 i-cache-line-size = <64>; 534 /* 4 ways set associativity */ 535 /* cache_size / (line_size / associativity) */ 536 i-cache-sets = <256>; 537 next-level-cache = <&l2_32>; 538 l2_32: l2-cache { 539 compatible = "cache"; 540 cache-level = <2>; 541 cache-size = <0x80000>; /* 512kB */ 542 cache-line-size = <64>; 543 /* 8 ways set associativity */ 544 /* cache_size / (line_size/associativity) */ 545 cache-sets = <1024>; 546 cache-unified; 547 next-level-cache = <&l3_3>; 548 }; 549 }; 550 cpu30300: cpu@30300 { 551 compatible = "arm,cortex-a78"; 552 device_type = "cpu"; 553 enable-method = "psci"; 554 reg = <0x30300>; 555 operating-points-v2 = <&cpu_opp_table>; 556 cpu-idle-states = <&CPU_SLEEP_0>; 557 d-cache-size = <0x10000>; /* 64kB */ 558 d-cache-line-size = <64>; 559 /* 4 ways set associativity */ 560 /* cache_size / (line_size / associativity) */ 561 d-cache-sets = <256>; 562 i-cache-size = <0x10000>; /* 64kB */ 563 i-cache-line-size = <64>; 564 /* 4 ways set associativity */ 565 /* cache_size / (line_size / associativity) */ 566 i-cache-sets = <256>; 567 next-level-cache = <&l2_33>; 568 l2_33: l2-cache { 569 compatible = "cache"; 570 cache-level = <2>; 571 cache-size = <0x80000>; /* 512kB */ 572 cache-line-size = <64>; 573 /* 8 ways set associativity */ 574 /* cache_size / (line_size/associativity) */ 575 cache-sets = <1024>; 576 cache-unified; 577 next-level-cache = <&l3_3>; 578 }; 579 }; 580 581 l3_0: l3-0-cache { /* cluster private */ 582 compatible = "cache"; 583 cache-level = <3>; 584 cache-size = <0x200000>; /* 2MB */ 585 cache-line-size = <64>; 586 /* 16 ways set associativity */ 587 /* cache_size / (line_size/associativity) */ 588 cache-sets = <2048>; 589 cache-unified; 590 next-level-cache = <&llc>; 591 }; 592 593 l3_1: l3-1-cache { /* cluster private */ 594 compatible = "cache"; 595 cache-level = <3>; 596 cache-size = <0x200000>; /* 2MB */ 597 cache-line-size = <64>; 598 /* 16 ways set associativity */ 599 /* cache_size / (line_size/associativity) */ 600 cache-sets = <2048>; 601 cache-unified; 602 next-level-cache = <&llc>; 603 }; 604 605 l3_2: l3-2-cache { /* cluster private */ 606 compatible = "cache"; 607 cache-level = <3>; 608 cache-size = <0x200000>; /* 2MB */ 609 cache-line-size = <64>; 610 /* 16 ways set associativity */ 611 /* cache_size / (line_size/associativity) */ 612 cache-sets = <2048>; 613 cache-unified; 614 next-level-cache = <&llc>; 615 }; 616 617 l3_3: l3-3-cache { /* cluster private */ 618 compatible = "cache"; 619 cache-level = <3>; 620 cache-size = <0x200000>; /* 2MB */ 621 cache-line-size = <64>; 622 /* 16 ways set associativity */ 623 /* cache_size / (line_size/associativity) */ 624 cache-sets = <2048>; 625 cache-unified; 626 next-level-cache = <&llc>; 627 }; 628 629 llc: l4-cache { /* LLC inside CMN */ 630 compatible = "cache"; 631 cache-level = <4>; 632 cache-size = <0x1000000>; /* 16MB */ 633 cache-unified; 634 }; 635 636 idle-states { 637 entry-method = "psci"; 638 639 CPU_SLEEP_0: cpu-sleep-0 { 640 compatible = "arm,idle-state"; 641 arm,psci-suspend-param = <0x40000000>; 642 local-timer-stop; 643 entry-latency-us = <300>; 644 exit-latency-us = <600>; 645 min-residency-us = <10000>; 646 }; 647 }; 648 }; 649 650 cpu_opp_table: opp-table { 651 compatible = "operating-points-v2"; 652 opp-1066000000 { 653 opp-hz = /bits/ 64 <1066000000>; 654 opp-microvolt = <1000000>; 655 clock-latency-ns = <500000>; 656 }; 657 opp-1866000000 { 658 opp-hz = /bits/ 64 <1866000000>; 659 opp-microvolt = <1000000>; 660 clock-latency-ns = <500000>; 661 }; 662 opp-1900000000 { 663 opp-hz = /bits/ 64 <1900000000>; 664 opp-microvolt = <1000000>; 665 clock-latency-ns = <500000>; 666 }; 667 opp-1999000000 { 668 opp-hz = /bits/ 64 <1999000000>; 669 opp-microvolt = <1000000>; 670 clock-latency-ns = <500000>; 671 }; 672 opp-2050000000 { 673 opp-hz = /bits/ 64 <2050000000>; 674 opp-microvolt = <1000000>; 675 clock-latency-ns = <500000>; 676 }; 677 opp-2100000000 { 678 opp-hz = /bits/ 64 <2100000000>; 679 opp-microvolt = <1000000>; 680 clock-latency-ns = <500000>; 681 }; 682 opp-2200000000 { 683 opp-hz = /bits/ 64 <2200000000>; 684 opp-microvolt = <1000000>; 685 clock-latency-ns = <500000>; 686 }; 687 opp-2400000000 { 688 opp-hz = /bits/ 64 <2400000000>; 689 opp-microvolt = <1000000>; 690 clock-latency-ns = <500000>; 691 }; 692 }; 693 694 aliases { 695 serial0 = &serial0; 696 serial1 = &serial1; 697 serial2 = &dcc; 698 mmc0 = &sdhci0; 699 mmc1 = &sdhci1; 700 i2c0 = &i2c0; 701 i2c1 = &i2c1; 702 rtc = &rtc; 703 usb0 = &usb0; 704 usb1 = &usb1; 705 spi0 = &ospi; 706 spi1 = &qspi; 707 }; 708 709 dcc: dcc { 710 compatible = "arm,dcc"; 711 status = "disabled"; 712 bootph-all; 713 }; 714 715 firmware { 716 psci { 717 compatible = "arm,psci-1.0"; 718 method = "smc"; 719 }; 720 }; 721 722 fpga: fpga-region { 723 compatible = "fpga-region"; 724 fpga-mgr = <&versal_fpga>; 725 #address-cells = <2>; 726 #size-cells = <2>; 727 }; 728 729 timer: timer { 730 compatible = "arm,armv8-timer"; 731 interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; 732 }; 733 734 versal_fpga: versal-fpga { 735 compatible = "xlnx,versal-fpga"; 736 }; 737 738 amba: axi { 739 compatible = "simple-bus"; 740 bootph-all; 741 #address-cells = <2>; 742 #size-cells = <2>; 743 ranges; 744 745 adma0: dma-controller@ebd00000 { 746 compatible = "xlnx,zynqmp-dma-1.0"; 747 status = "disabled"; 748 reg = <0 0xebd00000 0 0x1000>; 749 interrupts = <0 72 4>; 750 clock-names = "clk_main", "clk_apb"; 751 #dma-cells = <1>; 752 xlnx,bus-width = <64>; 753 }; 754 755 adma1: dma-controller@ebd10000 { 756 compatible = "xlnx,zynqmp-dma-1.0"; 757 status = "disabled"; 758 reg = <0 0xebd10000 0 0x1000>; 759 interrupts = <0 73 4>; 760 clock-names = "clk_main", "clk_apb"; 761 #dma-cells = <1>; 762 xlnx,bus-width = <64>; 763 }; 764 765 adma2: dma-controller@ebd20000 { 766 compatible = "xlnx,zynqmp-dma-1.0"; 767 status = "disabled"; 768 reg = <0 0xebd20000 0 0x1000>; 769 interrupts = <0 74 4>; 770 clock-names = "clk_main", "clk_apb"; 771 #dma-cells = <1>; 772 xlnx,bus-width = <64>; 773 }; 774 775 adma3: dma-controller@ebd30000 { 776 compatible = "xlnx,zynqmp-dma-1.0"; 777 status = "disabled"; 778 reg = <0 0xebd30000 0 0x1000>; 779 interrupts = <0 75 4>; 780 clock-names = "clk_main", "clk_apb"; 781 #dma-cells = <1>; 782 xlnx,bus-width = <64>; 783 }; 784 785 adma4: dma-controller@ebd40000 { 786 compatible = "xlnx,zynqmp-dma-1.0"; 787 status = "disabled"; 788 reg = <0 0xebd40000 0 0x1000>; 789 interrupts = <0 76 4>; 790 clock-names = "clk_main", "clk_apb"; 791 #dma-cells = <1>; 792 xlnx,bus-width = <64>; 793 }; 794 795 adma5: dma-controller@ebd50000 { 796 compatible = "xlnx,zynqmp-dma-1.0"; 797 status = "disabled"; 798 reg = <0 0xebd50000 0 0x1000>; 799 interrupts = <0 77 4>; 800 clock-names = "clk_main", "clk_apb"; 801 #dma-cells = <1>; 802 xlnx,bus-width = <64>; 803 }; 804 805 adma6: dma-controller@ebd60000 { 806 compatible = "xlnx,zynqmp-dma-1.0"; 807 status = "disabled"; 808 reg = <0 0xebd60000 0 0x1000>; 809 interrupts = <0 78 4>; 810 clock-names = "clk_main", "clk_apb"; 811 #dma-cells = <1>; 812 xlnx,bus-width = <64>; 813 }; 814 815 adma7: dma-controller@ebd70000 { 816 compatible = "xlnx,zynqmp-dma-1.0"; 817 status = "disabled"; 818 reg = <0 0xebd70000 0 0x1000>; 819 interrupts = <0 79 4>; 820 clock-names = "clk_main", "clk_apb"; 821 #dma-cells = <1>; 822 xlnx,bus-width = <64>; 823 }; 824 825 can0: can@f1980000 { 826 compatible = "xlnx,canfd-2.0"; 827 status = "disabled"; 828 reg = <0 0xf1980000 0 0x6000>; 829 interrupts = <0 27 4>; 830 clock-names = "can_clk", "s_axi_aclk"; 831 rx-fifo-depth = <64>; 832 tx-mailbox-count = <32>; 833 }; 834 835 can1: can@f1990000 { 836 compatible = "xlnx,canfd-2.0"; 837 status = "disabled"; 838 reg = <0 0xf1990000 0 0x6000>; 839 interrupts = <0 28 4>; 840 clock-names = "can_clk", "s_axi_aclk"; 841 rx-fifo-depth = <64>; 842 tx-mailbox-count = <32>; 843 }; 844 845 gem0: ethernet@f19e0000 { 846 compatible = "xlnx,versal-gem", "cdns,gem"; 847 status = "disabled"; 848 reg = <0 0xf19e0000 0 0x1000>; 849 interrupts = <0 39 4>, <0 39 4>; 850 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", 851 "tsu_clk"; 852 }; 853 854 gem1: ethernet@f19f0000 { 855 compatible = "xlnx,versal-gem", "cdns,gem"; 856 status = "disabled"; 857 reg = <0 0xf19f0000 0 0x1000>; 858 interrupts = <0 41 4>, <0 41 4>; 859 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", 860 "tsu_clk"; 861 }; 862 863 gic: interrupt-controller@e2000000 { 864 compatible = "arm,gic-v3"; 865 #interrupt-cells = <3>; 866 reg = <0 0xe2000000 0 0x10000>, 867 <0 0xe2060000 0 0x200000>; 868 interrupt-controller; 869 interrupts = <1 9 4>; 870 #address-cells = <2>; 871 #size-cells = <2>; 872 ranges; 873 its: msi-controller@e2040000 { 874 compatible = "arm,gic-v3-its"; 875 msi-controller; 876 #msi-cells = <1>; 877 reg = <0 0xe2040000 0 0x20000>; 878 }; 879 }; 880 881 gpio0: gpio@f19d0000 { 882 compatible = "xlnx,versal-gpio-1.0"; 883 status = "disabled"; 884 reg = <0 0xf19d0000 0 0x1000>; 885 interrupts = <0 20 4>; 886 #gpio-cells = <2>; 887 gpio-controller; 888 #interrupt-cells = <2>; 889 interrupt-controller; 890 }; 891 892 gpio1: gpio@f1020000 { 893 compatible = "xlnx,pmc-gpio-1.0"; 894 status = "disabled"; 895 reg = <0 0xf1020000 0 0x1000>; 896 interrupts = <0 180 4>; 897 #gpio-cells = <2>; 898 gpio-controller; 899 #interrupt-cells = <2>; 900 interrupt-controller; 901 }; 902 903 i2c0: i2c@f1940000 { 904 compatible = "cdns,i2c-r1p14"; 905 status = "disabled"; 906 reg = <0 0xf1940000 0 0x1000>; 907 interrupts = <0 21 4>; 908 clock-frequency = <400000>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 }; 912 913 i2c1: i2c@f1950000 { 914 compatible = "cdns,i2c-r1p14"; 915 status = "disabled"; 916 reg = <0 0xf1950000 0 0x1000>; 917 interrupts = <0 22 4>; 918 clock-frequency = <400000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 }; 922 923 i3c0: i3c@f1948000 { 924 compatible = "snps,dw-i3c-master-1.00a"; 925 status = "disabled"; 926 reg = <0 0xf1948000 0 0x1000>; 927 #address-cells = <3>; 928 #size-cells = <0>; 929 interrupts = <0 21 4>; 930 }; 931 932 i3c1: i3c@f1958000 { 933 compatible = "snps,dw-i3c-master-1.00a"; 934 status = "disabled"; 935 reg = <0 0xf1958000 0 0x1000>; 936 #address-cells = <3>; 937 #size-cells = <0>; 938 interrupts = <0 22 4>; 939 }; 940 941 ospi: spi@f1010000 { 942 compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; 943 status = "disabled"; 944 reg = <0 0xf1010000 0 0x10000>, 945 <0 0xc0000000 0 0x20000000>; 946 interrupts = <0 182 4>; 947 cdns,fifo-depth = <256>; 948 cdns,fifo-width = <4>; 949 cdns,is-dma = <1>; /* u-boot specific */ 950 cdns,trigger-address = <0xc0000000>; 951 }; 952 953 qspi: spi@f1030000 { 954 compatible = "xlnx,versal-qspi-1.0"; 955 status = "disabled"; 956 reg = <0 0xf1030000 0 0x1000>; 957 interrupts = <0 183 4>; 958 clock-names = "ref_clk", "pclk"; 959 }; 960 961 rtc: rtc@f12a0000 { 962 compatible = "xlnx,zynqmp-rtc"; 963 status = "disabled"; 964 reg = <0 0xf12a0000 0 0x100>; 965 interrupts = <0 200 4>, <0 201 4>; 966 interrupt-names = "alarm", "sec"; 967 calibration = <0x7FFF>; 968 }; 969 970 sdhci0: mmc@f1040000 { 971 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; 972 status = "disabled"; 973 reg = <0 0xf1040000 0 0x10000>; 974 interrupts = <0 184 4>; 975 clock-names = "clk_xin", "clk_ahb", "gate"; 976 #clock-cells = <1>; 977 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 978 }; 979 980 sdhci1: mmc@f1050000 { 981 compatible = "xlnx,versal-net-emmc"; 982 status = "disabled"; 983 reg = <0 0xf1050000 0 0x10000>; 984 interrupts = <0 186 4>; 985 clock-names = "clk_xin", "clk_ahb", "gate"; 986 #clock-cells = <1>; 987 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 988 }; 989 990 serial0: serial@f1920000 { 991 bootph-all; 992 compatible = "arm,pl011", "arm,primecell"; 993 status = "disabled"; 994 reg = <0 0xf1920000 0 0x1000>; 995 interrupts = <0 25 4>; 996 reg-io-width = <4>; 997 clock-names = "uartclk", "apb_pclk"; 998 }; 999 1000 serial1: serial@f1930000 { 1001 bootph-all; 1002 compatible = "arm,pl011", "arm,primecell"; 1003 status = "disabled"; 1004 reg = <0 0xf1930000 0 0x1000>; 1005 interrupts = <0 26 4>; 1006 reg-io-width = <4>; 1007 clock-names = "uartclk", "apb_pclk"; 1008 }; 1009 1010 smmu: iommu@ec000000 { 1011 compatible = "arm,smmu-v3"; 1012 status = "disabled"; 1013 reg = <0 0xec000000 0 0x40000>; 1014 #iommu-cells = <1>; 1015 interrupt-names = "combined"; 1016 interrupts = <0 169 4>; 1017 dma-coherent; 1018 }; 1019 1020 spi0: spi@f1960000 { 1021 compatible = "cdns,spi-r1p6"; 1022 status = "disabled"; 1023 interrupts = <0 23 4>; 1024 reg = <0 0xf1960000 0 0x1000>; 1025 clock-names = "ref_clk", "pclk"; 1026 }; 1027 1028 spi1: spi@f1970000 { 1029 compatible = "cdns,spi-r1p6"; 1030 status = "disabled"; 1031 interrupts = <0 24 4>; 1032 reg = <0 0xf1970000 0 0x1000>; 1033 clock-names = "ref_clk", "pclk"; 1034 }; 1035 1036 ttc0: timer@f1dc0000 { 1037 compatible = "cdns,ttc"; 1038 status = "disabled"; 1039 interrupts = <0 43 4>, <0 44 4>, <0 45 4>; 1040 timer-width = <32>; 1041 reg = <0x0 0xf1dc0000 0x0 0x1000>; 1042 }; 1043 1044 ttc1: timer@f1dd0000 { 1045 compatible = "cdns,ttc"; 1046 status = "disabled"; 1047 interrupts = <0 46 4>, <0 47 4>, <0 48 4>; 1048 timer-width = <32>; 1049 reg = <0x0 0xf1dd0000 0x0 0x1000>; 1050 }; 1051 1052 ttc2: timer@f1de0000 { 1053 compatible = "cdns,ttc"; 1054 status = "disabled"; 1055 interrupts = <0 49 4>, <0 50 4>, <0 51 4>; 1056 timer-width = <32>; 1057 reg = <0x0 0xf1de0000 0x0 0x1000>; 1058 }; 1059 1060 ttc3: timer@f1df0000 { 1061 compatible = "cdns,ttc"; 1062 status = "disabled"; 1063 interrupts = <0 52 4>, <0 53 4>, <0 54 4>; 1064 timer-width = <32>; 1065 reg = <0x0 0xf1df0000 0x0 0x1000>; 1066 }; 1067 1068 usb0: usb@f1e00000 { 1069 compatible = "xlnx,versal-dwc3"; 1070 status = "disabled"; 1071 reg = <0 0xf1e00000 0 0x100>; 1072 clock-names = "bus_clk", "ref_clk"; 1073 ranges; 1074 #address-cells = <2>; 1075 #size-cells = <2>; 1076 1077 dwc3_0: usb@f1b00000 { 1078 compatible = "snps,dwc3"; 1079 status = "disabled"; 1080 reg = <0 0xf1b00000 0 0x10000>; 1081 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1082 interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; 1083 snps,dis_u2_susphy_quirk; 1084 snps,dis_u3_susphy_quirk; 1085 snps,quirk-frame-length-adjustment = <0x20>; 1086 dr_mode = "peripheral"; 1087 maximum-speed = "high-speed"; 1088 snps,usb3_lpm_capable; 1089 clock-names = "ref"; 1090 }; 1091 }; 1092 1093 usb1: usb@f1e10000 { 1094 compatible = "xlnx,versal-dwc3"; 1095 status = "disabled"; 1096 reg = <0x0 0xf1e10000 0x0 0x100>; 1097 clock-names = "bus_clk", "ref_clk"; 1098 ranges; 1099 #address-cells = <2>; 1100 #size-cells = <2>; 1101 1102 dwc3_1: usb@f1c00000 { 1103 compatible = "snps,dwc3"; 1104 status = "disabled"; 1105 reg = <0x0 0xf1c00000 0x0 0x10000>; 1106 interrupt-names = "host", "peripheral", "otg", "wakeup"; 1107 interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; 1108 snps,dis_u2_susphy_quirk; 1109 snps,dis_u3_susphy_quirk; 1110 snps,quirk-frame-length-adjustment = <0x20>; 1111 dr_mode = "host"; 1112 maximum-speed = "high-speed"; 1113 snps,usb3_lpm_capable; 1114 clock-names = "ref"; 1115 }; 1116 }; 1117 1118 wwdt0: watchdog@ecc10000 { 1119 compatible = "xlnx,versal-wwdt"; 1120 status = "disabled"; 1121 reg = <0 0xecc10000 0 0x10000>; 1122 timeout-sec = <30>; 1123 }; 1124 1125 wwdt1: watchdog@ecd10000 { 1126 compatible = "xlnx,versal-wwdt"; 1127 status = "disabled"; 1128 reg = <0 0xecd10000 0 0x10000>; 1129 timeout-sec = <30>; 1130 }; 1131 1132 wwdt2: watchdog@ece10000 { 1133 compatible = "xlnx,versal-wwdt"; 1134 status = "disabled"; 1135 reg = <0 0xece10000 0 0x10000>; 1136 timeout-sec = <30>; 1137 }; 1138 1139 wwdt3: watchdog@ecf10000 { 1140 compatible = "xlnx,versal-wwdt"; 1141 status = "disabled"; 1142 reg = <0 0xecf10000 0 0x10000>; 1143 timeout-sec = <30>; 1144 }; 1145 1146 lpd_wwdt0: watchdog@ea420000 { 1147 compatible = "xlnx,versal-wwdt"; 1148 status = "disabled"; 1149 reg = <0 0xea420000 0 0x10000>; 1150 timeout-sec = <30>; 1151 }; 1152 1153 lpd_wwdt1: watchdog@ea430000 { 1154 compatible = "xlnx,versal-wwdt"; 1155 status = "disabled"; 1156 reg = <0 0xea430000 0 0x10000>; 1157 timeout-sec = <30>; 1158 }; 1159 }; 1160};
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