versal-net-clk.dtsi

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * dts file for Xilinx Versal NET fixed clock
  4 *
  5 * (C) Copyright 2022, Xilinx, Inc.
  6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
  7 *
  8 * Michal Simek <michal.simek@amd.com>
  9 */
 10
 11/ {
 12	clk60: clk60 {
 13		compatible = "fixed-clock";
 14		#clock-cells = <0>;
 15		clock-frequency = <60000000>;
 16	};
 17
 18	clk100: clk100 {
 19		compatible = "fixed-clock";
 20		#clock-cells = <0>;
 21		clock-frequency = <100000000>;
 22	};
 23
 24	clk125: clk125 {
 25		compatible = "fixed-clock";
 26		#clock-cells = <0>;
 27		clock-frequency = <125000000>;
 28	};
 29
 30	clk150: clk150 {
 31		compatible = "fixed-clock";
 32		#clock-cells = <0>;
 33		clock-frequency = <150000000>;
 34	};
 35
 36	clk160: clk160 {
 37		compatible = "fixed-clock";
 38		#clock-cells = <0>;
 39		clock-frequency = <160000000>;
 40	};
 41
 42	clk200: clk200 {
 43		compatible = "fixed-clock";
 44		#clock-cells = <0>;
 45		clock-frequency = <200000000>;
 46	};
 47
 48	clk250: clk250 {
 49		compatible = "fixed-clock";
 50		#clock-cells = <0>;
 51		clock-frequency = <250000000>;
 52	};
 53
 54	clk300: clk300 {
 55		compatible = "fixed-clock";
 56		#clock-cells = <0>;
 57		clock-frequency = <300000000>;
 58	};
 59
 60	clk450: clk450 {
 61		compatible = "fixed-clock";
 62		#clock-cells = <0>;
 63		clock-frequency = <450000000>;
 64	};
 65
 66	clk1200: clk1200 {
 67		compatible = "fixed-clock";
 68		#clock-cells = <0>;
 69		clock-frequency = <1200000000>;
 70	};
 71
 72	firmware {
 73		versal_net_firmware: versal-net-firmware {
 74			compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
 75			bootph-all;
 76			method = "smc";
 77		};
 78	};
 79};
 80
 81&adma0 {
 82	clocks = <&clk450>, <&clk450>;
 83};
 84
 85&adma1 {
 86	clocks = <&clk450>, <&clk450>;
 87};
 88
 89&adma2 {
 90	clocks = <&clk450>, <&clk450>;
 91};
 92
 93&adma3 {
 94	clocks = <&clk450>, <&clk450>;
 95};
 96
 97&adma4 {
 98	clocks = <&clk450>, <&clk450>;
 99};
100
101&adma5 {
102	clocks = <&clk450>, <&clk450>;
103};
104
105&adma6 {
106	clocks = <&clk450>, <&clk450>;
107};
108
109&adma7 {
110	clocks = <&clk450>, <&clk450>;
111};
112
113&can0 {
114	clocks = <&clk160>, <&clk160>;
115};
116
117&can1 {
118	clocks = <&clk160>, <&clk160>;
119};
120
121&gem0 {
122	clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
123};
124
125&gem1 {
126	clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
127};
128
129&gpio0 {
130	clocks = <&clk100>;
131};
132
133&gpio1 {
134	clocks = <&clk100>;
135};
136
137&i2c0 {
138	clocks = <&clk100>;
139};
140
141&i2c1 {
142	clocks = <&clk100>;
143};
144
145&i3c0 {
146	clocks = <&clk100>;
147};
148
149&i3c1 {
150	clocks = <&clk100>;
151};
152
153&ospi {
154	clocks = <&clk200>;
155};
156
157&qspi {
158	clocks = <&clk300>, <&clk300>;
159};
160
161&rtc {
162	/* Nothing */
163};
164
165&sdhci0 {
166	clocks = <&clk200>, <&clk200>, <&clk1200>;
167};
168
169&sdhci1 {
170	clocks = <&clk200>, <&clk200>, <&clk1200>;
171};
172
173&serial0 {
174	clocks = <&clk100>, <&clk100>;
175};
176
177&serial1 {
178	clocks = <&clk100>, <&clk100>;
179};
180
181&spi0 {
182	clocks = <&clk200>, <&clk200>;
183};
184
185&spi1 {
186	clocks = <&clk200>, <&clk200>;
187};
188
189&ttc0 {
190	clocks = <&clk150>;
191};
192
193&usb0 {
194	clocks = <&clk60>, <&clk60>;
195};
196
197&dwc3_0 {
198	clocks = <&clk60>;
199};
200
201&usb1 {
202	clocks = <&clk60>, <&clk60>;
203};
204
205&dwc3_1 {
206	clocks = <&clk60>;
207};
208
209&wwdt0 {
210	clocks = <&clk150>;
211};
212
213&wwdt1 {
214	clocks = <&clk150>;
215};
216
217&wwdt2 {
218	clocks = <&clk150>;
219};
220
221&wwdt3 {
222	clocks = <&clk150>;
223};
224
225&lpd_wwdt0 {
226	clocks = <&clk150>;
227};
228
229&lpd_wwdt1 {
230	clocks = <&clk150>;
231};