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k3-serdes.h

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linux-6.19.14/arch/arm64/boot/dts/ti/k3-serdes.h C 
  1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
  2/*
  3 * This header provides constants for SERDES MUX for TI SoCs
  4 *
  5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#ifndef DTS_ARM64_TI_K3_SERDES_H
  9#define DTS_ARM64_TI_K3_SERDES_H
 10
 11/* J721E */
 12
 13#define J721E_SERDES0_LANE0_QSGMII_LANE1	0x0
 14#define J721E_SERDES0_LANE0_PCIE0_LANE0		0x1
 15#define J721E_SERDES0_LANE0_USB3_0_SWAP		0x2
 16#define J721E_SERDES0_LANE0_IP4_UNUSED		0x3
 17
 18#define J721E_SERDES0_LANE1_QSGMII_LANE2	0x0
 19#define J721E_SERDES0_LANE1_PCIE0_LANE1		0x1
 20#define J721E_SERDES0_LANE1_USB3_0		0x2
 21#define J721E_SERDES0_LANE1_IP4_UNUSED		0x3
 22
 23#define J721E_SERDES1_LANE0_QSGMII_LANE3	0x0
 24#define J721E_SERDES1_LANE0_PCIE1_LANE0		0x1
 25#define J721E_SERDES1_LANE0_USB3_1_SWAP		0x2
 26#define J721E_SERDES1_LANE0_SGMII_LANE0		0x3
 27
 28#define J721E_SERDES1_LANE1_QSGMII_LANE4	0x0
 29#define J721E_SERDES1_LANE1_PCIE1_LANE1		0x1
 30#define J721E_SERDES1_LANE1_USB3_1		0x2
 31#define J721E_SERDES1_LANE1_SGMII_LANE1		0x3
 32
 33#define J721E_SERDES2_LANE0_IP1_UNUSED		0x0
 34#define J721E_SERDES2_LANE0_PCIE2_LANE0		0x1
 35#define J721E_SERDES2_LANE0_USB3_1_SWAP		0x2
 36#define J721E_SERDES2_LANE0_SGMII_LANE0		0x3
 37
 38#define J721E_SERDES2_LANE1_IP1_UNUSED		0x0
 39#define J721E_SERDES2_LANE1_PCIE2_LANE1		0x1
 40#define J721E_SERDES2_LANE1_USB3_1		0x2
 41#define J721E_SERDES2_LANE1_SGMII_LANE1		0x3
 42
 43#define J721E_SERDES3_LANE0_IP1_UNUSED		0x0
 44#define J721E_SERDES3_LANE0_PCIE3_LANE0		0x1
 45#define J721E_SERDES3_LANE0_USB3_0_SWAP		0x2
 46#define J721E_SERDES3_LANE0_IP4_UNUSED		0x3
 47
 48#define J721E_SERDES3_LANE1_IP1_UNUSED		0x0
 49#define J721E_SERDES3_LANE1_PCIE3_LANE1		0x1
 50#define J721E_SERDES3_LANE1_USB3_0		0x2
 51#define J721E_SERDES3_LANE1_IP4_UNUSED		0x3
 52
 53#define J721E_SERDES4_LANE0_EDP_LANE0		0x0
 54#define J721E_SERDES4_LANE0_IP2_UNUSED		0x1
 55#define J721E_SERDES4_LANE0_QSGMII_LANE5	0x2
 56#define J721E_SERDES4_LANE0_IP4_UNUSED		0x3
 57
 58#define J721E_SERDES4_LANE1_EDP_LANE1		0x0
 59#define J721E_SERDES4_LANE1_IP2_UNUSED		0x1
 60#define J721E_SERDES4_LANE1_QSGMII_LANE6	0x2
 61#define J721E_SERDES4_LANE1_IP4_UNUSED		0x3
 62
 63#define J721E_SERDES4_LANE2_EDP_LANE2		0x0
 64#define J721E_SERDES4_LANE2_IP2_UNUSED		0x1
 65#define J721E_SERDES4_LANE2_QSGMII_LANE7	0x2
 66#define J721E_SERDES4_LANE2_IP4_UNUSED		0x3
 67
 68#define J721E_SERDES4_LANE3_EDP_LANE3		0x0
 69#define J721E_SERDES4_LANE3_IP2_UNUSED		0x1
 70#define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
 71#define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
 72
 73/* J7200 */
 74
 75#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
 76#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
 77#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
 78#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
 79
 80#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
 81#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
 82#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
 83#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
 84
 85#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
 86#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
 87#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
 88#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
 89
 90#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
 91#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
 92#define J7200_SERDES0_LANE3_USB			0x2
 93#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
 94
 95/* AM64 */
 96
 97#define AM64_SERDES0_LANE0_PCIE0		0x0
 98#define AM64_SERDES0_LANE0_USB			0x1
 99
100/* J721S2 */
101
102#define J721S2_SERDES0_LANE0_EDP_LANE0		0x0
103#define J721S2_SERDES0_LANE0_PCIE1_LANE0	0x1
104#define J721S2_SERDES0_LANE0_IP3_UNUSED		0x2
105#define J721S2_SERDES0_LANE0_IP4_UNUSED		0x3
106
107#define J721S2_SERDES0_LANE1_EDP_LANE1		0x0
108#define J721S2_SERDES0_LANE1_PCIE1_LANE1	0x1
109#define J721S2_SERDES0_LANE1_USB		0x2
110#define J721S2_SERDES0_LANE1_IP4_UNUSED		0x3
111
112#define J721S2_SERDES0_LANE2_EDP_LANE2		0x0
113#define J721S2_SERDES0_LANE2_PCIE1_LANE2	0x1
114#define J721S2_SERDES0_LANE2_USB_SWAP		0x2
115#define J721S2_SERDES0_LANE2_IP4_UNUSED		0x3
116
117#define J721S2_SERDES0_LANE3_EDP_LANE3		0x0
118#define J721S2_SERDES0_LANE3_PCIE1_LANE3	0x1
119#define J721S2_SERDES0_LANE3_USB		0x2
120#define J721S2_SERDES0_LANE3_IP4_UNUSED		0x3
121
122/* J784S4 */
123
124#define J784S4_SERDES0_LANE0_IP1_UNUSED		0x0
125#define J784S4_SERDES0_LANE0_PCIE1_LANE0	0x1
126#define J784S4_SERDES0_LANE0_IP3_UNUSED		0x2
127#define J784S4_SERDES0_LANE0_IP4_UNUSED		0x3
128
129#define J784S4_SERDES0_LANE1_IP1_UNUSED		0x0
130#define J784S4_SERDES0_LANE1_PCIE1_LANE1	0x1
131#define J784S4_SERDES0_LANE1_IP3_UNUSED		0x2
132#define J784S4_SERDES0_LANE1_IP4_UNUSED		0x3
133
134#define J784S4_SERDES0_LANE2_PCIE3_LANE0	0x0
135#define J784S4_SERDES0_LANE2_PCIE1_LANE2	0x1
136#define J784S4_SERDES0_LANE2_IP3_UNUSED		0x2
137#define J784S4_SERDES0_LANE2_IP4_UNUSED		0x3
138
139#define J784S4_SERDES0_LANE3_PCIE3_LANE1	0x0
140#define J784S4_SERDES0_LANE3_PCIE1_LANE3	0x1
141#define J784S4_SERDES0_LANE3_USB		0x2
142#define J784S4_SERDES0_LANE3_IP4_UNUSED		0x3
143
144#define J784S4_SERDES1_LANE0_QSGMII_LANE3	0x0
145#define J784S4_SERDES1_LANE0_PCIE0_LANE0	0x1
146#define J784S4_SERDES1_LANE0_IP3_UNUSED		0x2
147#define J784S4_SERDES1_LANE0_IP4_UNUSED		0x3
148
149#define J784S4_SERDES1_LANE1_QSGMII_LANE4	0x0
150#define J784S4_SERDES1_LANE1_PCIE0_LANE1	0x1
151#define J784S4_SERDES1_LANE1_IP3_UNUSED		0x2
152#define J784S4_SERDES1_LANE1_IP4_UNUSED		0x3
153
154#define J784S4_SERDES1_LANE2_QSGMII_LANE1	0x0
155#define J784S4_SERDES1_LANE2_PCIE0_LANE2	0x1
156#define J784S4_SERDES1_LANE2_PCIE2_LANE0	0x2
157#define J784S4_SERDES1_LANE2_IP4_UNUSED		0x3
158
159#define J784S4_SERDES1_LANE3_QSGMII_LANE2	0x0
160#define J784S4_SERDES1_LANE3_PCIE0_LANE3	0x1
161#define J784S4_SERDES1_LANE3_PCIE2_LANE1	0x2
162#define J784S4_SERDES1_LANE3_IP4_UNUSED		0x3
163
164#define J784S4_SERDES2_LANE0_QSGMII_LANE5	0x0
165#define J784S4_SERDES2_LANE0_IP2_UNUSED		0x1
166#define J784S4_SERDES2_LANE0_IP3_UNUSED		0x2
167#define J784S4_SERDES2_LANE0_IP4_UNUSED		0x3
168
169#define J784S4_SERDES2_LANE1_QSGMII_LANE6	0x0
170#define J784S4_SERDES2_LANE1_IP2_UNUSED		0x1
171#define J784S4_SERDES2_LANE1_IP3_UNUSED		0x2
172#define J784S4_SERDES2_LANE1_IP4_UNUSED		0x3
173
174#define J784S4_SERDES2_LANE2_QSGMII_LANE7	0x0
175#define J784S4_SERDES2_LANE2_QSGMII_LANE1	0x1
176#define J784S4_SERDES2_LANE2_IP3_UNUSED		0x2
177#define J784S4_SERDES2_LANE2_IP4_UNUSED		0x3
178
179#define J784S4_SERDES2_LANE3_QSGMII_LANE8	0x0
180#define J784S4_SERDES2_LANE3_QSGMII_LANE2	0x1
181#define J784S4_SERDES2_LANE3_IP3_UNUSED		0x2
182#define J784S4_SERDES2_LANE3_IP4_UNUSED		0x3
183
184#define J784S4_SERDES4_LANE0_EDP_LANE0		0x0
185#define J784S4_SERDES4_LANE0_QSGMII_LANE5	0x1
186#define J784S4_SERDES4_LANE0_IP3_UNUSED		0x2
187#define J784S4_SERDES4_LANE0_IP4_UNUSED		0x3
188
189#define J784S4_SERDES4_LANE1_EDP_LANE1		0x0
190#define J784S4_SERDES4_LANE1_QSGMII_LANE6	0x1
191#define J784S4_SERDES4_LANE1_IP3_UNUSED		0x2
192#define J784S4_SERDES4_LANE1_IP4_UNUSED		0x3
193
194#define J784S4_SERDES4_LANE2_EDP_LANE2		0x0
195#define J784S4_SERDES4_LANE2_QSGMII_LANE7	0x1
196#define J784S4_SERDES4_LANE2_IP3_UNUSED		0x2
197#define J784S4_SERDES4_LANE2_IP4_UNUSED		0x3
198
199#define J784S4_SERDES4_LANE3_EDP_LANE3		0x0
200#define J784S4_SERDES4_LANE3_QSGMII_LANE8	0x1
201#define J784S4_SERDES4_LANE3_USB		0x2
202#define J784S4_SERDES4_LANE3_IP4_UNUSED		0x3
203
204/* J722S */
205
206#define J722S_SERDES0_LANE0_USB			0x0
207#define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
208
209#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
210#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
211
212#endif /* DTS_ARM64_TI_K3_SERDES_H */
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