k3-pinctrl.h

  1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
  2/*
  3 * This header provides constants for pinctrl bindings for TI's K3 SoC
  4 * family.
  5 *
  6 * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
  7 */
  8#ifndef DTS_ARM64_TI_K3_PINCTRL_H
  9#define DTS_ARM64_TI_K3_PINCTRL_H
 10
 11#define WKUP_LVL_EN_SHIFT       (7)
 12#define WKUP_LVL_POL_SHIFT      (8)
 13#define ST_EN_SHIFT		(14)
 14#define PULLUDEN_SHIFT		(16)
 15#define PULLTYPESEL_SHIFT	(17)
 16#define RXACTIVE_SHIFT		(18)
 17#define DRV_STR_SHIFT           (19)
 18#define ISO_OVERRIDE_EN_SHIFT   (22)
 19#define ISO_BYPASS_EN_SHIFT     (23)
 20#define DEBOUNCE_SHIFT		(11)
 21#define FORCE_DS_EN_SHIFT	(15)
 22#define DS_EN_SHIFT		(24)
 23#define DS_OUT_DIS_SHIFT	(25)
 24#define DS_OUT_VAL_SHIFT	(26)
 25#define DS_PULLUD_EN_SHIFT	(27)
 26#define DS_PULLTYPE_SEL_SHIFT	(28)
 27#define WKUP_EN_SHIFT           (29)
 28
 29/* Schmitt trigger configuration */
 30#define ST_DISABLE		(0 << ST_EN_SHIFT)
 31#define ST_ENABLE		(1 << ST_EN_SHIFT)
 32
 33#define PULL_DISABLE		(1 << PULLUDEN_SHIFT)
 34#define PULL_ENABLE		(0 << PULLUDEN_SHIFT)
 35
 36#define PULL_UP			(1 << PULLTYPESEL_SHIFT | PULL_ENABLE)
 37#define PULL_DOWN		(0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
 38
 39#define INPUT_EN		(1 << RXACTIVE_SHIFT)
 40#define INPUT_DISABLE		(0 << RXACTIVE_SHIFT)
 41
 42#define DS_PULL_DISABLE         (1 << DS_PULLUD_EN_SHIFT)
 43#define DS_PULL_ENABLE          (0 << DS_PULLUD_EN_SHIFT)
 44
 45#define DS_PULL_UP              (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE)
 46#define DS_PULL_DOWN            (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE)
 47
 48#define DS_STATE_EN             (1 << DS_EN_SHIFT)
 49#define DS_STATE_DISABLE        (0 << DS_EN_SHIFT)
 50
 51#define DS_INPUT_EN             (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN)
 52#define DS_INPUT_DISABLE        (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN)
 53
 54#define DS_OUT_VALUE_ZERO       (0 << DS_OUT_VAL_SHIFT)
 55#define DS_OUT_VALUE_ONE        (1 << DS_OUT_VAL_SHIFT)
 56
 57/* Configuration to enable wake-up on pin activity */
 58#define WKUP_ENABLE             (1 << WKUP_EN_SHIFT)
 59#define WKUP_DISABLE            (0 << WKUP_EN_SHIFT)
 60#define WKUP_ON_LEVEL           (1 << WKUP_LVL_EN_SHIFT)
 61#define WKUP_ON_EDGE            (0 << WKUP_LVL_EN_SHIFT)
 62#define WKUP_LEVEL_LOW          (0 << WKUP_LVL_POL_SHIFT)
 63#define WKUP_LEVEL_HIGH         (1 << WKUP_LVL_POL_SHIFT)
 64
 65/* Only these macros are expected be used directly in device tree files */
 66#define PIN_OUTPUT		(INPUT_DISABLE | PULL_DISABLE)
 67#define PIN_OUTPUT_PULLUP	(INPUT_DISABLE | PULL_UP)
 68#define PIN_OUTPUT_PULLDOWN	(INPUT_DISABLE | PULL_DOWN)
 69#define PIN_INPUT		(INPUT_EN | ST_ENABLE | PULL_DISABLE)
 70#define PIN_INPUT_PULLUP	(INPUT_EN | ST_ENABLE | PULL_UP)
 71#define PIN_INPUT_PULLDOWN	(INPUT_EN | ST_ENABLE | PULL_DOWN)
 72/* Input configurations with Schmitt Trigger disabled */
 73#define PIN_INPUT_NOST		(INPUT_EN | PULL_DISABLE)
 74#define PIN_INPUT_PULLUP_NOST	(INPUT_EN | PULL_UP)
 75#define PIN_INPUT_PULLDOWN_NOST	(INPUT_EN | PULL_DOWN)
 76
 77#define PIN_DEBOUNCE_DISABLE	(0 << DEBOUNCE_SHIFT)
 78#define PIN_DEBOUNCE_CONF1	(1 << DEBOUNCE_SHIFT)
 79#define PIN_DEBOUNCE_CONF2	(2 << DEBOUNCE_SHIFT)
 80#define PIN_DEBOUNCE_CONF3	(3 << DEBOUNCE_SHIFT)
 81#define PIN_DEBOUNCE_CONF4	(4 << DEBOUNCE_SHIFT)
 82#define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
 83#define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
 84
 85#define PIN_DRIVE_STRENGTH_NOMINAL      (0 << DRV_STR_SHIFT)
 86#define PIN_DRIVE_STRENGTH_SLOW         (1 << DRV_STR_SHIFT)
 87#define PIN_DRIVE_STRENGTH_FAST         (2 << DRV_STR_SHIFT)
 88
 89#define PIN_DS_FORCE_DISABLE		(0 << FORCE_DS_EN_SHIFT)
 90#define PIN_DS_FORCE_ENABLE		(1 << FORCE_DS_EN_SHIFT)
 91#define PIN_DS_ISO_OVERRIDE_DISABLE     (0 << ISO_OVERRIDE_EN_SHIFT)
 92#define PIN_DS_ISO_OVERRIDE_ENABLE      (1 << ISO_OVERRIDE_EN_SHIFT)
 93#define PIN_DS_OUT_ENABLE		(0 << DS_OUT_DIS_SHIFT)
 94#define PIN_DS_OUT_DISABLE		(1 << DS_OUT_DIS_SHIFT)
 95#define PIN_DS_OUT_VALUE_ZERO		(0 << DS_OUT_VAL_SHIFT)
 96#define PIN_DS_OUT_VALUE_ONE		(1 << DS_OUT_VAL_SHIFT)
 97#define PIN_DS_PULLUD_ENABLE		(0 << DS_PULLUD_EN_SHIFT)
 98#define PIN_DS_PULLUD_DISABLE		(1 << DS_PULLUD_EN_SHIFT)
 99#define PIN_DS_PULL_DOWN		(0 << DS_PULLTYPE_SEL_SHIFT)
100#define PIN_DS_PULL_UP			(1 << DS_PULLTYPE_SEL_SHIFT)
101#define PIN_DS_ISO_BYPASS               (1 << ISO_BYPASS_EN_SHIFT)
102#define PIN_DS_ISO_BYPASS_DISABLE       (0 << ISO_BYPASS_EN_SHIFT)
103
104#define PIN_DS_OUTPUT_LOW               (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO)
105#define PIN_DS_OUTPUT_HIGH              (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE)
106#define PIN_DS_INPUT                    (DS_INPUT_EN | DS_PULL_DISABLE)
107#define PIN_DS_INPUT_PULLUP             (DS_INPUT_EN | DS_PULL_UP)
108#define PIN_DS_INPUT_PULLDOWN           (DS_INPUT_EN | DS_PULL_DOWN)
109
110#define PIN_WKUP_EN_LEVEL_LOW           (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW)
111#define PIN_WKUP_EN_LEVEL_HIGH          (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
112#define PIN_WKUP_EN                     (WKUP_ENABLE | WKUP_ON_EDGE)
113
114/* Default mux configuration for gpio-ranges to use with pinctrl */
115#define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
116
117#define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
118#define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
119
120#define AM62DX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
121#define AM62DX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
122
123#define AM62PX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
124#define AM62PX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
125
126#define AM62LX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
127
128#define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
129#define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
130
131#define AM64X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
132#define AM64X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
133
134#define AM65X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
135#define AM65X_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
136
137#define J721E_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
138#define J721E_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
139
140#define J721S2_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
141#define J721S2_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
142
143#define J722S_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
144#define J722S_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
145
146#define J784S4_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
147#define J784S4_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
148
149#endif