FILE
k3-j784s4-j742s2-mcu-wakeup-common.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 bootph-all; 23 compatible = "ti,sci-pm-domain"; 24 #power-domain-cells = <2>; 25 }; 26 27 k3_clks: clock-controller { 28 bootph-all; 29 compatible = "ti,k2g-sci-clk"; 30 #clock-cells = <2>; 31 }; 32 33 k3_reset: reset-controller { 34 bootph-all; 35 compatible = "ti,sci-reset"; 36 #reset-cells = <2>; 37 }; 38 }; 39 40 wkup_conf: bus@43000000 { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x00 0x43000000 0x20000>; 45 46 chipid: chipid@14 { 47 bootph-all; 48 compatible = "ti,am654-chipid"; 49 reg = <0x14 0x4>; 50 }; 51 }; 52 53 secure_proxy_sa3: mailbox@43600000 { 54 compatible = "ti,am654-secure-proxy"; 55 #mbox-cells = <1>; 56 reg-names = "target_data", "rt", "scfg"; 57 reg = <0x00 0x43600000 0x00 0x10000>, 58 <0x00 0x44880000 0x00 0x20000>, 59 <0x00 0x44860000 0x00 0x20000>; 60 bootph-pre-ram; 61 62 /* 63 * Marked Disabled: 64 * Node is incomplete as it is meant for bootloaders and 65 * firmware on non-MPU processors 66 */ 67 status = "disabled"; 68 }; 69 70 mcu_ram: sram@41c00000 { 71 compatible = "mmio-sram"; 72 reg = <0x00 0x41c00000 0x00 0x100000>; 73 ranges = <0x00 0x00 0x41c00000 0x100000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 }; 77 78 wkup_pmx0: pinctrl@4301c000 { 79 compatible = "ti,j7200-padconf", "pinctrl-single"; 80 /* Proxy 0 addressing */ 81 reg = <0x00 0x4301c000 0x00 0x034>; 82 #pinctrl-cells = <1>; 83 pinctrl-single,register-width = <32>; 84 pinctrl-single,function-mask = <0xffffffff>; 85 }; 86 87 wkup_pmx1: pinctrl@4301c038 { 88 compatible = "ti,j7200-padconf", "pinctrl-single"; 89 /* Proxy 0 addressing */ 90 reg = <0x00 0x4301c038 0x00 0x02c>; 91 #pinctrl-cells = <1>; 92 pinctrl-single,register-width = <32>; 93 pinctrl-single,function-mask = <0xffffffff>; 94 }; 95 96 wkup_pmx2: pinctrl@4301c068 { 97 compatible = "ti,j7200-padconf", "pinctrl-single"; 98 /* Proxy 0 addressing */ 99 reg = <0x00 0x4301c068 0x00 0x120>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <32>; 102 pinctrl-single,function-mask = <0xffffffff>; 103 }; 104 105 wkup_pmx3: pinctrl@4301c190 { 106 compatible = "ti,j7200-padconf", "pinctrl-single"; 107 /* Proxy 0 addressing */ 108 reg = <0x00 0x4301c190 0x00 0x004>; 109 #pinctrl-cells = <1>; 110 pinctrl-single,register-width = <32>; 111 pinctrl-single,function-mask = <0xffffffff>; 112 }; 113 114 wkup_gpio_intr: interrupt-controller@42200000 { 115 compatible = "ti,sci-intr"; 116 reg = <0x00 0x42200000 0x00 0x400>; 117 ti,intr-trigger-type = <1>; 118 interrupt-controller; 119 interrupt-parent = <&gic500>; 120 #interrupt-cells = <1>; 121 ti,sci = <&sms>; 122 ti,sci-dev-id = <177>; 123 ti,interrupt-ranges = <16 960 16>; 124 }; 125 126 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 127 mcu_timerio_input: pinctrl@40f04200 { 128 compatible = "ti,j7200-padconf", "pinctrl-single"; 129 reg = <0x00 0x40f04200 0x00 0x28>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x0000000f>; 133 /* Non-MPU Firmware usage */ 134 status = "reserved"; 135 }; 136 137 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 138 mcu_timerio_output: pinctrl@40f04280 { 139 compatible = "ti,j7200-padconf", "pinctrl-single"; 140 reg = <0x00 0x40f04280 0x00 0x28>; 141 #pinctrl-cells = <1>; 142 pinctrl-single,register-width = <32>; 143 pinctrl-single,function-mask = <0x0000000f>; 144 /* Non-MPU Firmware usage */ 145 status = "reserved"; 146 }; 147 148 mcu_conf: bus@40f00000 { 149 compatible = "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0x0 0x40f00000 0x20000>; 153 154 cpsw_mac_syscon: ethernet-mac-syscon@200 { 155 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 156 reg = <0x200 0x8>; 157 }; 158 159 phy_gmii_sel: phy@4040 { 160 compatible = "ti,am654-phy-gmii-sel"; 161 reg = <0x4040 0x4>; 162 #phy-cells = <1>; 163 }; 164 }; 165 166 mcu_timer0: timer@40400000 { 167 compatible = "ti,am654-timer"; 168 reg = <0x00 0x40400000 0x00 0x400>; 169 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&k3_clks 35 2>; 171 clock-names = "fck"; 172 assigned-clocks = <&k3_clks 35 2>; 173 assigned-clock-parents = <&k3_clks 35 3>; 174 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 175 bootph-all; 176 ti,timer-pwm; 177 /* Non-MPU Firmware usage */ 178 status = "reserved"; 179 }; 180 181 mcu_timer1: timer@40410000 { 182 compatible = "ti,am654-timer"; 183 reg = <0x00 0x40410000 0x00 0x400>; 184 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&k3_clks 117 2>; 186 clock-names = "fck"; 187 assigned-clocks = <&k3_clks 117 2>; 188 assigned-clock-parents = <&k3_clks 117 3>; 189 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; 190 ti,timer-pwm; 191 /* Non-MPU Firmware usage */ 192 status = "reserved"; 193 }; 194 195 mcu_timer2: timer@40420000 { 196 compatible = "ti,am654-timer"; 197 reg = <0x00 0x40420000 0x00 0x400>; 198 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&k3_clks 118 2>; 200 clock-names = "fck"; 201 assigned-clocks = <&k3_clks 118 2>; 202 assigned-clock-parents = <&k3_clks 118 3>; 203 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; 204 ti,timer-pwm; 205 /* Non-MPU Firmware usage */ 206 status = "reserved"; 207 }; 208 209 mcu_timer3: timer@40430000 { 210 compatible = "ti,am654-timer"; 211 reg = <0x00 0x40430000 0x00 0x400>; 212 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&k3_clks 119 2>; 214 clock-names = "fck"; 215 assigned-clocks = <&k3_clks 119 2>; 216 assigned-clock-parents = <&k3_clks 119 3>; 217 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 218 ti,timer-pwm; 219 /* Non-MPU Firmware usage */ 220 status = "reserved"; 221 }; 222 223 mcu_timer4: timer@40440000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x40440000 0x00 0x400>; 226 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 120 2>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 120 2>; 230 assigned-clock-parents = <&k3_clks 120 3>; 231 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 /* Non-MPU Firmware usage */ 234 status = "reserved"; 235 }; 236 237 mcu_timer5: timer@40450000 { 238 compatible = "ti,am654-timer"; 239 reg = <0x00 0x40450000 0x00 0x400>; 240 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&k3_clks 121 2>; 242 clock-names = "fck"; 243 assigned-clocks = <&k3_clks 121 2>; 244 assigned-clock-parents = <&k3_clks 121 3>; 245 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 246 ti,timer-pwm; 247 /* Non-MPU Firmware usage */ 248 status = "reserved"; 249 }; 250 251 mcu_timer6: timer@40460000 { 252 compatible = "ti,am654-timer"; 253 reg = <0x00 0x40460000 0x00 0x400>; 254 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&k3_clks 122 2>; 256 clock-names = "fck"; 257 assigned-clocks = <&k3_clks 122 2>; 258 assigned-clock-parents = <&k3_clks 122 3>; 259 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; 260 ti,timer-pwm; 261 /* Non-MPU Firmware usage */ 262 status = "reserved"; 263 }; 264 265 mcu_timer7: timer@40470000 { 266 compatible = "ti,am654-timer"; 267 reg = <0x00 0x40470000 0x00 0x400>; 268 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&k3_clks 123 2>; 270 clock-names = "fck"; 271 assigned-clocks = <&k3_clks 123 2>; 272 assigned-clock-parents = <&k3_clks 123 3>; 273 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; 274 ti,timer-pwm; 275 /* Non-MPU Firmware usage */ 276 status = "reserved"; 277 }; 278 279 mcu_timer8: timer@40480000 { 280 compatible = "ti,am654-timer"; 281 reg = <0x00 0x40480000 0x00 0x400>; 282 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&k3_clks 124 2>; 284 clock-names = "fck"; 285 assigned-clocks = <&k3_clks 124 2>; 286 assigned-clock-parents = <&k3_clks 124 3>; 287 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; 288 ti,timer-pwm; 289 /* Non-MPU Firmware usage */ 290 status = "reserved"; 291 }; 292 293 mcu_timer9: timer@40490000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x40490000 0x00 0x400>; 296 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 125 2>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 125 2>; 300 assigned-clock-parents = <&k3_clks 125 3>; 301 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 /* Non-MPU Firmware usage */ 304 status = "reserved"; 305 }; 306 307 wkup_uart0: serial@42300000 { 308 compatible = "ti,j721e-uart", "ti,am654-uart"; 309 reg = <0x00 0x42300000 0x00 0x200>; 310 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 397 0>; 312 clock-names = "fclk"; 313 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; 314 status = "disabled"; 315 }; 316 317 mcu_uart0: serial@40a00000 { 318 compatible = "ti,j721e-uart", "ti,am654-uart"; 319 reg = <0x00 0x40a00000 0x00 0x200>; 320 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 149 0>; 322 clock-names = "fclk"; 323 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 324 status = "disabled"; 325 }; 326 327 wkup_gpio0: gpio@42110000 { 328 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 329 reg = <0x00 0x42110000 0x00 0x100>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-parent = <&wkup_gpio_intr>; 333 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 ti,ngpio = <89>; 337 ti,davinci-gpio-unbanked = <0>; 338 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 339 clocks = <&k3_clks 167 0>; 340 clock-names = "gpio"; 341 status = "disabled"; 342 }; 343 344 wkup_gpio1: gpio@42100000 { 345 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 346 reg = <0x00 0x42100000 0x00 0x100>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-parent = <&wkup_gpio_intr>; 350 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 ti,ngpio = <89>; 354 ti,davinci-gpio-unbanked = <0>; 355 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 168 0>; 357 clock-names = "gpio"; 358 status = "disabled"; 359 }; 360 361 wkup_i2c0: i2c@42120000 { 362 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 363 reg = <0x00 0x42120000 0x00 0x100>; 364 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clocks = <&k3_clks 279 2>; 368 clock-names = "fck"; 369 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 370 status = "disabled"; 371 }; 372 373 mcu_i2c0: i2c@40b00000 { 374 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 375 reg = <0x00 0x40b00000 0x00 0x100>; 376 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&k3_clks 277 2>; 380 clock-names = "fck"; 381 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 382 status = "disabled"; 383 }; 384 385 mcu_i2c1: i2c@40b10000 { 386 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 387 reg = <0x00 0x40b10000 0x00 0x100>; 388 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&k3_clks 278 2>; 392 clock-names = "fck"; 393 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 394 status = "disabled"; 395 }; 396 397 mcu_mcan0: can@40528000 { 398 compatible = "bosch,m_can"; 399 reg = <0x00 0x40528000 0x00 0x200>, 400 <0x00 0x40500000 0x00 0x8000>; 401 reg-names = "m_can", "message_ram"; 402 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; 404 clock-names = "hclk", "cclk"; 405 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "int0", "int1"; 408 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 409 status = "disabled"; 410 }; 411 412 mcu_mcan1: can@40568000 { 413 compatible = "bosch,m_can"; 414 reg = <0x00 0x40568000 0x00 0x200>, 415 <0x00 0x40540000 0x00 0x8000>; 416 reg-names = "m_can", "message_ram"; 417 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; 419 clock-names = "hclk", "cclk"; 420 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "int0", "int1"; 423 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 424 status = "disabled"; 425 }; 426 427 mcu_spi0: spi@40300000 { 428 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 429 reg = <0x00 0x040300000 0x00 0x400>; 430 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 384 0>; 435 status = "disabled"; 436 }; 437 438 mcu_spi1: spi@40310000 { 439 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 440 reg = <0x00 0x040310000 0x00 0x400>; 441 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 385 0>; 446 status = "disabled"; 447 }; 448 449 mcu_spi2: spi@40320000 { 450 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 451 reg = <0x00 0x040320000 0x00 0x400>; 452 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 386 0>; 457 status = "disabled"; 458 }; 459 460 mcu_navss: bus@28380000 { 461 compatible = "simple-bus"; 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 465 ti,sci-dev-id = <323>; 466 dma-coherent; 467 dma-ranges; 468 469 mcu_ringacc: ringacc@2b800000 { 470 bootph-all; 471 compatible = "ti,am654-navss-ringacc"; 472 reg = <0x00 0x2b800000 0x00 0x400000>, 473 <0x00 0x2b000000 0x00 0x400000>, 474 <0x00 0x28590000 0x00 0x100>, 475 <0x00 0x2a500000 0x00 0x40000>, 476 <0x00 0x28440000 0x00 0x40000>; 477 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 478 ti,num-rings = <286>; 479 ti,sci-rm-range-gp-rings = <0x1>; 480 ti,sci = <&sms>; 481 ti,sci-dev-id = <328>; 482 msi-parent = <&main_udmass_inta>; 483 }; 484 485 mcu_udmap: dma-controller@285c0000 { 486 bootph-all; 487 compatible = "ti,j721e-navss-mcu-udmap"; 488 reg = <0x00 0x285c0000 0x00 0x100>, 489 <0x00 0x2a800000 0x00 0x40000>, 490 <0x00 0x2aa00000 0x00 0x40000>, 491 <0x00 0x284a0000 0x00 0x4000>, 492 <0x00 0x284c0000 0x00 0x4000>, 493 <0x00 0x28400000 0x00 0x2000>; 494 reg-names = "gcfg", "rchanrt", "tchanrt", 495 "tchan", "rchan", "rflow"; 496 msi-parent = <&main_udmass_inta>; 497 #dma-cells = <1>; 498 499 ti,sci = <&sms>; 500 ti,sci-dev-id = <329>; 501 ti,ringacc = <&mcu_ringacc>; 502 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 503 <0x0f>; /* TX_HCHAN */ 504 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 505 <0x0b>; /* RX_HCHAN */ 506 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 507 }; 508 }; 509 510 secure_proxy_mcu: mailbox@2a480000 { 511 compatible = "ti,am654-secure-proxy"; 512 #mbox-cells = <1>; 513 reg-names = "target_data", "rt", "scfg"; 514 reg = <0x00 0x2a480000 0x00 0x80000>, 515 <0x00 0x2a380000 0x00 0x80000>, 516 <0x00 0x2a400000 0x00 0x80000>; 517 bootph-pre-ram; 518 519 /* 520 * Marked Disabled: 521 * Node is incomplete as it is meant for bootloaders and 522 * firmware on non-MPU processors 523 */ 524 status = "disabled"; 525 }; 526 527 mcu_cpsw: ethernet@46000000 { 528 compatible = "ti,j721e-cpsw-nuss"; 529 #address-cells = <2>; 530 #size-cells = <2>; 531 reg = <0x00 0x46000000 0x00 0x200000>; 532 reg-names = "cpsw_nuss"; 533 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 534 dma-coherent; 535 clocks = <&k3_clks 63 0>; 536 clock-names = "fck"; 537 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 538 539 dmas = <&mcu_udmap 0xf000>, 540 <&mcu_udmap 0xf001>, 541 <&mcu_udmap 0xf002>, 542 <&mcu_udmap 0xf003>, 543 <&mcu_udmap 0xf004>, 544 <&mcu_udmap 0xf005>, 545 <&mcu_udmap 0xf006>, 546 <&mcu_udmap 0xf007>, 547 <&mcu_udmap 0x7000>; 548 dma-names = "tx0", "tx1", "tx2", "tx3", 549 "tx4", "tx5", "tx6", "tx7", 550 "rx"; 551 status = "disabled"; 552 553 ethernet-ports { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 557 mcu_cpsw_port1: port@1 { 558 reg = <1>; 559 ti,mac-only; 560 label = "port1"; 561 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 562 phys = <&phy_gmii_sel 1>; 563 }; 564 }; 565 566 davinci_mdio: mdio@f00 { 567 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 568 reg = <0x00 0xf00 0x00 0x100>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 clocks = <&k3_clks 63 0>; 572 clock-names = "fck"; 573 bus_freq = <1000000>; 574 }; 575 576 cpts@3d000 { 577 compatible = "ti,am65-cpts"; 578 reg = <0x00 0x3d000 0x00 0x400>; 579 clocks = <&k3_clks 63 3>; 580 clock-names = "cpts"; 581 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ 582 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ 583 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "cpts"; 585 ti,cpts-ext-ts-inputs = <4>; 586 ti,cpts-periodic-outputs = <2>; 587 }; 588 }; 589 590 mcu_r5fss0: r5fss@41000000 { 591 compatible = "ti,j721s2-r5fss"; 592 ti,cluster-mode = <1>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges = <0x41000000 0x00 0x41000000 0x20000>, 596 <0x41400000 0x00 0x41400000 0x20000>; 597 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 598 status = "disabled"; 599 600 mcu_r5fss0_core0: r5f@41000000 { 601 compatible = "ti,j721s2-r5f"; 602 reg = <0x41000000 0x00010000>, 603 <0x41010000 0x00010000>; 604 reg-names = "atcm", "btcm"; 605 ti,sci = <&sms>; 606 ti,sci-dev-id = <346>; 607 ti,sci-proc-ids = <0x01 0xff>; 608 resets = <&k3_reset 346 1>; 609 firmware-name = "j784s4-mcu-r5f0_0-fw"; 610 ti,atcm-enable = <1>; 611 ti,btcm-enable = <1>; 612 ti,loczrama = <1>; 613 status = "disabled"; 614 }; 615 616 mcu_r5fss0_core1: r5f@41400000 { 617 compatible = "ti,j721s2-r5f"; 618 reg = <0x41400000 0x00010000>, 619 <0x41410000 0x00010000>; 620 reg-names = "atcm", "btcm"; 621 ti,sci = <&sms>; 622 ti,sci-dev-id = <347>; 623 ti,sci-proc-ids = <0x02 0xff>; 624 resets = <&k3_reset 347 1>; 625 firmware-name = "j784s4-mcu-r5f0_1-fw"; 626 ti,atcm-enable = <1>; 627 ti,btcm-enable = <1>; 628 ti,loczrama = <1>; 629 status = "disabled"; 630 }; 631 }; 632 633 wkup_vtm0: temperature-sensor@42040000 { 634 compatible = "ti,j7200-vtm"; 635 reg = <0x00 0x42040000 0x00 0x350>, 636 <0x00 0x42050000 0x00 0x350>; 637 power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; 638 #thermal-sensor-cells = <1>; 639 bootph-pre-ram; 640 }; 641 642 tscadc0: tscadc@40200000 { 643 compatible = "ti,am3359-tscadc"; 644 reg = <0x00 0x40200000 0x00 0x1000>; 645 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 646 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 647 clocks = <&k3_clks 0 0>; 648 assigned-clocks = <&k3_clks 0 2>; 649 assigned-clock-rates = <60000000>; 650 clock-names = "fck"; 651 dmas = <&main_udmap 0x7400>, 652 <&main_udmap 0x7401>; 653 dma-names = "fifo0", "fifo1"; 654 status = "disabled"; 655 656 adc { 657 #io-channel-cells = <1>; 658 compatible = "ti,am3359-adc"; 659 }; 660 }; 661 662 tscadc1: tscadc@40210000 { 663 compatible = "ti,am3359-tscadc"; 664 reg = <0x00 0x40210000 0x00 0x1000>; 665 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 666 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 667 clocks = <&k3_clks 1 0>; 668 assigned-clocks = <&k3_clks 1 2>; 669 assigned-clock-rates = <60000000>; 670 clock-names = "fck"; 671 dmas = <&main_udmap 0x7402>, 672 <&main_udmap 0x7403>; 673 dma-names = "fifo0", "fifo1"; 674 status = "disabled"; 675 676 adc { 677 #io-channel-cells = <1>; 678 compatible = "ti,am3359-adc"; 679 }; 680 }; 681 682 fss: bus@47000000 { 683 compatible = "simple-bus"; 684 #address-cells = <2>; 685 #size-cells = <2>; 686 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00000100>, /* FSS Control */ 687 <0x00 0x47040000 0x00 0x47040000 0x00 0x00000100>, /* OSPI0 Control */ 688 <0x00 0x47050000 0x00 0x47050000 0x00 0x00000100>, /* OSPI1 Control */ 689 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */ 690 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */ 691 692 ospi0: spi@47040000 { 693 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 694 reg = <0x00 0x47040000 0x00 0x100>, 695 <0x05 0x00000000 0x01 0x00000000>; 696 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 697 cdns,fifo-depth = <256>; 698 cdns,fifo-width = <4>; 699 cdns,trigger-address = <0x0>; 700 clocks = <&k3_clks 161 7>; 701 assigned-clocks = <&k3_clks 161 7>; 702 assigned-clock-parents = <&k3_clks 161 9>; 703 assigned-clock-rates = <166666666>; 704 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 status = "disabled"; 708 }; 709 710 ospi1: spi@47050000 { 711 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 712 reg = <0x00 0x47050000 0x00 0x100>, 713 <0x07 0x00000000 0x01 0x00000000>; 714 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 715 cdns,fifo-depth = <256>; 716 cdns,fifo-width = <4>; 717 cdns,trigger-address = <0x0>; 718 clocks = <&k3_clks 162 7>; 719 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 }; 725 726 mcu_esm: esm@40800000 { 727 compatible = "ti,j721e-esm"; 728 reg = <0x00 0x40800000 0x00 0x1000>; 729 ti,esm-pins = <95>; 730 bootph-pre-ram; 731 }; 732 733 wkup_esm: esm@42080000 { 734 compatible = "ti,j721e-esm"; 735 reg = <0x00 0x42080000 0x00 0x1000>; 736 ti,esm-pins = <63>; 737 bootph-pre-ram; 738 }; 739 740 /* 741 * The 2 RTI instances are couple with MCU R5Fs so keeping them 742 * reserved as these will be used by their respective firmware 743 */ 744 mcu_watchdog0: watchdog@40600000 { 745 compatible = "ti,j7-rti-wdt"; 746 reg = <0x00 0x40600000 0x00 0x100>; 747 clocks = <&k3_clks 367 1>; 748 power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; 749 assigned-clocks = <&k3_clks 367 0>; 750 assigned-clock-parents = <&k3_clks 367 4>; 751 /* reserved for MCU_R5F0_0 */ 752 status = "reserved"; 753 }; 754 755 mcu_watchdog1: watchdog@40610000 { 756 compatible = "ti,j7-rti-wdt"; 757 reg = <0x00 0x40610000 0x00 0x100>; 758 clocks = <&k3_clks 368 1>; 759 power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; 760 assigned-clocks = <&k3_clks 368 0>; 761 assigned-clock-parents = <&k3_clks 368 4>; 762 /* reserved for MCU_R5F0_1 */ 763 status = "reserved"; 764 }; 765};
~/
Read-only file preview.