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k3-j784s4-j742s2-main-common.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 /* 25 * MSMC is configured by bootloaders and a runtime fixup is done in the 26 * DT for this node 27 */ 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x00 0x70000000 0x00 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x00 0x20000>; 37 }; 38 39 tifs-sram@1f0000 { 40 reg = <0x1f0000 0x10000>; 41 }; 42 43 l3cache-sram@200000 { 44 reg = <0x200000 0x200000>; 45 }; 46 }; 47 48 scm_conf: bus@100000 { 49 compatible = "simple-bus"; 50 reg = <0x00 0x00100000 0x00 0x1c000>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 ranges = <0x00 0x00 0x00100000 0x1c000>; 54 55 cpsw1_phy_gmii_sel: phy@4034 { 56 compatible = "ti,am654-phy-gmii-sel"; 57 reg = <0x4034 0x4>; 58 #phy-cells = <1>; 59 }; 60 61 cpsw0_phy_gmii_sel: phy@4044 { 62 compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; 63 reg = <0x4044 0x20>; 64 #phy-cells = <1>; 65 ti,qsgmii-main-ports = <7>, <7>; 66 }; 67 68 pcie0_ctrl: pcie0-ctrl@4070 { 69 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 70 reg = <0x4070 0x4>; 71 }; 72 73 pcie1_ctrl: pcie1-ctrl@4074 { 74 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 75 reg = <0x4074 0x4>; 76 }; 77 78 serdes_ln_ctrl: mux-controller@4080 { 79 compatible = "reg-mux"; 80 reg = <0x00004080 0x50>; 81 #mux-control-cells = <1>; 82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 83 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 85 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 87 <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ 88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 89 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 90 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 91 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 92 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 93 <J784S4_SERDES0_LANE3_USB>, 94 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 95 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 96 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 97 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 98 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 99 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 100 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 101 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 102 <J784S4_SERDES4_LANE0_EDP_LANE0>, 103 <J784S4_SERDES4_LANE1_EDP_LANE1>, 104 <J784S4_SERDES4_LANE2_EDP_LANE2>, 105 <J784S4_SERDES4_LANE3_EDP_LANE3>; 106 }; 107 108 usb_serdes_mux: mux-controller@4000 { 109 compatible = "reg-mux"; 110 reg = <0x4000 0x4>; 111 #mux-control-cells = <1>; 112 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ 113 }; 114 115 ehrpwm_tbclk: clock-controller@4140 { 116 compatible = "ti,am654-ehrpwm-tbclk"; 117 reg = <0x4140 0x18>; 118 #clock-cells = <1>; 119 }; 120 121 audio_refclk1: clock@82e4 { 122 compatible = "ti,am62-audio-refclk"; 123 reg = <0x82e4 0x4>; 124 clocks = <&k3_clks 157 34>; 125 assigned-clocks = <&k3_clks 157 34>; 126 assigned-clock-parents = <&k3_clks 157 63>; 127 #clock-cells = <0>; 128 }; 129 130 acspcie0_proxy_ctrl: clock-controller@1a090 { 131 compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; 132 reg = <0x1a090 0x4>; 133 }; 134 135 acspcie1_proxy_ctrl: clock-controller@1a094 { 136 compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; 137 reg = <0x1a094 0x4>; 138 }; 139 }; 140 141 main_ehrpwm0: pwm@3000000 { 142 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 143 reg = <0x00 0x3000000 0x00 0x100>; 144 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; 145 clock-names = "tbclk", "fck"; 146 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 147 #pwm-cells = <3>; 148 status = "disabled"; 149 }; 150 151 main_ehrpwm1: pwm@3010000 { 152 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 153 reg = <0x00 0x3010000 0x00 0x100>; 154 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; 155 clock-names = "tbclk", "fck"; 156 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 157 #pwm-cells = <3>; 158 status = "disabled"; 159 }; 160 161 main_ehrpwm2: pwm@3020000 { 162 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 163 reg = <0x00 0x3020000 0x00 0x100>; 164 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; 165 clock-names = "tbclk", "fck"; 166 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 167 #pwm-cells = <3>; 168 status = "disabled"; 169 }; 170 171 main_ehrpwm3: pwm@3030000 { 172 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 173 reg = <0x00 0x3030000 0x00 0x100>; 174 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; 175 clock-names = "tbclk", "fck"; 176 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 177 #pwm-cells = <3>; 178 status = "disabled"; 179 }; 180 181 main_ehrpwm4: pwm@3040000 { 182 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 183 reg = <0x00 0x3040000 0x00 0x100>; 184 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; 185 clock-names = "tbclk", "fck"; 186 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 187 #pwm-cells = <3>; 188 status = "disabled"; 189 }; 190 191 main_ehrpwm5: pwm@3050000 { 192 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 193 reg = <0x00 0x3050000 0x00 0x100>; 194 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; 195 clock-names = "tbclk", "fck"; 196 power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; 197 #pwm-cells = <3>; 198 status = "disabled"; 199 }; 200 201 gic500: interrupt-controller@1800000 { 202 compatible = "arm,gic-v3"; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges; 206 #interrupt-cells = <3>; 207 interrupt-controller; 208 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 209 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 210 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 211 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 212 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 213 214 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 216 217 gic_its: msi-controller@1820000 { 218 compatible = "arm,gic-v3-its"; 219 reg = <0x00 0x01820000 0x00 0x10000>; 220 socionext,synquacer-pre-its = <0x1000000 0x400000>; 221 msi-controller; 222 #msi-cells = <1>; 223 }; 224 }; 225 226 main_gpio_intr: interrupt-controller@a00000 { 227 compatible = "ti,sci-intr"; 228 reg = <0x00 0x00a00000 0x00 0x800>; 229 ti,intr-trigger-type = <1>; 230 interrupt-controller; 231 interrupt-parent = <&gic500>; 232 #interrupt-cells = <1>; 233 ti,sci = <&sms>; 234 ti,sci-dev-id = <10>; 235 ti,interrupt-ranges = <8 392 56>; 236 }; 237 238 main_pmx0: pinctrl@11c000 { 239 compatible = "ti,j7200-padconf", "pinctrl-single"; 240 /* Proxy 0 addressing */ 241 reg = <0x00 0x11c000 0x00 0x120>; 242 #pinctrl-cells = <1>; 243 pinctrl-single,register-width = <32>; 244 pinctrl-single,function-mask = <0xffffffff>; 245 }; 246 247 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 248 main_timerio_input: pinctrl@104200 { 249 compatible = "ti,j7200-padconf", "pinctrl-single"; 250 reg = <0x00 0x104200 0x00 0x50>; 251 #pinctrl-cells = <1>; 252 pinctrl-single,register-width = <32>; 253 pinctrl-single,function-mask = <0x00000007>; 254 }; 255 256 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 257 main_timerio_output: pinctrl@104280 { 258 compatible = "ti,j7200-padconf", "pinctrl-single"; 259 reg = <0x00 0x104280 0x00 0x20>; 260 #pinctrl-cells = <1>; 261 pinctrl-single,register-width = <32>; 262 pinctrl-single,function-mask = <0x0000001f>; 263 }; 264 265 main_crypto: crypto@4e00000 { 266 compatible = "ti,j721e-sa2ul"; 267 reg = <0x00 0x4e00000 0x00 0x1200>; 268 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 269 #address-cells = <2>; 270 #size-cells = <2>; 271 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 272 273 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 274 <&main_udmap 0x4a41>; 275 dma-names = "tx", "rx1", "rx2"; 276 277 rng: rng@4e10000 { 278 compatible = "inside-secure,safexcel-eip76"; 279 reg = <0x00 0x4e10000 0x00 0x7d>; 280 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 }; 283 284 main_timer0: timer@2400000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2400000 0x00 0x400>; 287 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 97 2>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 97 2>; 291 assigned-clock-parents = <&k3_clks 97 3>; 292 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 }; 295 296 main_timer1: timer@2410000 { 297 compatible = "ti,am654-timer"; 298 reg = <0x00 0x2410000 0x00 0x400>; 299 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&k3_clks 98 2>; 301 clock-names = "fck"; 302 assigned-clocks = <&k3_clks 98 2>; 303 assigned-clock-parents = <&k3_clks 98 3>; 304 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 305 ti,timer-pwm; 306 }; 307 308 main_timer2: timer@2420000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2420000 0x00 0x400>; 311 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 99 2>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 99 2>; 315 assigned-clock-parents = <&k3_clks 99 3>; 316 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer3: timer@2430000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2430000 0x00 0x400>; 323 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 100 2>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 100 2>; 327 assigned-clock-parents = <&k3_clks 100 3>; 328 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer4: timer@2440000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x2440000 0x00 0x400>; 335 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 101 2>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 101 2>; 339 assigned-clock-parents = <&k3_clks 101 3>; 340 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_timer5: timer@2450000 { 345 compatible = "ti,am654-timer"; 346 reg = <0x00 0x2450000 0x00 0x400>; 347 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&k3_clks 102 2>; 349 clock-names = "fck"; 350 assigned-clocks = <&k3_clks 102 2>; 351 assigned-clock-parents = <&k3_clks 102 3>; 352 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 353 ti,timer-pwm; 354 }; 355 356 main_timer6: timer@2460000 { 357 compatible = "ti,am654-timer"; 358 reg = <0x00 0x2460000 0x00 0x400>; 359 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&k3_clks 103 2>; 361 clock-names = "fck"; 362 assigned-clocks = <&k3_clks 103 2>; 363 assigned-clock-parents = <&k3_clks 103 3>; 364 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 365 ti,timer-pwm; 366 }; 367 368 main_timer7: timer@2470000 { 369 compatible = "ti,am654-timer"; 370 reg = <0x00 0x2470000 0x00 0x400>; 371 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&k3_clks 104 2>; 373 clock-names = "fck"; 374 assigned-clocks = <&k3_clks 104 2>; 375 assigned-clock-parents = <&k3_clks 104 3>; 376 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 377 ti,timer-pwm; 378 }; 379 380 main_timer8: timer@2480000 { 381 compatible = "ti,am654-timer"; 382 reg = <0x00 0x2480000 0x00 0x400>; 383 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&k3_clks 105 2>; 385 clock-names = "fck"; 386 assigned-clocks = <&k3_clks 105 2>; 387 assigned-clock-parents = <&k3_clks 105 3>; 388 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 389 ti,timer-pwm; 390 }; 391 392 main_timer9: timer@2490000 { 393 compatible = "ti,am654-timer"; 394 reg = <0x00 0x2490000 0x00 0x400>; 395 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&k3_clks 106 2>; 397 clock-names = "fck"; 398 assigned-clocks = <&k3_clks 106 2>; 399 assigned-clock-parents = <&k3_clks 106 3>; 400 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 401 ti,timer-pwm; 402 }; 403 404 main_timer10: timer@24a0000 { 405 compatible = "ti,am654-timer"; 406 reg = <0x00 0x24a0000 0x00 0x400>; 407 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&k3_clks 107 2>; 409 clock-names = "fck"; 410 assigned-clocks = <&k3_clks 107 2>; 411 assigned-clock-parents = <&k3_clks 107 3>; 412 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 413 ti,timer-pwm; 414 }; 415 416 main_timer11: timer@24b0000 { 417 compatible = "ti,am654-timer"; 418 reg = <0x00 0x24b0000 0x00 0x400>; 419 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&k3_clks 108 2>; 421 clock-names = "fck"; 422 assigned-clocks = <&k3_clks 108 2>; 423 assigned-clock-parents = <&k3_clks 108 3>; 424 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 425 ti,timer-pwm; 426 }; 427 428 main_timer12: timer@24c0000 { 429 compatible = "ti,am654-timer"; 430 reg = <0x00 0x24c0000 0x00 0x400>; 431 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&k3_clks 109 2>; 433 clock-names = "fck"; 434 assigned-clocks = <&k3_clks 109 2>; 435 assigned-clock-parents = <&k3_clks 109 3>; 436 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 437 ti,timer-pwm; 438 }; 439 440 main_timer13: timer@24d0000 { 441 compatible = "ti,am654-timer"; 442 reg = <0x00 0x24d0000 0x00 0x400>; 443 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&k3_clks 110 2>; 445 clock-names = "fck"; 446 assigned-clocks = <&k3_clks 110 2>; 447 assigned-clock-parents = <&k3_clks 110 3>; 448 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 449 ti,timer-pwm; 450 }; 451 452 main_timer14: timer@24e0000 { 453 compatible = "ti,am654-timer"; 454 reg = <0x00 0x24e0000 0x00 0x400>; 455 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&k3_clks 111 2>; 457 clock-names = "fck"; 458 assigned-clocks = <&k3_clks 111 2>; 459 assigned-clock-parents = <&k3_clks 111 3>; 460 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 461 ti,timer-pwm; 462 }; 463 464 main_timer15: timer@24f0000 { 465 compatible = "ti,am654-timer"; 466 reg = <0x00 0x24f0000 0x00 0x400>; 467 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&k3_clks 112 2>; 469 clock-names = "fck"; 470 assigned-clocks = <&k3_clks 112 2>; 471 assigned-clock-parents = <&k3_clks 112 3>; 472 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 473 ti,timer-pwm; 474 }; 475 476 main_timer16: timer@2500000 { 477 compatible = "ti,am654-timer"; 478 reg = <0x00 0x2500000 0x00 0x400>; 479 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&k3_clks 113 2>; 481 clock-names = "fck"; 482 assigned-clocks = <&k3_clks 113 2>; 483 assigned-clock-parents = <&k3_clks 113 3>; 484 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 485 ti,timer-pwm; 486 }; 487 488 main_timer17: timer@2510000 { 489 compatible = "ti,am654-timer"; 490 reg = <0x00 0x2510000 0x00 0x400>; 491 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&k3_clks 114 2>; 493 clock-names = "fck"; 494 assigned-clocks = <&k3_clks 114 2>; 495 assigned-clock-parents = <&k3_clks 114 3>; 496 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 497 ti,timer-pwm; 498 }; 499 500 main_timer18: timer@2520000 { 501 compatible = "ti,am654-timer"; 502 reg = <0x00 0x2520000 0x00 0x400>; 503 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&k3_clks 115 2>; 505 clock-names = "fck"; 506 assigned-clocks = <&k3_clks 115 2>; 507 assigned-clock-parents = <&k3_clks 115 3>; 508 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 509 ti,timer-pwm; 510 }; 511 512 main_timer19: timer@2530000 { 513 compatible = "ti,am654-timer"; 514 reg = <0x00 0x2530000 0x00 0x400>; 515 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&k3_clks 116 2>; 517 clock-names = "fck"; 518 assigned-clocks = <&k3_clks 116 2>; 519 assigned-clock-parents = <&k3_clks 116 3>; 520 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 521 ti,timer-pwm; 522 }; 523 524 main_uart0: serial@2800000 { 525 compatible = "ti,j721e-uart", "ti,am654-uart"; 526 reg = <0x00 0x02800000 0x00 0x200>; 527 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&k3_clks 146 0>; 529 clock-names = "fclk"; 530 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 531 status = "disabled"; 532 }; 533 534 main_uart1: serial@2810000 { 535 compatible = "ti,j721e-uart", "ti,am654-uart"; 536 reg = <0x00 0x02810000 0x00 0x200>; 537 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&k3_clks 388 0>; 539 clock-names = "fclk"; 540 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 541 status = "disabled"; 542 }; 543 544 main_uart2: serial@2820000 { 545 compatible = "ti,j721e-uart", "ti,am654-uart"; 546 reg = <0x00 0x02820000 0x00 0x200>; 547 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&k3_clks 389 0>; 549 clock-names = "fclk"; 550 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 551 status = "disabled"; 552 }; 553 554 main_uart3: serial@2830000 { 555 compatible = "ti,j721e-uart", "ti,am654-uart"; 556 reg = <0x00 0x02830000 0x00 0x200>; 557 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&k3_clks 390 0>; 559 clock-names = "fclk"; 560 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 561 status = "disabled"; 562 }; 563 564 main_uart4: serial@2840000 { 565 compatible = "ti,j721e-uart", "ti,am654-uart"; 566 reg = <0x00 0x02840000 0x00 0x200>; 567 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&k3_clks 391 0>; 569 clock-names = "fclk"; 570 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 571 status = "disabled"; 572 }; 573 574 main_uart5: serial@2850000 { 575 compatible = "ti,j721e-uart", "ti,am654-uart"; 576 reg = <0x00 0x02850000 0x00 0x200>; 577 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&k3_clks 392 0>; 579 clock-names = "fclk"; 580 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 581 status = "disabled"; 582 }; 583 584 main_uart6: serial@2860000 { 585 compatible = "ti,j721e-uart", "ti,am654-uart"; 586 reg = <0x00 0x02860000 0x00 0x200>; 587 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&k3_clks 393 0>; 589 clock-names = "fclk"; 590 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 591 status = "disabled"; 592 }; 593 594 main_uart7: serial@2870000 { 595 compatible = "ti,j721e-uart", "ti,am654-uart"; 596 reg = <0x00 0x02870000 0x00 0x200>; 597 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&k3_clks 394 0>; 599 clock-names = "fclk"; 600 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 601 status = "disabled"; 602 }; 603 604 main_uart8: serial@2880000 { 605 compatible = "ti,j721e-uart", "ti,am654-uart"; 606 reg = <0x00 0x02880000 0x00 0x200>; 607 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&k3_clks 395 0>; 609 clock-names = "fclk"; 610 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 611 status = "disabled"; 612 }; 613 614 main_uart9: serial@2890000 { 615 compatible = "ti,j721e-uart", "ti,am654-uart"; 616 reg = <0x00 0x02890000 0x00 0x200>; 617 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&k3_clks 396 0>; 619 clock-names = "fclk"; 620 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 621 status = "disabled"; 622 }; 623 624 main_gpio0: gpio@600000 { 625 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 626 reg = <0x00 0x00600000 0x00 0x100>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 interrupt-parent = <&main_gpio_intr>; 630 interrupts = <145>, <146>, <147>, <148>, <149>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 ti,ngpio = <66>; 634 ti,davinci-gpio-unbanked = <0>; 635 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 636 clocks = <&k3_clks 163 0>; 637 clock-names = "gpio"; 638 status = "disabled"; 639 }; 640 641 main_gpio2: gpio@610000 { 642 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 643 reg = <0x00 0x00610000 0x00 0x100>; 644 gpio-controller; 645 #gpio-cells = <2>; 646 interrupt-parent = <&main_gpio_intr>; 647 interrupts = <154>, <155>, <156>, <157>, <158>; 648 interrupt-controller; 649 #interrupt-cells = <2>; 650 ti,ngpio = <66>; 651 ti,davinci-gpio-unbanked = <0>; 652 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 653 clocks = <&k3_clks 164 0>; 654 clock-names = "gpio"; 655 status = "disabled"; 656 }; 657 658 main_gpio4: gpio@620000 { 659 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 660 reg = <0x00 0x00620000 0x00 0x100>; 661 gpio-controller; 662 #gpio-cells = <2>; 663 interrupt-parent = <&main_gpio_intr>; 664 interrupts = <163>, <164>, <165>, <166>, <167>; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 ti,ngpio = <66>; 668 ti,davinci-gpio-unbanked = <0>; 669 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 670 clocks = <&k3_clks 165 0>; 671 clock-names = "gpio"; 672 status = "disabled"; 673 }; 674 675 main_gpio6: gpio@630000 { 676 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 677 reg = <0x00 0x00630000 0x00 0x100>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 interrupt-parent = <&main_gpio_intr>; 681 interrupts = <172>, <173>, <174>, <175>, <176>; 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 ti,ngpio = <66>; 685 ti,davinci-gpio-unbanked = <0>; 686 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 687 clocks = <&k3_clks 166 0>; 688 clock-names = "gpio"; 689 status = "disabled"; 690 }; 691 692 usbss0: usb@4104000 { 693 bootph-all; 694 compatible = "ti,j721e-usb"; 695 reg = <0x00 0x4104000 0x00 0x100>; 696 dma-coherent; 697 power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; 698 clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; 699 clock-names = "ref", "lpm"; 700 assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ 701 assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ 702 #address-cells = <2>; 703 #size-cells = <2>; 704 ranges; 705 706 status = "disabled"; /* Needs lane config */ 707 708 usb0: usb@6000000 { 709 bootph-all; 710 compatible = "cdns,usb3"; 711 reg = <0x00 0x6000000 0x00 0x10000>, 712 <0x00 0x6010000 0x00 0x10000>, 713 <0x00 0x6020000 0x00 0x10000>; 714 reg-names = "otg", "xhci", "dev"; 715 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 716 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 717 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 718 interrupt-names = "host", 719 "peripheral", 720 "otg"; 721 }; 722 }; 723 724 main_i2c0: i2c@2000000 { 725 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 726 reg = <0x00 0x02000000 0x00 0x100>; 727 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 clocks = <&k3_clks 270 2>; 731 clock-names = "fck"; 732 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 733 status = "disabled"; 734 }; 735 736 main_i2c1: i2c@2010000 { 737 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 738 reg = <0x00 0x02010000 0x00 0x100>; 739 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&k3_clks 271 2>; 743 clock-names = "fck"; 744 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 745 status = "disabled"; 746 }; 747 748 main_i2c2: i2c@2020000 { 749 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 750 reg = <0x00 0x02020000 0x00 0x100>; 751 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 clocks = <&k3_clks 272 2>; 755 clock-names = "fck"; 756 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 757 status = "disabled"; 758 }; 759 760 main_i2c3: i2c@2030000 { 761 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 762 reg = <0x00 0x02030000 0x00 0x100>; 763 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 clocks = <&k3_clks 273 2>; 767 clock-names = "fck"; 768 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 769 status = "disabled"; 770 }; 771 772 main_i2c4: i2c@2040000 { 773 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 774 reg = <0x00 0x02040000 0x00 0x100>; 775 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&k3_clks 274 2>; 779 clock-names = "fck"; 780 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 781 status = "disabled"; 782 }; 783 784 main_i2c5: i2c@2050000 { 785 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 786 reg = <0x00 0x02050000 0x00 0x100>; 787 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clocks = <&k3_clks 275 2>; 791 clock-names = "fck"; 792 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 793 status = "disabled"; 794 }; 795 796 main_i2c6: i2c@2060000 { 797 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 798 reg = <0x00 0x02060000 0x00 0x100>; 799 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 clocks = <&k3_clks 276 2>; 803 clock-names = "fck"; 804 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 805 status = "disabled"; 806 }; 807 808 ti_csi2rx0: ticsi2rx@4500000 { 809 compatible = "ti,j721e-csi2rx-shim"; 810 reg = <0x00 0x04500000 0x00 0x00001000>; 811 ranges; 812 #address-cells = <2>; 813 #size-cells = <2>; 814 dmas = <&main_bcdma_csi 0 0x4940 0>; 815 dma-names = "rx0"; 816 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 817 status = "disabled"; 818 819 cdns_csi2rx0: csi-bridge@4504000 { 820 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 821 reg = <0x00 0x04504000 0x00 0x00001000>; 822 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 824 interrupt-names = "error_irq", "irq"; 825 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 826 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 827 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 828 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 829 phys = <&dphy0>; 830 phy-names = "dphy"; 831 832 ports { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 csi0_port0: port@0 { 837 reg = <0>; 838 status = "disabled"; 839 }; 840 841 csi0_port1: port@1 { 842 reg = <1>; 843 status = "disabled"; 844 }; 845 846 csi0_port2: port@2 { 847 reg = <2>; 848 status = "disabled"; 849 }; 850 851 csi0_port3: port@3 { 852 reg = <3>; 853 status = "disabled"; 854 }; 855 856 csi0_port4: port@4 { 857 reg = <4>; 858 status = "disabled"; 859 }; 860 }; 861 }; 862 }; 863 864 ti_csi2rx1: ticsi2rx@4510000 { 865 compatible = "ti,j721e-csi2rx-shim"; 866 reg = <0x00 0x04510000 0x00 0x1000>; 867 ranges; 868 #address-cells = <2>; 869 #size-cells = <2>; 870 dmas = <&main_bcdma_csi 0 0x4960 0>; 871 dma-names = "rx0"; 872 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 873 status = "disabled"; 874 875 cdns_csi2rx1: csi-bridge@4514000 { 876 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 877 reg = <0x00 0x04514000 0x00 0x00001000>; 878 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "error_irq", "irq"; 881 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 882 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 883 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 884 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 885 phys = <&dphy1>; 886 phy-names = "dphy"; 887 ports { 888 #address-cells = <1>; 889 #size-cells = <0>; 890 891 csi1_port0: port@0 { 892 reg = <0>; 893 status = "disabled"; 894 }; 895 896 csi1_port1: port@1 { 897 reg = <1>; 898 status = "disabled"; 899 }; 900 901 csi1_port2: port@2 { 902 reg = <2>; 903 status = "disabled"; 904 }; 905 906 csi1_port3: port@3 { 907 reg = <3>; 908 status = "disabled"; 909 }; 910 911 csi1_port4: port@4 { 912 reg = <4>; 913 status = "disabled"; 914 }; 915 }; 916 }; 917 }; 918 919 ti_csi2rx2: ticsi2rx@4520000 { 920 compatible = "ti,j721e-csi2rx-shim"; 921 reg = <0x00 0x04520000 0x00 0x00001000>; 922 ranges; 923 #address-cells = <2>; 924 #size-cells = <2>; 925 dmas = <&main_bcdma_csi 0 0x4980 0>; 926 dma-names = "rx0"; 927 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 928 status = "disabled"; 929 930 cdns_csi2rx2: csi-bridge@4524000 { 931 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 932 reg = <0x00 0x04524000 0x00 0x00001000>; 933 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "error_irq", "irq"; 936 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 937 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 938 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 939 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 940 phys = <&dphy2>; 941 phy-names = "dphy"; 942 943 ports { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 csi2_port0: port@0 { 948 reg = <0>; 949 status = "disabled"; 950 }; 951 952 csi2_port1: port@1 { 953 reg = <1>; 954 status = "disabled"; 955 }; 956 957 csi2_port2: port@2 { 958 reg = <2>; 959 status = "disabled"; 960 }; 961 962 csi2_port3: port@3 { 963 reg = <3>; 964 status = "disabled"; 965 }; 966 967 csi2_port4: port@4 { 968 reg = <4>; 969 status = "disabled"; 970 }; 971 }; 972 }; 973 }; 974 975 dphy0: phy@4580000 { 976 compatible = "cdns,dphy-rx"; 977 reg = <0x00 0x04580000 0x00 0x00001100>; 978 #phy-cells = <0>; 979 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 980 status = "disabled"; 981 }; 982 983 dphy1: phy@4590000 { 984 compatible = "cdns,dphy-rx"; 985 reg = <0x00 0x04590000 0x00 0x00001100>; 986 #phy-cells = <0>; 987 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 988 status = "disabled"; 989 }; 990 991 dphy2: phy@45a0000 { 992 compatible = "cdns,dphy-rx"; 993 reg = <0x00 0x045a0000 0x00 0x00001100>; 994 #phy-cells = <0>; 995 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 996 status = "disabled"; 997 }; 998 999 vpu0: video-codec@4210000 { 1000 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1001 reg = <0x00 0x4210000 0x00 0x10000>; 1002 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&k3_clks 241 2>; 1004 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 1005 }; 1006 1007 vpu1: video-codec@4220000 { 1008 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1009 reg = <0x00 0x4220000 0x00 0x10000>; 1010 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&k3_clks 242 2>; 1012 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 1013 }; 1014 1015 main_sdhci0: mmc@4f80000 { 1016 compatible = "ti,j721e-sdhci-8bit"; 1017 reg = <0x00 0x04f80000 0x00 0x1000>, 1018 <0x00 0x04f88000 0x00 0x400>; 1019 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1020 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 1021 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 1022 clock-names = "clk_ahb", "clk_xin"; 1023 assigned-clocks = <&k3_clks 140 2>; 1024 assigned-clock-parents = <&k3_clks 140 3>; 1025 bus-width = <8>; 1026 ti,otap-del-sel-legacy = <0x0>; 1027 ti,otap-del-sel-mmc-hs = <0x0>; 1028 ti,otap-del-sel-ddr52 = <0x6>; 1029 ti,otap-del-sel-hs200 = <0x8>; 1030 ti,otap-del-sel-hs400 = <0x5>; 1031 ti,itap-del-sel-legacy = <0x10>; 1032 ti,itap-del-sel-mmc-hs = <0xa>; 1033 ti,strobe-sel = <0x77>; 1034 ti,clkbuf-sel = <0x7>; 1035 ti,trm-icp = <0x8>; 1036 mmc-ddr-1_8v; 1037 mmc-hs200-1_8v; 1038 mmc-hs400-1_8v; 1039 dma-coherent; 1040 status = "disabled"; 1041 }; 1042 1043 main_sdhci1: mmc@4fb0000 { 1044 compatible = "ti,j721e-sdhci-4bit"; 1045 reg = <0x00 0x04fb0000 0x00 0x1000>, 1046 <0x00 0x04fb8000 0x00 0x400>; 1047 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1048 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 1049 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 1050 clock-names = "clk_ahb", "clk_xin"; 1051 assigned-clocks = <&k3_clks 141 4>; 1052 assigned-clock-parents = <&k3_clks 141 5>; 1053 bus-width = <4>; 1054 ti,otap-del-sel-legacy = <0x0>; 1055 ti,otap-del-sel-sd-hs = <0x0>; 1056 ti,otap-del-sel-sdr12 = <0xf>; 1057 ti,otap-del-sel-sdr25 = <0xf>; 1058 ti,otap-del-sel-sdr50 = <0xc>; 1059 ti,otap-del-sel-sdr104 = <0x5>; 1060 ti,otap-del-sel-ddr50 = <0xc>; 1061 ti,itap-del-sel-legacy = <0x0>; 1062 ti,itap-del-sel-sd-hs = <0x0>; 1063 ti,itap-del-sel-sdr12 = <0x0>; 1064 ti,itap-del-sel-sdr25 = <0x0>; 1065 ti,itap-del-sel-ddr50 = <0x2>; 1066 ti,clkbuf-sel = <0x7>; 1067 ti,trm-icp = <0x8>; 1068 dma-coherent; 1069 status = "disabled"; 1070 }; 1071 1072 pcie0_rc: pcie@2900000 { 1073 compatible = "ti,j784s4-pcie-host"; 1074 reg = <0x00 0x02900000 0x00 0x1000>, 1075 <0x00 0x02907000 0x00 0x400>, 1076 <0x00 0x0d000000 0x00 0x00800000>, 1077 <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1078 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1079 interrupt-names = "link_state"; 1080 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 1081 device_type = "pci"; 1082 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1083 max-link-speed = <3>; 1084 num-lanes = <4>; 1085 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 1086 clocks = <&k3_clks 332 0>; 1087 clock-names = "fck"; 1088 #address-cells = <3>; 1089 #size-cells = <2>; 1090 bus-range = <0x0 0xff>; 1091 vendor-id = <0x104c>; 1092 device-id = <0xb012>; 1093 msi-map = <0x0 &gic_its 0x0 0x10000>; 1094 dma-coherent; 1095 ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1096 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1097 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1098 status = "disabled"; 1099 }; 1100 1101 pcie1_rc: pcie@2910000 { 1102 compatible = "ti,j784s4-pcie-host"; 1103 reg = <0x00 0x02910000 0x00 0x1000>, 1104 <0x00 0x02917000 0x00 0x400>, 1105 <0x00 0x0d800000 0x00 0x00800000>, 1106 <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 1107 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1108 interrupt-names = "link_state"; 1109 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1110 device_type = "pci"; 1111 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1112 max-link-speed = <3>; 1113 num-lanes = <4>; 1114 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 1115 clocks = <&k3_clks 333 0>; 1116 clock-names = "fck"; 1117 #address-cells = <3>; 1118 #size-cells = <2>; 1119 bus-range = <0x0 0xff>; 1120 vendor-id = <0x104c>; 1121 device-id = <0xb012>; 1122 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1123 dma-coherent; 1124 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1125 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1126 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1127 status = "disabled"; 1128 }; 1129 1130 serdes_wiz0: wiz@5060000 { 1131 compatible = "ti,j784s4-wiz-10g"; 1132 #address-cells = <1>; 1133 #size-cells = <1>; 1134 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 1135 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 1136 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1137 assigned-clocks = <&k3_clks 404 6>; 1138 assigned-clock-parents = <&k3_clks 404 10>; 1139 num-lanes = <4>; 1140 #reset-cells = <1>; 1141 #clock-cells = <1>; 1142 ranges = <0x5060000 0x00 0x5060000 0x10000>; 1143 status = "disabled"; 1144 1145 serdes0: serdes@5060000 { 1146 compatible = "ti,j721e-serdes-10g"; 1147 reg = <0x05060000 0x010000>; 1148 reg-names = "torrent_phy"; 1149 resets = <&serdes_wiz0 0>; 1150 reset-names = "torrent_reset"; 1151 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1152 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1153 clock-names = "refclk", "phy_en_refclk"; 1154 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1155 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1156 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1157 assigned-clock-parents = <&k3_clks 404 6>, 1158 <&k3_clks 404 6>, 1159 <&k3_clks 404 6>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 #clock-cells = <1>; 1163 status = "disabled"; 1164 }; 1165 }; 1166 1167 serdes_wiz1: wiz@5070000 { 1168 compatible = "ti,j784s4-wiz-10g"; 1169 #address-cells = <1>; 1170 #size-cells = <1>; 1171 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 1172 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 1173 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1174 assigned-clocks = <&k3_clks 405 6>; 1175 assigned-clock-parents = <&k3_clks 405 10>; 1176 num-lanes = <4>; 1177 #reset-cells = <1>; 1178 #clock-cells = <1>; 1179 ranges = <0x05070000 0x00 0x05070000 0x10000>; 1180 status = "disabled"; 1181 1182 serdes1: serdes@5070000 { 1183 compatible = "ti,j721e-serdes-10g"; 1184 reg = <0x05070000 0x010000>; 1185 reg-names = "torrent_phy"; 1186 resets = <&serdes_wiz1 0>; 1187 reset-names = "torrent_reset"; 1188 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1189 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 1190 clock-names = "refclk", "phy_en_refclk"; 1191 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1192 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 1193 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 1194 assigned-clock-parents = <&k3_clks 405 6>, 1195 <&k3_clks 405 6>, 1196 <&k3_clks 405 6>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 #clock-cells = <1>; 1200 status = "disabled"; 1201 }; 1202 }; 1203 1204 serdes_wiz4: wiz@5050000 { 1205 compatible = "ti,j784s4-wiz-10g"; 1206 #address-cells = <1>; 1207 #size-cells = <1>; 1208 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1209 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1210 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1211 assigned-clocks = <&k3_clks 407 6>; 1212 assigned-clock-parents = <&k3_clks 407 10>; 1213 num-lanes = <4>; 1214 #reset-cells = <1>; 1215 #clock-cells = <1>; 1216 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1217 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1218 status = "disabled"; 1219 1220 serdes4: serdes@5050000 { 1221 /* 1222 * Note: we also map DPTX PHY registers as the Torrent 1223 * needs to manage those. 1224 */ 1225 compatible = "ti,j721e-serdes-10g"; 1226 reg = <0x05050000 0x010000>, 1227 <0x0a030a00 0x40>; /* DPTX PHY */ 1228 reg-names = "torrent_phy"; 1229 resets = <&serdes_wiz4 0>; 1230 reset-names = "torrent_reset"; 1231 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1232 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1233 clock-names = "refclk", "phy_en_refclk"; 1234 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1235 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1236 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1237 assigned-clock-parents = <&k3_clks 407 6>, 1238 <&k3_clks 407 6>, 1239 <&k3_clks 407 6>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 #clock-cells = <1>; 1243 status = "disabled"; 1244 }; 1245 }; 1246 1247 main_navss: bus@30000000 { 1248 bootph-all; 1249 compatible = "simple-bus"; 1250 #address-cells = <2>; 1251 #size-cells = <2>; 1252 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1253 ti,sci-dev-id = <280>; 1254 dma-coherent; 1255 dma-ranges; 1256 1257 main_navss_intr: interrupt-controller@310e0000 { 1258 compatible = "ti,sci-intr"; 1259 reg = <0x00 0x310e0000 0x00 0x4000>; 1260 ti,intr-trigger-type = <4>; 1261 interrupt-controller; 1262 interrupt-parent = <&gic500>; 1263 #interrupt-cells = <1>; 1264 ti,sci = <&sms>; 1265 ti,sci-dev-id = <283>; 1266 ti,interrupt-ranges = <0 64 64>, 1267 <64 448 64>, 1268 <128 672 64>; 1269 }; 1270 1271 main_udmass_inta: msi-controller@33d00000 { 1272 compatible = "ti,sci-inta"; 1273 reg = <0x00 0x33d00000 0x00 0x100000>; 1274 interrupt-controller; 1275 #interrupt-cells = <0>; 1276 interrupt-parent = <&main_navss_intr>; 1277 msi-controller; 1278 ti,sci = <&sms>; 1279 ti,sci-dev-id = <321>; 1280 ti,interrupt-ranges = <0 0 256>; 1281 ti,unmapped-event-sources = <&main_bcdma_csi>; 1282 }; 1283 1284 secure_proxy_main: mailbox@32c00000 { 1285 bootph-all; 1286 compatible = "ti,am654-secure-proxy"; 1287 #mbox-cells = <1>; 1288 reg-names = "target_data", "rt", "scfg"; 1289 reg = <0x00 0x32c00000 0x00 0x100000>, 1290 <0x00 0x32400000 0x00 0x100000>, 1291 <0x00 0x32800000 0x00 0x100000>; 1292 interrupt-names = "rx_011"; 1293 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1294 }; 1295 1296 hwspinlock: hwlock@30e00000 { 1297 compatible = "ti,am654-hwspinlock"; 1298 reg = <0x00 0x30e00000 0x00 0x1000>; 1299 #hwlock-cells = <1>; 1300 }; 1301 1302 mailbox0_cluster0: mailbox@31f80000 { 1303 compatible = "ti,am654-mailbox"; 1304 reg = <0x00 0x31f80000 0x00 0x200>; 1305 #mbox-cells = <1>; 1306 ti,mbox-num-users = <4>; 1307 ti,mbox-num-fifos = <16>; 1308 interrupt-parent = <&main_navss_intr>; 1309 status = "disabled"; 1310 }; 1311 1312 mailbox0_cluster1: mailbox@31f81000 { 1313 compatible = "ti,am654-mailbox"; 1314 reg = <0x00 0x31f81000 0x00 0x200>; 1315 #mbox-cells = <1>; 1316 ti,mbox-num-users = <4>; 1317 ti,mbox-num-fifos = <16>; 1318 interrupt-parent = <&main_navss_intr>; 1319 status = "disabled"; 1320 }; 1321 1322 mailbox0_cluster2: mailbox@31f82000 { 1323 compatible = "ti,am654-mailbox"; 1324 reg = <0x00 0x31f82000 0x00 0x200>; 1325 #mbox-cells = <1>; 1326 ti,mbox-num-users = <4>; 1327 ti,mbox-num-fifos = <16>; 1328 interrupt-parent = <&main_navss_intr>; 1329 status = "disabled"; 1330 }; 1331 1332 mailbox0_cluster3: mailbox@31f83000 { 1333 compatible = "ti,am654-mailbox"; 1334 reg = <0x00 0x31f83000 0x00 0x200>; 1335 #mbox-cells = <1>; 1336 ti,mbox-num-users = <4>; 1337 ti,mbox-num-fifos = <16>; 1338 interrupt-parent = <&main_navss_intr>; 1339 status = "disabled"; 1340 }; 1341 1342 mailbox0_cluster4: mailbox@31f84000 { 1343 compatible = "ti,am654-mailbox"; 1344 reg = <0x00 0x31f84000 0x00 0x200>; 1345 #mbox-cells = <1>; 1346 ti,mbox-num-users = <4>; 1347 ti,mbox-num-fifos = <16>; 1348 interrupt-parent = <&main_navss_intr>; 1349 status = "disabled"; 1350 }; 1351 1352 mailbox0_cluster5: mailbox@31f85000 { 1353 compatible = "ti,am654-mailbox"; 1354 reg = <0x00 0x31f85000 0x00 0x200>; 1355 #mbox-cells = <1>; 1356 ti,mbox-num-users = <4>; 1357 ti,mbox-num-fifos = <16>; 1358 interrupt-parent = <&main_navss_intr>; 1359 status = "disabled"; 1360 }; 1361 1362 mailbox0_cluster6: mailbox@31f86000 { 1363 compatible = "ti,am654-mailbox"; 1364 reg = <0x00 0x31f86000 0x00 0x200>; 1365 #mbox-cells = <1>; 1366 ti,mbox-num-users = <4>; 1367 ti,mbox-num-fifos = <16>; 1368 interrupt-parent = <&main_navss_intr>; 1369 status = "disabled"; 1370 }; 1371 1372 mailbox0_cluster7: mailbox@31f87000 { 1373 compatible = "ti,am654-mailbox"; 1374 reg = <0x00 0x31f87000 0x00 0x200>; 1375 #mbox-cells = <1>; 1376 ti,mbox-num-users = <4>; 1377 ti,mbox-num-fifos = <16>; 1378 interrupt-parent = <&main_navss_intr>; 1379 status = "disabled"; 1380 }; 1381 1382 mailbox0_cluster8: mailbox@31f88000 { 1383 compatible = "ti,am654-mailbox"; 1384 reg = <0x00 0x31f88000 0x00 0x200>; 1385 #mbox-cells = <1>; 1386 ti,mbox-num-users = <4>; 1387 ti,mbox-num-fifos = <16>; 1388 interrupt-parent = <&main_navss_intr>; 1389 status = "disabled"; 1390 }; 1391 1392 mailbox0_cluster9: mailbox@31f89000 { 1393 compatible = "ti,am654-mailbox"; 1394 reg = <0x00 0x31f89000 0x00 0x200>; 1395 #mbox-cells = <1>; 1396 ti,mbox-num-users = <4>; 1397 ti,mbox-num-fifos = <16>; 1398 interrupt-parent = <&main_navss_intr>; 1399 status = "disabled"; 1400 }; 1401 1402 mailbox0_cluster10: mailbox@31f8a000 { 1403 compatible = "ti,am654-mailbox"; 1404 reg = <0x00 0x31f8a000 0x00 0x200>; 1405 #mbox-cells = <1>; 1406 ti,mbox-num-users = <4>; 1407 ti,mbox-num-fifos = <16>; 1408 interrupt-parent = <&main_navss_intr>; 1409 status = "disabled"; 1410 }; 1411 1412 mailbox0_cluster11: mailbox@31f8b000 { 1413 compatible = "ti,am654-mailbox"; 1414 reg = <0x00 0x31f8b000 0x00 0x200>; 1415 #mbox-cells = <1>; 1416 ti,mbox-num-users = <4>; 1417 ti,mbox-num-fifos = <16>; 1418 interrupt-parent = <&main_navss_intr>; 1419 status = "disabled"; 1420 }; 1421 1422 mailbox1_cluster0: mailbox@31f90000 { 1423 compatible = "ti,am654-mailbox"; 1424 reg = <0x00 0x31f90000 0x00 0x200>; 1425 #mbox-cells = <1>; 1426 ti,mbox-num-users = <4>; 1427 ti,mbox-num-fifos = <16>; 1428 interrupt-parent = <&main_navss_intr>; 1429 status = "disabled"; 1430 }; 1431 1432 mailbox1_cluster1: mailbox@31f91000 { 1433 compatible = "ti,am654-mailbox"; 1434 reg = <0x00 0x31f91000 0x00 0x200>; 1435 #mbox-cells = <1>; 1436 ti,mbox-num-users = <4>; 1437 ti,mbox-num-fifos = <16>; 1438 interrupt-parent = <&main_navss_intr>; 1439 status = "disabled"; 1440 }; 1441 1442 mailbox1_cluster2: mailbox@31f92000 { 1443 compatible = "ti,am654-mailbox"; 1444 reg = <0x00 0x31f92000 0x00 0x200>; 1445 #mbox-cells = <1>; 1446 ti,mbox-num-users = <4>; 1447 ti,mbox-num-fifos = <16>; 1448 interrupt-parent = <&main_navss_intr>; 1449 status = "disabled"; 1450 }; 1451 1452 mailbox1_cluster3: mailbox@31f93000 { 1453 compatible = "ti,am654-mailbox"; 1454 reg = <0x00 0x31f93000 0x00 0x200>; 1455 #mbox-cells = <1>; 1456 ti,mbox-num-users = <4>; 1457 ti,mbox-num-fifos = <16>; 1458 interrupt-parent = <&main_navss_intr>; 1459 status = "disabled"; 1460 }; 1461 1462 mailbox1_cluster4: mailbox@31f94000 { 1463 compatible = "ti,am654-mailbox"; 1464 reg = <0x00 0x31f94000 0x00 0x200>; 1465 #mbox-cells = <1>; 1466 ti,mbox-num-users = <4>; 1467 ti,mbox-num-fifos = <16>; 1468 interrupt-parent = <&main_navss_intr>; 1469 status = "disabled"; 1470 }; 1471 1472 mailbox1_cluster5: mailbox@31f95000 { 1473 compatible = "ti,am654-mailbox"; 1474 reg = <0x00 0x31f95000 0x00 0x200>; 1475 #mbox-cells = <1>; 1476 ti,mbox-num-users = <4>; 1477 ti,mbox-num-fifos = <16>; 1478 interrupt-parent = <&main_navss_intr>; 1479 status = "disabled"; 1480 }; 1481 1482 mailbox1_cluster6: mailbox@31f96000 { 1483 compatible = "ti,am654-mailbox"; 1484 reg = <0x00 0x31f96000 0x00 0x200>; 1485 #mbox-cells = <1>; 1486 ti,mbox-num-users = <4>; 1487 ti,mbox-num-fifos = <16>; 1488 interrupt-parent = <&main_navss_intr>; 1489 status = "disabled"; 1490 }; 1491 1492 mailbox1_cluster7: mailbox@31f97000 { 1493 compatible = "ti,am654-mailbox"; 1494 reg = <0x00 0x31f97000 0x00 0x200>; 1495 #mbox-cells = <1>; 1496 ti,mbox-num-users = <4>; 1497 ti,mbox-num-fifos = <16>; 1498 interrupt-parent = <&main_navss_intr>; 1499 status = "disabled"; 1500 }; 1501 1502 mailbox1_cluster8: mailbox@31f98000 { 1503 compatible = "ti,am654-mailbox"; 1504 reg = <0x00 0x31f98000 0x00 0x200>; 1505 #mbox-cells = <1>; 1506 ti,mbox-num-users = <4>; 1507 ti,mbox-num-fifos = <16>; 1508 interrupt-parent = <&main_navss_intr>; 1509 status = "disabled"; 1510 }; 1511 1512 mailbox1_cluster9: mailbox@31f99000 { 1513 compatible = "ti,am654-mailbox"; 1514 reg = <0x00 0x31f99000 0x00 0x200>; 1515 #mbox-cells = <1>; 1516 ti,mbox-num-users = <4>; 1517 ti,mbox-num-fifos = <16>; 1518 interrupt-parent = <&main_navss_intr>; 1519 status = "disabled"; 1520 }; 1521 1522 mailbox1_cluster10: mailbox@31f9a000 { 1523 compatible = "ti,am654-mailbox"; 1524 reg = <0x00 0x31f9a000 0x00 0x200>; 1525 #mbox-cells = <1>; 1526 ti,mbox-num-users = <4>; 1527 ti,mbox-num-fifos = <16>; 1528 interrupt-parent = <&main_navss_intr>; 1529 status = "disabled"; 1530 }; 1531 1532 mailbox1_cluster11: mailbox@31f9b000 { 1533 compatible = "ti,am654-mailbox"; 1534 reg = <0x00 0x31f9b000 0x00 0x200>; 1535 #mbox-cells = <1>; 1536 ti,mbox-num-users = <4>; 1537 ti,mbox-num-fifos = <16>; 1538 interrupt-parent = <&main_navss_intr>; 1539 status = "disabled"; 1540 }; 1541 1542 main_ringacc: ringacc@3c000000 { 1543 compatible = "ti,am654-navss-ringacc"; 1544 reg = <0x00 0x3c000000 0x00 0x400000>, 1545 <0x00 0x38000000 0x00 0x400000>, 1546 <0x00 0x31120000 0x00 0x100>, 1547 <0x00 0x33000000 0x00 0x40000>, 1548 <0x00 0x31080000 0x00 0x40000>; 1549 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1550 ti,num-rings = <1024>; 1551 ti,sci-rm-range-gp-rings = <0x1>; 1552 ti,sci = <&sms>; 1553 ti,sci-dev-id = <315>; 1554 msi-parent = <&main_udmass_inta>; 1555 }; 1556 1557 main_udmap: dma-controller@31150000 { 1558 compatible = "ti,j721e-navss-main-udmap"; 1559 reg = <0x00 0x31150000 0x00 0x100>, 1560 <0x00 0x34000000 0x00 0x80000>, 1561 <0x00 0x35000000 0x00 0x200000>, 1562 <0x00 0x30b00000 0x00 0x20000>, 1563 <0x00 0x30c00000 0x00 0x8000>, 1564 <0x00 0x30d00000 0x00 0x4000>; 1565 reg-names = "gcfg", "rchanrt", "tchanrt", 1566 "tchan", "rchan", "rflow"; 1567 msi-parent = <&main_udmass_inta>; 1568 #dma-cells = <1>; 1569 1570 ti,sci = <&sms>; 1571 ti,sci-dev-id = <319>; 1572 ti,ringacc = <&main_ringacc>; 1573 1574 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1575 <0x0f>, /* TX_HCHAN */ 1576 <0x10>; /* TX_UHCHAN */ 1577 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1578 <0x0b>, /* RX_HCHAN */ 1579 <0x0c>; /* RX_UHCHAN */ 1580 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1581 }; 1582 1583 main_bcdma_csi: dma-controller@311a0000 { 1584 compatible = "ti,j721s2-dmss-bcdma-csi"; 1585 reg = <0x00 0x311a0000 0x00 0x100>, 1586 <0x00 0x35d00000 0x00 0x20000>, 1587 <0x00 0x35c00000 0x00 0x10000>, 1588 <0x00 0x35e00000 0x00 0x80000>; 1589 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1590 msi-parent = <&main_udmass_inta>; 1591 #dma-cells = <3>; 1592 ti,sci = <&sms>; 1593 ti,sci-dev-id = <281>; 1594 ti,sci-rm-range-rchan = <0x21>; 1595 ti,sci-rm-range-tchan = <0x22>; 1596 }; 1597 1598 cpts@310d0000 { 1599 compatible = "ti,j721e-cpts"; 1600 reg = <0x00 0x310d0000 0x00 0x400>; 1601 reg-names = "cpts"; 1602 clocks = <&k3_clks 282 0>; 1603 clock-names = "cpts"; 1604 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1605 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1606 interrupts-extended = <&main_navss_intr 391>; 1607 interrupt-names = "cpts"; 1608 ti,cpts-periodic-outputs = <6>; 1609 ti,cpts-ext-ts-inputs = <8>; 1610 }; 1611 }; 1612 1613 main_cpsw0: ethernet@c000000 { 1614 compatible = "ti,j784s4-cpswxg-nuss"; 1615 reg = <0x00 0xc000000 0x00 0x200000>; 1616 reg-names = "cpsw_nuss"; 1617 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 1618 #address-cells = <2>; 1619 #size-cells = <2>; 1620 dma-coherent; 1621 clocks = <&k3_clks 64 0>; 1622 clock-names = "fck"; 1623 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1624 1625 dmas = <&main_udmap 0xca00>, 1626 <&main_udmap 0xca01>, 1627 <&main_udmap 0xca02>, 1628 <&main_udmap 0xca03>, 1629 <&main_udmap 0xca04>, 1630 <&main_udmap 0xca05>, 1631 <&main_udmap 0xca06>, 1632 <&main_udmap 0xca07>, 1633 <&main_udmap 0x4a00>; 1634 dma-names = "tx0", "tx1", "tx2", "tx3", 1635 "tx4", "tx5", "tx6", "tx7", 1636 "rx"; 1637 1638 status = "disabled"; 1639 1640 ethernet-ports { 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 1644 main_cpsw0_port1: port@1 { 1645 reg = <1>; 1646 label = "port1"; 1647 ti,mac-only; 1648 status = "disabled"; 1649 }; 1650 1651 main_cpsw0_port2: port@2 { 1652 reg = <2>; 1653 label = "port2"; 1654 ti,mac-only; 1655 status = "disabled"; 1656 }; 1657 1658 main_cpsw0_port3: port@3 { 1659 reg = <3>; 1660 label = "port3"; 1661 ti,mac-only; 1662 status = "disabled"; 1663 }; 1664 1665 main_cpsw0_port4: port@4 { 1666 reg = <4>; 1667 label = "port4"; 1668 ti,mac-only; 1669 status = "disabled"; 1670 }; 1671 1672 main_cpsw0_port5: port@5 { 1673 reg = <5>; 1674 label = "port5"; 1675 ti,mac-only; 1676 status = "disabled"; 1677 }; 1678 1679 main_cpsw0_port6: port@6 { 1680 reg = <6>; 1681 label = "port6"; 1682 ti,mac-only; 1683 status = "disabled"; 1684 }; 1685 1686 main_cpsw0_port7: port@7 { 1687 reg = <7>; 1688 label = "port7"; 1689 ti,mac-only; 1690 status = "disabled"; 1691 }; 1692 1693 main_cpsw0_port8: port@8 { 1694 reg = <8>; 1695 label = "port8"; 1696 ti,mac-only; 1697 status = "disabled"; 1698 }; 1699 }; 1700 1701 main_cpsw0_mdio: mdio@f00 { 1702 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1703 reg = <0x00 0xf00 0x00 0x100>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 clocks = <&k3_clks 64 0>; 1707 clock-names = "fck"; 1708 bus_freq = <1000000>; 1709 status = "disabled"; 1710 }; 1711 1712 cpts@3d000 { 1713 compatible = "ti,am65-cpts"; 1714 reg = <0x00 0x3d000 0x00 0x400>; 1715 clocks = <&k3_clks 64 3>; 1716 clock-names = "cpts"; 1717 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1718 interrupt-names = "cpts"; 1719 ti,cpts-ext-ts-inputs = <4>; 1720 ti,cpts-periodic-outputs = <2>; 1721 }; 1722 }; 1723 1724 main_cpsw1: ethernet@c200000 { 1725 compatible = "ti,j721e-cpsw-nuss"; 1726 reg = <0x00 0xc200000 0x00 0x200000>; 1727 reg-names = "cpsw_nuss"; 1728 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; 1729 #address-cells = <2>; 1730 #size-cells = <2>; 1731 dma-coherent; 1732 clocks = <&k3_clks 62 0>; 1733 clock-names = "fck"; 1734 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1735 1736 dmas = <&main_udmap 0xc640>, 1737 <&main_udmap 0xc641>, 1738 <&main_udmap 0xc642>, 1739 <&main_udmap 0xc643>, 1740 <&main_udmap 0xc644>, 1741 <&main_udmap 0xc645>, 1742 <&main_udmap 0xc646>, 1743 <&main_udmap 0xc647>, 1744 <&main_udmap 0x4640>; 1745 dma-names = "tx0", "tx1", "tx2", "tx3", 1746 "tx4", "tx5", "tx6", "tx7", 1747 "rx"; 1748 1749 status = "disabled"; 1750 1751 ethernet-ports { 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 1755 main_cpsw1_port1: port@1 { 1756 reg = <1>; 1757 label = "port1"; 1758 phys = <&cpsw1_phy_gmii_sel 1>; 1759 ti,mac-only; 1760 status = "disabled"; 1761 }; 1762 }; 1763 1764 main_cpsw1_mdio: mdio@f00 { 1765 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 1766 reg = <0x00 0xf00 0x00 0x100>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 clocks = <&k3_clks 62 0>; 1770 clock-names = "fck"; 1771 bus_freq = <1000000>; 1772 status = "disabled"; 1773 }; 1774 1775 cpts@3d000 { 1776 compatible = "ti,am65-cpts"; 1777 reg = <0x00 0x3d000 0x00 0x400>; 1778 clocks = <&k3_clks 62 3>; 1779 clock-names = "cpts"; 1780 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1781 interrupt-names = "cpts"; 1782 ti,cpts-ext-ts-inputs = <4>; 1783 ti,cpts-periodic-outputs = <2>; 1784 }; 1785 }; 1786 1787 main_mcan0: can@2701000 { 1788 compatible = "bosch,m_can"; 1789 reg = <0x00 0x02701000 0x00 0x200>, 1790 <0x00 0x02708000 0x00 0x8000>; 1791 reg-names = "m_can", "message_ram"; 1792 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1793 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1794 clock-names = "hclk", "cclk"; 1795 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1797 interrupt-names = "int0", "int1"; 1798 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1799 status = "disabled"; 1800 }; 1801 1802 main_mcan1: can@2711000 { 1803 compatible = "bosch,m_can"; 1804 reg = <0x00 0x02711000 0x00 0x200>, 1805 <0x00 0x02718000 0x00 0x8000>; 1806 reg-names = "m_can", "message_ram"; 1807 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1808 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1809 clock-names = "hclk", "cclk"; 1810 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1812 interrupt-names = "int0", "int1"; 1813 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1814 status = "disabled"; 1815 }; 1816 1817 main_mcan2: can@2721000 { 1818 compatible = "bosch,m_can"; 1819 reg = <0x00 0x02721000 0x00 0x200>, 1820 <0x00 0x02728000 0x00 0x8000>; 1821 reg-names = "m_can", "message_ram"; 1822 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1823 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1824 clock-names = "hclk", "cclk"; 1825 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1827 interrupt-names = "int0", "int1"; 1828 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1829 status = "disabled"; 1830 }; 1831 1832 main_mcan3: can@2731000 { 1833 compatible = "bosch,m_can"; 1834 reg = <0x00 0x02731000 0x00 0x200>, 1835 <0x00 0x02738000 0x00 0x8000>; 1836 reg-names = "m_can", "message_ram"; 1837 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1838 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1839 clock-names = "hclk", "cclk"; 1840 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1842 interrupt-names = "int0", "int1"; 1843 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1844 status = "disabled"; 1845 }; 1846 1847 main_mcan4: can@2741000 { 1848 compatible = "bosch,m_can"; 1849 reg = <0x00 0x02741000 0x00 0x200>, 1850 <0x00 0x02748000 0x00 0x8000>; 1851 reg-names = "m_can", "message_ram"; 1852 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1853 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1854 clock-names = "hclk", "cclk"; 1855 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1857 interrupt-names = "int0", "int1"; 1858 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1859 status = "disabled"; 1860 }; 1861 1862 main_mcan5: can@2751000 { 1863 compatible = "bosch,m_can"; 1864 reg = <0x00 0x02751000 0x00 0x200>, 1865 <0x00 0x02758000 0x00 0x8000>; 1866 reg-names = "m_can", "message_ram"; 1867 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1868 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1869 clock-names = "hclk", "cclk"; 1870 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1872 interrupt-names = "int0", "int1"; 1873 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1874 status = "disabled"; 1875 }; 1876 1877 main_mcan6: can@2761000 { 1878 compatible = "bosch,m_can"; 1879 reg = <0x00 0x02761000 0x00 0x200>, 1880 <0x00 0x02768000 0x00 0x8000>; 1881 reg-names = "m_can", "message_ram"; 1882 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1883 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1884 clock-names = "hclk", "cclk"; 1885 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1887 interrupt-names = "int0", "int1"; 1888 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1889 status = "disabled"; 1890 }; 1891 1892 main_mcan7: can@2771000 { 1893 compatible = "bosch,m_can"; 1894 reg = <0x00 0x02771000 0x00 0x200>, 1895 <0x00 0x02778000 0x00 0x8000>; 1896 reg-names = "m_can", "message_ram"; 1897 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1898 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1899 clock-names = "hclk", "cclk"; 1900 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1902 interrupt-names = "int0", "int1"; 1903 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1904 status = "disabled"; 1905 }; 1906 1907 main_mcan8: can@2781000 { 1908 compatible = "bosch,m_can"; 1909 reg = <0x00 0x02781000 0x00 0x200>, 1910 <0x00 0x02788000 0x00 0x8000>; 1911 reg-names = "m_can", "message_ram"; 1912 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1913 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1914 clock-names = "hclk", "cclk"; 1915 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1917 interrupt-names = "int0", "int1"; 1918 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1919 status = "disabled"; 1920 }; 1921 1922 main_mcan9: can@2791000 { 1923 compatible = "bosch,m_can"; 1924 reg = <0x00 0x02791000 0x00 0x200>, 1925 <0x00 0x02798000 0x00 0x8000>; 1926 reg-names = "m_can", "message_ram"; 1927 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1928 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1929 clock-names = "hclk", "cclk"; 1930 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1932 interrupt-names = "int0", "int1"; 1933 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1934 status = "disabled"; 1935 }; 1936 1937 main_mcan10: can@27a1000 { 1938 compatible = "bosch,m_can"; 1939 reg = <0x00 0x027a1000 0x00 0x200>, 1940 <0x00 0x027a8000 0x00 0x8000>; 1941 reg-names = "m_can", "message_ram"; 1942 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1943 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1944 clock-names = "hclk", "cclk"; 1945 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1947 interrupt-names = "int0", "int1"; 1948 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1949 status = "disabled"; 1950 }; 1951 1952 main_mcan11: can@27b1000 { 1953 compatible = "bosch,m_can"; 1954 reg = <0x00 0x027b1000 0x00 0x200>, 1955 <0x00 0x027b8000 0x00 0x8000>; 1956 reg-names = "m_can", "message_ram"; 1957 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1958 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1959 clock-names = "hclk", "cclk"; 1960 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1962 interrupt-names = "int0", "int1"; 1963 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1964 status = "disabled"; 1965 }; 1966 1967 main_mcan12: can@27c1000 { 1968 compatible = "bosch,m_can"; 1969 reg = <0x00 0x027c1000 0x00 0x200>, 1970 <0x00 0x027c8000 0x00 0x8000>; 1971 reg-names = "m_can", "message_ram"; 1972 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1973 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1974 clock-names = "hclk", "cclk"; 1975 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1977 interrupt-names = "int0", "int1"; 1978 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1979 status = "disabled"; 1980 }; 1981 1982 main_mcan13: can@27d1000 { 1983 compatible = "bosch,m_can"; 1984 reg = <0x00 0x027d1000 0x00 0x200>, 1985 <0x00 0x027d8000 0x00 0x8000>; 1986 reg-names = "m_can", "message_ram"; 1987 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1988 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1989 clock-names = "hclk", "cclk"; 1990 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1992 interrupt-names = "int0", "int1"; 1993 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1994 status = "disabled"; 1995 }; 1996 1997 main_mcan14: can@2681000 { 1998 compatible = "bosch,m_can"; 1999 reg = <0x00 0x02681000 0x00 0x200>, 2000 <0x00 0x02688000 0x00 0x8000>; 2001 reg-names = "m_can", "message_ram"; 2002 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 2003 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 2004 clock-names = "hclk", "cclk"; 2005 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 2007 interrupt-names = "int0", "int1"; 2008 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2009 status = "disabled"; 2010 }; 2011 2012 main_mcan15: can@2691000 { 2013 compatible = "bosch,m_can"; 2014 reg = <0x00 0x02691000 0x00 0x200>, 2015 <0x00 0x02698000 0x00 0x8000>; 2016 reg-names = "m_can", "message_ram"; 2017 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 2018 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 2019 clock-names = "hclk", "cclk"; 2020 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 2022 interrupt-names = "int0", "int1"; 2023 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2024 status = "disabled"; 2025 }; 2026 2027 main_mcan16: can@26a1000 { 2028 compatible = "bosch,m_can"; 2029 reg = <0x00 0x026a1000 0x00 0x200>, 2030 <0x00 0x026a8000 0x00 0x8000>; 2031 reg-names = "m_can", "message_ram"; 2032 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 2033 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 2034 clock-names = "hclk", "cclk"; 2035 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2037 interrupt-names = "int0", "int1"; 2038 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2039 status = "disabled"; 2040 }; 2041 2042 main_mcan17: can@26b1000 { 2043 compatible = "bosch,m_can"; 2044 reg = <0x00 0x026b1000 0x00 0x200>, 2045 <0x00 0x026b8000 0x00 0x8000>; 2046 reg-names = "m_can", "message_ram"; 2047 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 2048 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 2049 clock-names = "hclk", "cclk"; 2050 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 2052 interrupt-names = "int0", "int1"; 2053 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2054 status = "disabled"; 2055 }; 2056 2057 main_spi0: spi@2100000 { 2058 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2059 reg = <0x00 0x02100000 0x00 0x400>; 2060 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2061 #address-cells = <1>; 2062 #size-cells = <0>; 2063 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 2064 clocks = <&k3_clks 376 0>; 2065 status = "disabled"; 2066 }; 2067 2068 main_spi1: spi@2110000 { 2069 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2070 reg = <0x00 0x02110000 0x00 0x400>; 2071 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 2075 clocks = <&k3_clks 377 0>; 2076 status = "disabled"; 2077 }; 2078 2079 main_spi2: spi@2120000 { 2080 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2081 reg = <0x00 0x02120000 0x00 0x400>; 2082 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 2086 clocks = <&k3_clks 378 0>; 2087 status = "disabled"; 2088 }; 2089 2090 main_spi3: spi@2130000 { 2091 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2092 reg = <0x00 0x02130000 0x00 0x400>; 2093 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2094 #address-cells = <1>; 2095 #size-cells = <0>; 2096 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 2097 clocks = <&k3_clks 379 0>; 2098 status = "disabled"; 2099 }; 2100 2101 main_spi4: spi@2140000 { 2102 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2103 reg = <0x00 0x02140000 0x00 0x400>; 2104 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 2108 clocks = <&k3_clks 380 0>; 2109 status = "disabled"; 2110 }; 2111 2112 main_spi5: spi@2150000 { 2113 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2114 reg = <0x00 0x02150000 0x00 0x400>; 2115 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2116 #address-cells = <1>; 2117 #size-cells = <0>; 2118 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 2119 clocks = <&k3_clks 381 0>; 2120 status = "disabled"; 2121 }; 2122 2123 main_spi6: spi@2160000 { 2124 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2125 reg = <0x00 0x02160000 0x00 0x400>; 2126 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 2130 clocks = <&k3_clks 382 0>; 2131 status = "disabled"; 2132 }; 2133 2134 main_spi7: spi@2170000 { 2135 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2136 reg = <0x00 0x02170000 0x00 0x400>; 2137 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 2141 clocks = <&k3_clks 383 0>; 2142 status = "disabled"; 2143 }; 2144 2145 ufs_wrapper: ufs-wrapper@4e80000 { 2146 compatible = "ti,j721e-ufs"; 2147 reg = <0x00 0x4e80000 0x00 0x100>; 2148 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 2149 clocks = <&k3_clks 387 3>; 2150 assigned-clocks = <&k3_clks 387 3>; 2151 assigned-clock-parents = <&k3_clks 387 6>; 2152 ranges; 2153 #address-cells = <2>; 2154 #size-cells = <2>; 2155 status = "disabled"; 2156 2157 ufs@4e84000 { 2158 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 2159 reg = <0x00 0x4e84000 0x00 0x10000>; 2160 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2161 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 2162 <19200000 19200000>; 2163 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 2164 clock-names = "core_clk", "phy_clk", "ref_clk"; 2165 dma-coherent; 2166 }; 2167 }; 2168 2169 main_r5fss0: r5fss@5c00000 { 2170 compatible = "ti,j721s2-r5fss"; 2171 ti,cluster-mode = <1>; 2172 #address-cells = <1>; 2173 #size-cells = <1>; 2174 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2175 <0x5d00000 0x00 0x5d00000 0x20000>; 2176 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 2177 status = "disabled"; 2178 2179 main_r5fss0_core0: r5f@5c00000 { 2180 compatible = "ti,j721s2-r5f"; 2181 reg = <0x5c00000 0x00010000>, 2182 <0x5c10000 0x00010000>; 2183 reg-names = "atcm", "btcm"; 2184 ti,sci = <&sms>; 2185 ti,sci-dev-id = <339>; 2186 ti,sci-proc-ids = <0x06 0xff>; 2187 resets = <&k3_reset 339 1>; 2188 firmware-name = "j784s4-main-r5f0_0-fw"; 2189 ti,atcm-enable = <1>; 2190 ti,btcm-enable = <1>; 2191 ti,loczrama = <1>; 2192 status = "disabled"; 2193 }; 2194 2195 main_r5fss0_core1: r5f@5d00000 { 2196 compatible = "ti,j721s2-r5f"; 2197 reg = <0x5d00000 0x00010000>, 2198 <0x5d10000 0x00010000>; 2199 reg-names = "atcm", "btcm"; 2200 ti,sci = <&sms>; 2201 ti,sci-dev-id = <340>; 2202 ti,sci-proc-ids = <0x07 0xff>; 2203 resets = <&k3_reset 340 1>; 2204 firmware-name = "j784s4-main-r5f0_1-fw"; 2205 ti,atcm-enable = <1>; 2206 ti,btcm-enable = <1>; 2207 ti,loczrama = <1>; 2208 status = "disabled"; 2209 }; 2210 }; 2211 2212 main_r5fss1: r5fss@5e00000 { 2213 compatible = "ti,j721s2-r5fss"; 2214 ti,cluster-mode = <1>; 2215 #address-cells = <1>; 2216 #size-cells = <1>; 2217 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2218 <0x5f00000 0x00 0x5f00000 0x20000>; 2219 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 2220 status = "disabled"; 2221 2222 main_r5fss1_core0: r5f@5e00000 { 2223 compatible = "ti,j721s2-r5f"; 2224 reg = <0x5e00000 0x00010000>, 2225 <0x5e10000 0x00010000>; 2226 reg-names = "atcm", "btcm"; 2227 ti,sci = <&sms>; 2228 ti,sci-dev-id = <341>; 2229 ti,sci-proc-ids = <0x08 0xff>; 2230 resets = <&k3_reset 341 1>; 2231 firmware-name = "j784s4-main-r5f1_0-fw"; 2232 ti,atcm-enable = <1>; 2233 ti,btcm-enable = <1>; 2234 ti,loczrama = <1>; 2235 status = "disabled"; 2236 }; 2237 2238 main_r5fss1_core1: r5f@5f00000 { 2239 compatible = "ti,j721s2-r5f"; 2240 reg = <0x5f00000 0x00010000>, 2241 <0x5f10000 0x00010000>; 2242 reg-names = "atcm", "btcm"; 2243 ti,sci = <&sms>; 2244 ti,sci-dev-id = <342>; 2245 ti,sci-proc-ids = <0x09 0xff>; 2246 resets = <&k3_reset 342 1>; 2247 firmware-name = "j784s4-main-r5f1_1-fw"; 2248 ti,atcm-enable = <1>; 2249 ti,btcm-enable = <1>; 2250 ti,loczrama = <1>; 2251 status = "disabled"; 2252 }; 2253 }; 2254 2255 main_r5fss2: r5fss@5900000 { 2256 compatible = "ti,j721s2-r5fss"; 2257 ti,cluster-mode = <1>; 2258 #address-cells = <1>; 2259 #size-cells = <1>; 2260 ranges = <0x5900000 0x00 0x5900000 0x20000>, 2261 <0x5a00000 0x00 0x5a00000 0x20000>; 2262 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 2263 status = "disabled"; 2264 2265 main_r5fss2_core0: r5f@5900000 { 2266 compatible = "ti,j721s2-r5f"; 2267 reg = <0x5900000 0x00010000>, 2268 <0x5910000 0x00010000>; 2269 reg-names = "atcm", "btcm"; 2270 ti,sci = <&sms>; 2271 ti,sci-dev-id = <343>; 2272 ti,sci-proc-ids = <0x0a 0xff>; 2273 resets = <&k3_reset 343 1>; 2274 firmware-name = "j784s4-main-r5f2_0-fw"; 2275 ti,atcm-enable = <1>; 2276 ti,btcm-enable = <1>; 2277 ti,loczrama = <1>; 2278 status = "disabled"; 2279 }; 2280 2281 main_r5fss2_core1: r5f@5a00000 { 2282 compatible = "ti,j721s2-r5f"; 2283 reg = <0x5a00000 0x00010000>, 2284 <0x5a10000 0x00010000>; 2285 reg-names = "atcm", "btcm"; 2286 ti,sci = <&sms>; 2287 ti,sci-dev-id = <344>; 2288 ti,sci-proc-ids = <0x0b 0xff>; 2289 resets = <&k3_reset 344 1>; 2290 firmware-name = "j784s4-main-r5f2_1-fw"; 2291 ti,atcm-enable = <1>; 2292 ti,btcm-enable = <1>; 2293 ti,loczrama = <1>; 2294 status = "disabled"; 2295 }; 2296 }; 2297 2298 c71_0: dsp@64800000 { 2299 compatible = "ti,j721s2-c71-dsp"; 2300 reg = <0x00 0x64800000 0x00 0x00080000>, 2301 <0x00 0x64e00000 0x00 0x0000c000>; 2302 reg-names = "l2sram", "l1dram"; 2303 ti,sci = <&sms>; 2304 ti,sci-dev-id = <30>; 2305 ti,sci-proc-ids = <0x30 0xff>; 2306 resets = <&k3_reset 30 1>; 2307 firmware-name = "j784s4-c71_0-fw"; 2308 status = "disabled"; 2309 }; 2310 2311 c71_1: dsp@65800000 { 2312 compatible = "ti,j721s2-c71-dsp"; 2313 reg = <0x00 0x65800000 0x00 0x00080000>, 2314 <0x00 0x65e00000 0x00 0x0000c000>; 2315 reg-names = "l2sram", "l1dram"; 2316 ti,sci = <&sms>; 2317 ti,sci-dev-id = <33>; 2318 ti,sci-proc-ids = <0x31 0xff>; 2319 resets = <&k3_reset 33 1>; 2320 firmware-name = "j784s4-c71_1-fw"; 2321 status = "disabled"; 2322 }; 2323 2324 c71_2: dsp@66800000 { 2325 compatible = "ti,j721s2-c71-dsp"; 2326 reg = <0x00 0x66800000 0x00 0x00080000>, 2327 <0x00 0x66e00000 0x00 0x0000c000>; 2328 reg-names = "l2sram", "l1dram"; 2329 ti,sci = <&sms>; 2330 ti,sci-dev-id = <37>; 2331 ti,sci-proc-ids = <0x32 0xff>; 2332 resets = <&k3_reset 37 1>; 2333 firmware-name = "j784s4-c71_2-fw"; 2334 status = "disabled"; 2335 }; 2336 2337 main_esm: esm@700000 { 2338 compatible = "ti,j721e-esm"; 2339 reg = <0x00 0x700000 0x00 0x1000>; 2340 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2341 <695>; 2342 bootph-pre-ram; 2343 }; 2344 2345 watchdog0: watchdog@2200000 { 2346 compatible = "ti,j7-rti-wdt"; 2347 reg = <0x00 0x2200000 0x00 0x100>; 2348 clocks = <&k3_clks 348 0>; 2349 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2350 assigned-clocks = <&k3_clks 348 0>; 2351 assigned-clock-parents = <&k3_clks 348 4>; 2352 }; 2353 2354 watchdog1: watchdog@2210000 { 2355 compatible = "ti,j7-rti-wdt"; 2356 reg = <0x00 0x2210000 0x00 0x100>; 2357 clocks = <&k3_clks 349 0>; 2358 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2359 assigned-clocks = <&k3_clks 349 0>; 2360 assigned-clock-parents = <&k3_clks 349 4>; 2361 }; 2362 2363 watchdog2: watchdog@2220000 { 2364 compatible = "ti,j7-rti-wdt"; 2365 reg = <0x00 0x2220000 0x00 0x100>; 2366 clocks = <&k3_clks 350 0>; 2367 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2368 assigned-clocks = <&k3_clks 350 0>; 2369 assigned-clock-parents = <&k3_clks 350 4>; 2370 }; 2371 2372 watchdog3: watchdog@2230000 { 2373 compatible = "ti,j7-rti-wdt"; 2374 reg = <0x00 0x2230000 0x00 0x100>; 2375 clocks = <&k3_clks 351 0>; 2376 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2377 assigned-clocks = <&k3_clks 351 0>; 2378 assigned-clock-parents = <&k3_clks 351 4>; 2379 }; 2380 2381 /* 2382 * The following RTI instances are coupled with MCU R5Fs, c7x and 2383 * GPU so keeping them reserved as these will be used by their 2384 * respective firmware 2385 */ 2386 watchdog8: watchdog@22f0000 { 2387 compatible = "ti,j7-rti-wdt"; 2388 reg = <0x00 0x22f0000 0x00 0x100>; 2389 clocks = <&k3_clks 360 0>; 2390 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2391 assigned-clocks = <&k3_clks 360 0>; 2392 assigned-clock-parents = <&k3_clks 360 4>; 2393 /* reserved for GPU */ 2394 status = "reserved"; 2395 }; 2396 2397 watchdog9: watchdog@2300000 { 2398 compatible = "ti,j7-rti-wdt"; 2399 reg = <0x00 0x2300000 0x00 0x100>; 2400 clocks = <&k3_clks 356 0>; 2401 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2402 assigned-clocks = <&k3_clks 356 0>; 2403 assigned-clock-parents = <&k3_clks 356 4>; 2404 /* reserved for C7X_0 DSP */ 2405 status = "reserved"; 2406 }; 2407 2408 watchdog10: watchdog@2310000 { 2409 compatible = "ti,j7-rti-wdt"; 2410 reg = <0x00 0x2310000 0x00 0x100>; 2411 clocks = <&k3_clks 357 0>; 2412 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2413 assigned-clocks = <&k3_clks 357 0>; 2414 assigned-clock-parents = <&k3_clks 357 4>; 2415 /* reserved for C7X_1 DSP */ 2416 status = "reserved"; 2417 }; 2418 2419 watchdog11: watchdog@2320000 { 2420 compatible = "ti,j7-rti-wdt"; 2421 reg = <0x00 0x2320000 0x00 0x100>; 2422 clocks = <&k3_clks 358 0>; 2423 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2424 assigned-clocks = <&k3_clks 358 0>; 2425 assigned-clock-parents = <&k3_clks 358 4>; 2426 /* reserved for C7X_2 DSP */ 2427 status = "reserved"; 2428 }; 2429 2430 watchdog12: watchdog@2330000 { 2431 compatible = "ti,j7-rti-wdt"; 2432 reg = <0x00 0x2330000 0x00 0x100>; 2433 clocks = <&k3_clks 359 0>; 2434 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2435 assigned-clocks = <&k3_clks 359 0>; 2436 assigned-clock-parents = <&k3_clks 359 4>; 2437 /* reserved for C7X_3 DSP */ 2438 status = "reserved"; 2439 }; 2440 2441 watchdog13: watchdog@23c0000 { 2442 compatible = "ti,j7-rti-wdt"; 2443 reg = <0x00 0x23c0000 0x00 0x100>; 2444 clocks = <&k3_clks 361 0>; 2445 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2446 assigned-clocks = <&k3_clks 361 0>; 2447 assigned-clock-parents = <&k3_clks 361 4>; 2448 /* reserved for MAIN_R5F0_0 */ 2449 status = "reserved"; 2450 }; 2451 2452 watchdog14: watchdog@23d0000 { 2453 compatible = "ti,j7-rti-wdt"; 2454 reg = <0x00 0x23d0000 0x00 0x100>; 2455 clocks = <&k3_clks 362 0>; 2456 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2457 assigned-clocks = <&k3_clks 362 0>; 2458 assigned-clock-parents = <&k3_clks 362 4>; 2459 /* reserved for MAIN_R5F0_1 */ 2460 status = "reserved"; 2461 }; 2462 2463 watchdog15: watchdog@23e0000 { 2464 compatible = "ti,j7-rti-wdt"; 2465 reg = <0x00 0x23e0000 0x00 0x100>; 2466 clocks = <&k3_clks 363 0>; 2467 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2468 assigned-clocks = <&k3_clks 363 0>; 2469 assigned-clock-parents = <&k3_clks 363 4>; 2470 /* reserved for MAIN_R5F1_0 */ 2471 status = "reserved"; 2472 }; 2473 2474 watchdog16: watchdog@23f0000 { 2475 compatible = "ti,j7-rti-wdt"; 2476 reg = <0x00 0x23f0000 0x00 0x100>; 2477 clocks = <&k3_clks 364 0>; 2478 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2479 assigned-clocks = <&k3_clks 364 0>; 2480 assigned-clock-parents = <&k3_clks 364 4>; 2481 /* reserved for MAIN_R5F1_1 */ 2482 status = "reserved"; 2483 }; 2484 2485 watchdog17: watchdog@2540000 { 2486 compatible = "ti,j7-rti-wdt"; 2487 reg = <0x00 0x2540000 0x00 0x100>; 2488 clocks = <&k3_clks 365 0>; 2489 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2490 assigned-clocks = <&k3_clks 365 0>; 2491 assigned-clock-parents = <&k3_clks 366 4>; 2492 /* reserved for MAIN_R5F2_0 */ 2493 status = "reserved"; 2494 }; 2495 2496 watchdog18: watchdog@2550000 { 2497 compatible = "ti,j7-rti-wdt"; 2498 reg = <0x00 0x2550000 0x00 0x100>; 2499 clocks = <&k3_clks 366 0>; 2500 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2501 assigned-clocks = <&k3_clks 366 0>; 2502 assigned-clock-parents = <&k3_clks 366 4>; 2503 /* reserved for MAIN_R5F2_1 */ 2504 status = "reserved"; 2505 }; 2506 2507 dphy_tx0: phy@4480000 { 2508 compatible = "ti,j721e-dphy"; 2509 reg = <0x00 0x04480000 0x00 0x00001000>; 2510 clocks = <&k3_clks 402 20>, <&k3_clks 402 3>; 2511 clock-names = "psm", "pll_ref"; 2512 #phy-cells = <0>; 2513 power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; 2514 assigned-clocks = <&k3_clks 402 3>; 2515 assigned-clock-parents = <&k3_clks 402 4>; 2516 assigned-clock-rates = <19200000>; 2517 status = "disabled"; 2518 }; 2519 2520 dsi0: dsi@4800000 { 2521 compatible = "ti,j721e-dsi"; 2522 reg = <0x00 0x04800000 0x00 0x00100000>, 2523 <0x00 0x04710000 0x00 0x00000100>; 2524 clocks = <&k3_clks 215 2>, <&k3_clks 215 5>; 2525 clock-names = "dsi_p_clk", "dsi_sys_clk"; 2526 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 2527 interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 2528 phys = <&dphy_tx0>; 2529 phy-names = "dphy"; 2530 status = "disabled"; 2531 2532 dsi0_ports: ports { 2533 #address-cells = <1>; 2534 #size-cells = <0>; 2535 2536 port@0 { 2537 reg = <0>; 2538 }; 2539 2540 port@1 { 2541 reg = <1>; 2542 }; 2543 }; 2544 }; 2545 2546 mhdp: bridge@a000000 { 2547 compatible = "ti,j721e-mhdp8546"; 2548 reg = <0x0 0xa000000 0x0 0x30a00>, 2549 <0x0 0x4f40000 0x0 0x20>; 2550 reg-names = "mhdptx", "j721e-intg"; 2551 clocks = <&k3_clks 217 11>; 2552 interrupt-parent = <&gic500>; 2553 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2554 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2555 status = "disabled"; 2556 2557 dp0_ports: ports { 2558 #address-cells = <1>; 2559 #size-cells = <0>; 2560 /* Remote-endpoints are on the boards so 2561 * ports are defined in the platform dt file. 2562 */ 2563 }; 2564 }; 2565 2566 dss: dss@4a00000 { 2567 compatible = "ti,j721e-dss"; 2568 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2569 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2570 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2571 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2572 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2573 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2574 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2575 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2576 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2577 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2578 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2579 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2580 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2581 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2582 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2583 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2584 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2585 reg-names = "common_m", "common_s0", 2586 "common_s1", "common_s2", 2587 "vidl1", "vidl2","vid1","vid2", 2588 "ovr1", "ovr2", "ovr3", "ovr4", 2589 "vp1", "vp2", "vp3", "vp4", 2590 "wb"; 2591 clocks = <&k3_clks 218 0>, 2592 <&k3_clks 218 2>, 2593 <&k3_clks 218 5>, 2594 <&k3_clks 218 14>, 2595 <&k3_clks 218 18>; 2596 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2597 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2598 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2602 interrupt-names = "common_m", 2603 "common_s0", 2604 "common_s1", 2605 "common_s2"; 2606 status = "disabled"; 2607 2608 dss_ports: ports { 2609 /* Ports that DSS drives are platform specific 2610 * so they are defined in platform dt file. 2611 */ 2612 }; 2613 }; 2614 2615 mcasp0: mcasp@2b00000 { 2616 compatible = "ti,am33xx-mcasp-audio"; 2617 reg = <0x00 0x02b00000 0x00 0x2000>, 2618 <0x00 0x02b08000 0x00 0x1000>; 2619 reg-names = "mpu","dat"; 2620 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 2622 interrupt-names = "tx", "rx"; 2623 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 2624 dma-names = "tx", "rx"; 2625 clocks = <&k3_clks 265 0>; 2626 clock-names = "fck"; 2627 assigned-clocks = <&k3_clks 265 0>; 2628 assigned-clock-parents = <&k3_clks 265 1>; 2629 power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; 2630 status = "disabled"; 2631 }; 2632 2633 mcasp1: mcasp@2b10000 { 2634 compatible = "ti,am33xx-mcasp-audio"; 2635 reg = <0x00 0x02b10000 0x00 0x2000>, 2636 <0x00 0x02b18000 0x00 0x1000>; 2637 reg-names = "mpu","dat"; 2638 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2640 interrupt-names = "tx", "rx"; 2641 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2642 dma-names = "tx", "rx"; 2643 clocks = <&k3_clks 266 0>; 2644 clock-names = "fck"; 2645 assigned-clocks = <&k3_clks 266 0>; 2646 assigned-clock-parents = <&k3_clks 266 1>; 2647 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2648 status = "disabled"; 2649 }; 2650 2651 mcasp2: mcasp@2b20000 { 2652 compatible = "ti,am33xx-mcasp-audio"; 2653 reg = <0x00 0x02b20000 0x00 0x2000>, 2654 <0x00 0x02b28000 0x00 0x1000>; 2655 reg-names = "mpu","dat"; 2656 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2658 interrupt-names = "tx", "rx"; 2659 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2660 dma-names = "tx", "rx"; 2661 clocks = <&k3_clks 267 0>; 2662 clock-names = "fck"; 2663 assigned-clocks = <&k3_clks 267 0>; 2664 assigned-clock-parents = <&k3_clks 267 1>; 2665 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2666 status = "disabled"; 2667 }; 2668 2669 mcasp3: mcasp@2b30000 { 2670 compatible = "ti,am33xx-mcasp-audio"; 2671 reg = <0x00 0x02b30000 0x00 0x2000>, 2672 <0x00 0x02b38000 0x00 0x1000>; 2673 reg-names = "mpu","dat"; 2674 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2676 interrupt-names = "tx", "rx"; 2677 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; 2678 dma-names = "tx", "rx"; 2679 clocks = <&k3_clks 268 0>; 2680 clock-names = "fck"; 2681 assigned-clocks = <&k3_clks 268 0>; 2682 assigned-clock-parents = <&k3_clks 268 1>; 2683 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2684 status = "disabled"; 2685 }; 2686 2687 mcasp4: mcasp@2b40000 { 2688 compatible = "ti,am33xx-mcasp-audio"; 2689 reg = <0x00 0x02b40000 0x00 0x2000>, 2690 <0x00 0x02b48000 0x00 0x1000>; 2691 reg-names = "mpu","dat"; 2692 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2694 interrupt-names = "tx", "rx"; 2695 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; 2696 dma-names = "tx", "rx"; 2697 clocks = <&k3_clks 269 0>; 2698 clock-names = "fck"; 2699 assigned-clocks = <&k3_clks 269 0>; 2700 assigned-clock-parents = <&k3_clks 269 1>; 2701 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2702 status = "disabled"; 2703 }; 2704 2705 bist_main14: bist@33c0000 { 2706 compatible = "ti,j784s4-bist"; 2707 reg = <0x00 0x033c0000 0x00 0x400>, 2708 <0x00 0x0010c1a0 0x00 0x01c>; 2709 reg-names = "cfg", "ctrl_mmr"; 2710 clocks = <&k3_clks 237 7>; 2711 power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>; 2712 bootph-pre-ram; 2713 ti,sci-dev-id = <234>; 2714 }; 2715};
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