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k3-j784s4-j742s2-evm-common.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 6 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 7 */ 8 9#include <dt-bindings/phy/phy-cadence.h> 10 11/ { 12 chosen { 13 stdout-path = "serial2:115200n8"; 14 }; 15 16 aliases { 17 serial0 = &wkup_uart0; 18 serial1 = &mcu_uart0; 19 serial2 = &main_uart8; 20 mmc0 = &main_sdhci0; 21 mmc1 = &main_sdhci1; 22 i2c0 = &wkup_i2c0; 23 i2c3 = &main_i2c0; 24 ethernet0 = &mcu_cpsw_port1; 25 ethernet1 = &main_cpsw1_port1; 26 }; 27 28 reserved_memory: reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 secure_ddr: optee@9e800000 { 34 reg = <0x00 0x9e800000 0x00 0x01800000>; 35 no-map; 36 }; 37 38 mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { 39 compatible = "shared-dma-pool"; 40 reg = <0x00 0xa0000000 0x00 0x100000>; 41 no-map; 42 }; 43 44 mcu_r5fss0_core0_memory_region: memory@a0100000 { 45 compatible = "shared-dma-pool"; 46 reg = <0x00 0xa0100000 0x00 0xf00000>; 47 no-map; 48 }; 49 }; 50 51 evm_12v0: regulator-evm12v0 { 52 /* main supply */ 53 compatible = "regulator-fixed"; 54 regulator-name = "evm_12v0"; 55 regulator-min-microvolt = <12000000>; 56 regulator-max-microvolt = <12000000>; 57 regulator-always-on; 58 regulator-boot-on; 59 }; 60 61 vsys_3v3: regulator-vsys3v3 { 62 /* Output of LM5140 */ 63 compatible = "regulator-fixed"; 64 regulator-name = "vsys_3v3"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 vin-supply = <&evm_12v0>; 68 regulator-always-on; 69 regulator-boot-on; 70 }; 71 72 vsys_5v0: regulator-vsys5v0 { 73 /* Output of LM5140 */ 74 compatible = "regulator-fixed"; 75 regulator-name = "vsys_5v0"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 vin-supply = <&evm_12v0>; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 vdd_mmc1: regulator-sd { 84 /* Output of TPS22918 */ 85 compatible = "regulator-fixed"; 86 regulator-name = "vdd_mmc1"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-boot-on; 90 enable-active-high; 91 vin-supply = <&vsys_3v3>; 92 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 93 }; 94 95 vdd_sd_dv: regulator-TLV71033 { 96 /* Output of TLV71033 */ 97 compatible = "regulator-gpio"; 98 regulator-name = "tlv71033"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&vdd_sd_dv_pins_default>; 101 regulator-min-microvolt = <1800000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-boot-on; 104 vin-supply = <&vsys_5v0>; 105 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 106 states = <1800000 0x0>, 107 <3300000 0x1>; 108 }; 109 110 dp0_pwr_3v3: regulator-dp0-prw { 111 compatible = "regulator-fixed"; 112 regulator-name = "dp0-pwr"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 }; 118 119 dp0: connector-dp0 { 120 compatible = "dp-connector"; 121 label = "DP0"; 122 type = "full-size"; 123 dp-pwr-supply = <&dp0_pwr_3v3>; 124 125 port { 126 dp0_connector_in: endpoint { 127 remote-endpoint = <&dp0_out>; 128 }; 129 }; 130 }; 131 132 transceiver0: can-phy0 { 133 compatible = "ti,tcan1042"; 134 #phy-cells = <0>; 135 max-bitrate = <5000000>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 138 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; 139 }; 140 141 transceiver1: can-phy1 { 142 compatible = "ti,tcan1042"; 143 #phy-cells = <0>; 144 max-bitrate = <5000000>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 147 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 148 }; 149 150 transceiver2: can-phy2 { 151 /* standby pin has been grounded by default */ 152 compatible = "ti,tcan1042"; 153 #phy-cells = <0>; 154 max-bitrate = <5000000>; 155 }; 156 157 transceiver3: can-phy3 { 158 compatible = "ti,tcan1042"; 159 #phy-cells = <0>; 160 max-bitrate = <5000000>; 161 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 162 mux-states = <&mux1 1>; 163 }; 164 165 mux1: mux-controller { 166 compatible = "gpio-mux"; 167 #mux-state-cells = <1>; 168 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; 169 idle-state = <1>; 170 }; 171 172 codec_audio: sound { 173 compatible = "ti,j7200-cpb-audio"; 174 model = "j784s4-cpb"; 175 176 ti,cpb-mcasp = <&mcasp0>; 177 ti,cpb-codec = <&pcm3168a_1>; 178 179 clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, 180 <&k3_clks 157 34>, <&k3_clks 157 63>; 181 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", 182 "cpb-codec-scki", "cpb-codec-scki-48000"; 183 }; 184 185 vsys_io_1v8: regulator-vsys-io-1v8 { 186 compatible = "regulator-fixed"; 187 regulator-name = "vsys_io_1v8"; 188 regulator-min-microvolt = <1800000>; 189 regulator-max-microvolt = <1800000>; 190 regulator-always-on; 191 regulator-boot-on; 192 }; 193 194 vsys_io_1v2: regulator-vsys-io-1v2 { 195 compatible = "regulator-fixed"; 196 regulator-name = "vsys_io_1v2"; 197 regulator-min-microvolt = <1200000>; 198 regulator-max-microvolt = <1200000>; 199 regulator-always-on; 200 regulator-boot-on; 201 }; 202 203 edp1_refclk: clock-edp1-refclk { 204 compatible = "fixed-clock"; 205 clock-frequency = <19200000>; 206 #clock-cells = <0>; 207 }; 208 209 dp1_pwr_3v3: regulator-dp1-prw { 210 compatible = "regulator-fixed"; 211 regulator-name = "dp1-pwr"; 212 regulator-min-microvolt = <3300000>; 213 regulator-max-microvolt = <3300000>; 214 gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; 215 enable-active-high; 216 }; 217 218 dp1: connector-dp1 { 219 compatible = "dp-connector"; 220 label = "DP1"; 221 type = "full-size"; 222 dp-pwr-supply = <&dp1_pwr_3v3>; 223 224 port { 225 dp1_connector_in: endpoint { 226 remote-endpoint = <&dp1_out>; 227 }; 228 }; 229 }; 230}; 231 232&wkup_gpio0 { 233 status = "okay"; 234}; 235 236&main_pmx0 { 237 main_cpsw2g_default_pins: main-cpsw2g-default-pins { 238 pinctrl-single,pins = < 239 J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ 240 J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ 241 J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ 242 J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ 243 J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ 244 J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ 245 J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ 246 J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ 247 J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ 248 J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ 249 J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ 250 J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ 251 >; 252 }; 253 254 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { 255 pinctrl-single,pins = < 256 J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ 257 J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ 258 >; 259 }; 260 261 main_uart8_pins_default: main-uart8-default-pins { 262 bootph-all; 263 pinctrl-single,pins = < 264 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 265 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 266 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 267 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 268 >; 269 }; 270 271 main_i2c0_pins_default: main-i2c0-default-pins { 272 pinctrl-single,pins = < 273 J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ 274 J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ 275 >; 276 }; 277 278 main_i2c5_pins_default: main-i2c5-default-pins { 279 pinctrl-single,pins = < 280 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ 281 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ 282 >; 283 }; 284 285 main_mmc1_pins_default: main-mmc1-default-pins { 286 bootph-all; 287 pinctrl-single,pins = < 288 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 289 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 290 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 291 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 292 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 293 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 294 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 295 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 296 >; 297 }; 298 299 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 300 pinctrl-single,pins = < 301 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 302 >; 303 }; 304 305 dp0_pins_default: dp0-default-pins { 306 pinctrl-single,pins = < 307 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 308 >; 309 }; 310 311 main_i2c4_pins_default: main-i2c4-default-pins { 312 pinctrl-single,pins = < 313 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 314 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 315 >; 316 }; 317 318 main_mcan4_pins_default: main-mcan4-default-pins { 319 pinctrl-single,pins = < 320 J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ 321 J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ 322 >; 323 }; 324 325 main_mcan16_pins_default: main-mcan16-default-pins { 326 pinctrl-single,pins = < 327 J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ 328 J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ 329 >; 330 }; 331 332 main_usbss0_pins_default: main-usbss0-default-pins { 333 bootph-all; 334 pinctrl-single,pins = < 335 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 336 >; 337 }; 338 339 main_i2c3_pins_default: main-i2c3-default-pins { 340 pinctrl-single,pins = < 341 J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ 342 J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ 343 >; 344 }; 345 346 main_mcasp0_pins_default: main-mcasp0-default-pins { 347 pinctrl-single,pins = < 348 J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ 349 J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ 350 J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ 351 J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ 352 >; 353 }; 354 355 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 356 pinctrl-single,pins = < 357 J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ 358 >; 359 }; 360}; 361 362&wkup_pmx2 { 363 wkup_uart0_pins_default: wkup-uart0-default-pins { 364 bootph-all; 365 pinctrl-single,pins = < 366 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 367 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 368 >; 369 }; 370 371 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 372 bootph-all; 373 pinctrl-single,pins = < 374 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 375 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 376 >; 377 }; 378 379 mcu_uart0_pins_default: mcu-uart0-default-pins { 380 bootph-all; 381 pinctrl-single,pins = < 382 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 383 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 384 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 385 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 386 >; 387 }; 388 389 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 390 pinctrl-single,pins = < 391 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 392 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 393 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 394 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 395 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 396 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 397 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 398 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 399 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 400 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 401 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 402 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 403 >; 404 }; 405 406 mcu_mdio_pins_default: mcu-mdio-default-pins { 407 pinctrl-single,pins = < 408 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 409 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 410 >; 411 }; 412 413 mcu_adc0_pins_default: mcu-adc0-default-pins { 414 pinctrl-single,pins = < 415 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 416 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 417 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 418 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 419 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 420 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 421 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 422 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 423 >; 424 }; 425 426 mcu_adc1_pins_default: mcu-adc1-default-pins { 427 pinctrl-single,pins = < 428 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 429 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 430 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 431 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 432 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 433 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 434 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 435 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 436 >; 437 }; 438 439 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 440 pinctrl-single,pins = < 441 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 442 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 443 >; 444 }; 445 446 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 447 pinctrl-single,pins = < 448 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 449 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 450 >; 451 }; 452 453 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 454 pinctrl-single,pins = < 455 J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ 456 >; 457 }; 458 459 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 460 pinctrl-single,pins = < 461 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 462 >; 463 }; 464}; 465 466&wkup_pmx1 { 467 status = "okay"; 468 469 pmic_irq_pins_default: pmic-irq-default-pins { 470 pinctrl-single,pins = < 471 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 472 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 473 >; 474 }; 475}; 476 477&wkup_pmx0 { 478 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 479 bootph-all; 480 pinctrl-single,pins = < 481 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 482 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 483 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 484 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 485 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 486 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 487 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 488 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 489 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 490 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 491 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 492 >; 493 }; 494}; 495 496&wkup_pmx1 { 497 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 498 bootph-all; 499 pinctrl-single,pins = < 500 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 501 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 502 >; 503 }; 504 505 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 506 bootph-all; 507 pinctrl-single,pins = < 508 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 509 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 510 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 511 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 512 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 513 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 514 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 515 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 516 >; 517 }; 518}; 519 520&wkup_uart0 { 521 /* Firmware usage */ 522 status = "reserved"; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&wkup_uart0_pins_default>; 525}; 526 527&wkup_i2c0 { 528 bootph-all; 529 status = "okay"; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&wkup_i2c0_pins_default>; 532 clock-frequency = <400000>; 533 534 eeprom@50 { 535 /* CAV24C256WE-GT3 */ 536 compatible = "atmel,24c256"; 537 reg = <0x50>; 538 }; 539 540 tps659413: pmic@48 { 541 compatible = "ti,tps6594-q1"; 542 reg = <0x48>; 543 system-power-controller; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pmic_irq_pins_default>; 546 interrupt-parent = <&wkup_gpio0>; 547 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 ti,primary-pmic; 551 buck12-supply = <&vsys_3v3>; 552 buck3-supply = <&vsys_3v3>; 553 buck4-supply = <&vsys_3v3>; 554 buck5-supply = <&vsys_3v3>; 555 ldo1-supply = <&vsys_3v3>; 556 ldo2-supply = <&vsys_3v3>; 557 ldo3-supply = <&vsys_3v3>; 558 ldo4-supply = <&vsys_3v3>; 559 560 regulators { 561 bucka12: buck12 { 562 regulator-name = "vdd_ddr_1v1"; 563 regulator-min-microvolt = <1100000>; 564 regulator-max-microvolt = <1100000>; 565 regulator-boot-on; 566 regulator-always-on; 567 bootph-all; 568 }; 569 570 bucka3: buck3 { 571 regulator-name = "vdd_ram_0v85"; 572 regulator-min-microvolt = <850000>; 573 regulator-max-microvolt = <850000>; 574 regulator-boot-on; 575 regulator-always-on; 576 bootph-all; 577 }; 578 579 bucka4: buck4 { 580 regulator-name = "vdd_io_1v8"; 581 regulator-min-microvolt = <1800000>; 582 regulator-max-microvolt = <1800000>; 583 regulator-boot-on; 584 regulator-always-on; 585 bootph-all; 586 }; 587 588 bucka5: buck5 { 589 regulator-name = "vdd_mcu_0v85"; 590 regulator-min-microvolt = <850000>; 591 regulator-max-microvolt = <850000>; 592 regulator-boot-on; 593 regulator-always-on; 594 bootph-all; 595 }; 596 597 ldoa1: ldo1 { 598 regulator-name = "vdd_mcuio_1v8"; 599 regulator-min-microvolt = <1800000>; 600 regulator-max-microvolt = <1800000>; 601 regulator-boot-on; 602 regulator-always-on; 603 bootph-all; 604 }; 605 606 ldoa2: ldo2 { 607 regulator-name = "vdd_mcuio_3v3"; 608 regulator-min-microvolt = <3300000>; 609 regulator-max-microvolt = <3300000>; 610 regulator-boot-on; 611 regulator-always-on; 612 bootph-all; 613 }; 614 615 ldoa3: ldo3 { 616 regulator-name = "vds_dll_0v8"; 617 regulator-min-microvolt = <800000>; 618 regulator-max-microvolt = <800000>; 619 regulator-boot-on; 620 regulator-always-on; 621 bootph-all; 622 }; 623 624 ldoa4: ldo4 { 625 regulator-name = "vda_mcu_1v8"; 626 regulator-min-microvolt = <1800000>; 627 regulator-max-microvolt = <1800000>; 628 regulator-boot-on; 629 regulator-always-on; 630 bootph-all; 631 }; 632 }; 633 }; 634 635 tps62873a: regulator@40 { 636 compatible = "ti,tps62873"; 637 reg = <0x40>; 638 bootph-pre-ram; 639 regulator-name = "VDD_CPU_AVS"; 640 regulator-min-microvolt = <750000>; 641 regulator-max-microvolt = <1330000>; 642 regulator-boot-on; 643 regulator-always-on; 644 }; 645 646 tps62873b: regulator@43 { 647 compatible = "ti,tps62873"; 648 reg = <0x43>; 649 regulator-name = "VDD_CORE_0V8"; 650 regulator-min-microvolt = <760000>; 651 regulator-max-microvolt = <840000>; 652 regulator-boot-on; 653 regulator-always-on; 654 }; 655}; 656 657&mcu_uart0 { 658 bootph-all; 659 status = "okay"; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&mcu_uart0_pins_default>; 662}; 663 664&main_uart8 { 665 bootph-all; 666 status = "okay"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&main_uart8_pins_default>; 669}; 670 671&ufs_wrapper { 672 status = "okay"; 673}; 674 675&fss { 676 status = "okay"; 677}; 678 679&ospi0 { 680 status = "okay"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 683 684 flash@0 { 685 compatible = "jedec,spi-nor"; 686 reg = <0x0>; 687 spi-tx-bus-width = <8>; 688 spi-rx-bus-width = <8>; 689 spi-max-frequency = <25000000>; 690 cdns,tshsl-ns = <60>; 691 cdns,tsd2d-ns = <60>; 692 cdns,tchsh-ns = <60>; 693 cdns,tslch-ns = <60>; 694 cdns,read-delay = <4>; 695 696 partitions { 697 compatible = "fixed-partitions"; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 701 partition@0 { 702 label = "ospi.tiboot3"; 703 reg = <0x0 0x80000>; 704 }; 705 706 partition@80000 { 707 label = "ospi.tispl"; 708 reg = <0x80000 0x200000>; 709 }; 710 711 partition@280000 { 712 label = "ospi.u-boot"; 713 reg = <0x280000 0x400000>; 714 }; 715 716 partition@680000 { 717 label = "ospi.env"; 718 reg = <0x680000 0x40000>; 719 }; 720 721 partition@6c0000 { 722 label = "ospi.env.backup"; 723 reg = <0x6c0000 0x40000>; 724 }; 725 726 partition@800000 { 727 label = "ospi.rootfs"; 728 reg = <0x800000 0x37c0000>; 729 }; 730 731 partition@3fc0000 { 732 bootph-all; 733 label = "ospi.phypattern"; 734 reg = <0x3fc0000 0x40000>; 735 }; 736 }; 737 }; 738}; 739 740&ospi1 { 741 status = "okay"; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 744 745 flash@0 { 746 compatible = "jedec,spi-nor"; 747 reg = <0x0>; 748 spi-tx-bus-width = <1>; 749 spi-rx-bus-width = <4>; 750 spi-max-frequency = <40000000>; 751 cdns,tshsl-ns = <60>; 752 cdns,tsd2d-ns = <60>; 753 cdns,tchsh-ns = <60>; 754 cdns,tslch-ns = <60>; 755 cdns,read-delay = <2>; 756 757 partitions { 758 compatible = "fixed-partitions"; 759 #address-cells = <1>; 760 #size-cells = <1>; 761 762 partition@0 { 763 label = "qspi.tiboot3"; 764 reg = <0x0 0x80000>; 765 }; 766 767 partition@80000 { 768 label = "qspi.tispl"; 769 reg = <0x80000 0x200000>; 770 }; 771 772 partition@280000 { 773 label = "qspi.u-boot"; 774 reg = <0x280000 0x400000>; 775 }; 776 777 partition@680000 { 778 label = "qspi.env"; 779 reg = <0x680000 0x40000>; 780 }; 781 782 partition@6c0000 { 783 label = "qspi.env.backup"; 784 reg = <0x6c0000 0x40000>; 785 }; 786 787 partition@800000 { 788 label = "qspi.rootfs"; 789 reg = <0x800000 0x37c0000>; 790 }; 791 792 partition@3fc0000 { 793 bootph-all; 794 label = "qspi.phypattern"; 795 reg = <0x3fc0000 0x40000>; 796 }; 797 }; 798 799 }; 800}; 801 802&main_i2c0 { 803 status = "okay"; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&main_i2c0_pins_default>; 806 807 clock-frequency = <400000>; 808 809 exp1: gpio@20 { 810 compatible = "ti,tca6416"; 811 reg = <0x20>; 812 gpio-controller; 813 #gpio-cells = <2>; 814 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 815 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 816 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 817 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 818 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 819 820 p12-hog { 821 /* P12 - AUDIO_MUX_SEL */ 822 gpio-hog; 823 gpios = <12 GPIO_ACTIVE_HIGH>; 824 output-low; 825 line-name = "AUDIO_MUX_SEL"; 826 }; 827 }; 828 829 exp2: gpio@22 { 830 compatible = "ti,tca6424"; 831 reg = <0x22>; 832 gpio-controller; 833 #gpio-cells = <2>; 834 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 835 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 836 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 837 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 838 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 839 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 840 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 841 "USER_INPUT1", "USER_LED1", "USER_LED2"; 842 843 p13-hog { 844 /* P13 - CANUART_MUX_SEL0 */ 845 gpio-hog; 846 gpios = <13 GPIO_ACTIVE_HIGH>; 847 output-high; 848 line-name = "CANUART_MUX_SEL0"; 849 }; 850 851 p15-hog { 852 /* P15 - CANUART_MUX1_SEL1 */ 853 gpio-hog; 854 gpios = <15 GPIO_ACTIVE_HIGH>; 855 output-high; 856 line-name = "CANUART_MUX1_SEL1"; 857 }; 858 }; 859}; 860 861&main_i2c5 { 862 pinctrl-names = "default"; 863 pinctrl-0 = <&main_i2c5_pins_default>; 864 clock-frequency = <400000>; 865 status = "okay"; 866 867 exp5: gpio@20 { 868 compatible = "ti,tca6408"; 869 reg = <0x20>; 870 gpio-controller; 871 #gpio-cells = <2>; 872 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 873 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", 874 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 875 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 876 }; 877}; 878 879&main_sdhci0 { 880 bootph-all; 881 /* eMMC */ 882 status = "okay"; 883 non-removable; 884 ti,driver-strength-ohm = <50>; 885 disable-wp; 886}; 887 888&main_sdhci1 { 889 bootph-all; 890 /* SD card */ 891 status = "okay"; 892 pinctrl-0 = <&main_mmc1_pins_default>; 893 pinctrl-names = "default"; 894 disable-wp; 895 vmmc-supply = <&vdd_mmc1>; 896 vqmmc-supply = <&vdd_sd_dv>; 897}; 898 899&main_gpio0 { 900 status = "okay"; 901}; 902 903&mcu_cpsw { 904 status = "okay"; 905 pinctrl-names = "default"; 906 pinctrl-0 = <&mcu_cpsw_pins_default>; 907}; 908 909&davinci_mdio { 910 pinctrl-names = "default"; 911 pinctrl-0 = <&mcu_mdio_pins_default>; 912 913 mcu_phy0: ethernet-phy@0 { 914 reg = <0>; 915 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 916 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 917 ti,min-output-impedance; 918 }; 919}; 920 921&mcu_cpsw_port1 { 922 status = "okay"; 923 phy-mode = "rgmii-id"; 924 phy-handle = <&mcu_phy0>; 925}; 926 927&main_cpsw1 { 928 pinctrl-names = "default"; 929 pinctrl-0 = <&main_cpsw2g_default_pins>; 930 status = "okay"; 931}; 932 933&main_cpsw1_mdio { 934 pinctrl-names = "default"; 935 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; 936 status = "okay"; 937 938 main_cpsw1_phy0: ethernet-phy@0 { 939 reg = <0>; 940 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 941 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 942 ti,min-output-impedance; 943 }; 944}; 945 946&main_cpsw1_port1 { 947 phy-mode = "rgmii-id"; 948 phy-handle = <&main_cpsw1_phy0>; 949 status = "okay"; 950}; 951 952&tscadc0 { 953 pinctrl-0 = <&mcu_adc0_pins_default>; 954 pinctrl-names = "default"; 955 status = "okay"; 956 adc { 957 ti,adc-channels = <0 1 2 3 4 5 6 7>; 958 }; 959}; 960 961&tscadc1 { 962 pinctrl-0 = <&mcu_adc1_pins_default>; 963 pinctrl-names = "default"; 964 status = "okay"; 965 adc { 966 ti,adc-channels = <0 1 2 3 4 5 6 7>; 967 }; 968}; 969 970&serdes_refclk { 971 status = "okay"; 972 clock-frequency = <100000000>; 973 bootph-all; 974}; 975 976&dss { 977 status = "okay"; 978 assigned-clocks = <&k3_clks 218 2>, 979 <&k3_clks 218 5>, 980 <&k3_clks 218 14>, 981 <&k3_clks 218 18>; 982 assigned-clock-parents = <&k3_clks 218 3>, 983 <&k3_clks 218 7>, 984 <&k3_clks 218 16>, 985 <&k3_clks 218 22>; 986}; 987 988&pcie1_ctrl { 989 bootph-all; 990}; 991 992&serdes_ln_ctrl { 993 bootph-all; 994}; 995 996&serdes0 { 997 status = "okay"; 998 999 serdes0_pcie1_link: phy@0 { 1000 reg = <0>; 1001 cdns,num-lanes = <2>; 1002 #phy-cells = <0>; 1003 cdns,phy-type = <PHY_TYPE_PCIE>; 1004 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 1005 bootph-all; 1006 }; 1007 1008 serdes0_usb_link: phy@3 { 1009 reg = <3>; 1010 cdns,num-lanes = <1>; 1011 #phy-cells = <0>; 1012 cdns,phy-type = <PHY_TYPE_USB3>; 1013 resets = <&serdes_wiz0 4>; 1014 }; 1015}; 1016 1017&serdes_wiz0 { 1018 status = "okay"; 1019}; 1020 1021&usb_serdes_mux { 1022 idle-states = <0>; /* USB0 to SERDES lane 3 */ 1023}; 1024 1025&usbss0 { 1026 status = "okay"; 1027 pinctrl-0 = <&main_usbss0_pins_default>; 1028 pinctrl-names = "default"; 1029 ti,vbus-divider; 1030}; 1031 1032&usb0 { 1033 dr_mode = "otg"; 1034 maximum-speed = "super-speed"; 1035 phys = <&serdes0_usb_link>; 1036 phy-names = "cdns3,usb3-phy"; 1037}; 1038 1039&serdes_wiz4 { 1040 status = "okay"; 1041}; 1042 1043&serdes4 { 1044 status = "okay"; 1045 serdes4_dp_link: phy@0 { 1046 reg = <0>; 1047 cdns,num-lanes = <4>; 1048 #phy-cells = <0>; 1049 cdns,phy-type = <PHY_TYPE_DP>; 1050 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1051 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1052 }; 1053}; 1054 1055&mhdp { 1056 status = "okay"; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&dp0_pins_default>; 1059 phys = <&serdes4_dp_link>; 1060 phy-names = "dpphy"; 1061}; 1062 1063&dss_ports { 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 /* DP */ 1068 port@0 { 1069 reg = <0>; 1070 1071 dpi0_out: endpoint { 1072 remote-endpoint = <&dp0_in>; 1073 }; 1074 }; 1075 1076 /* DSI */ 1077 port@2 { 1078 reg = <2>; 1079 1080 dpi2_out: endpoint { 1081 remote-endpoint = <&dsi0_in>; 1082 }; 1083 }; 1084}; 1085 1086&main_i2c4 { 1087 status = "okay"; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&main_i2c4_pins_default>; 1090 clock-frequency = <400000>; 1091 1092 exp4: gpio@20 { 1093 compatible = "ti,tca6408"; 1094 reg = <0x20>; 1095 gpio-controller; 1096 #gpio-cells = <2>; 1097 }; 1098 1099 bridge_dsi_edp: bridge-dsi-edp@2c { 1100 compatible = "ti,sn65dsi86"; 1101 reg = <0x2c>; 1102 clock-names = "refclk"; 1103 clocks = <&edp1_refclk>; 1104 enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>; 1105 vpll-supply = <&vsys_io_1v8>; 1106 vccio-supply = <&vsys_io_1v8>; 1107 vcca-supply = <&vsys_io_1v2>; 1108 vcc-supply = <&vsys_io_1v2>; 1109 1110 dsi_edp_bridge_ports: ports { 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 1114 port@0 { 1115 reg = <0>; 1116 1117 dp1_in: endpoint { 1118 remote-endpoint = <&dsi0_out>; 1119 }; 1120 }; 1121 1122 port@1 { 1123 reg = <1>; 1124 1125 dp1_out: endpoint { 1126 remote-endpoint = <&dp1_connector_in>; 1127 }; 1128 }; 1129 }; 1130 }; 1131}; 1132 1133&dsi0_ports { 1134 port@0 { 1135 reg = <0>; 1136 1137 dsi0_out: endpoint { 1138 remote-endpoint = <&dp1_in>; 1139 }; 1140 }; 1141 1142 port@1 { 1143 reg = <1>; 1144 1145 dsi0_in: endpoint { 1146 remote-endpoint = <&dpi2_out>; 1147 }; 1148 }; 1149}; 1150 1151&dphy_tx0 { 1152 status = "okay"; 1153}; 1154 1155&dsi0 { 1156 status = "okay"; 1157}; 1158 1159&dp0_ports { 1160 port@0 { 1161 reg = <0>; 1162 1163 dp0_in: endpoint { 1164 remote-endpoint = <&dpi0_out>; 1165 }; 1166 }; 1167 1168 port@4 { 1169 reg = <4>; 1170 1171 dp0_out: endpoint { 1172 remote-endpoint = <&dp0_connector_in>; 1173 }; 1174 }; 1175}; 1176 1177&mcu_mcan0 { 1178 status = "okay"; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&mcu_mcan0_pins_default>; 1181 phys = <&transceiver0>; 1182}; 1183 1184&mcu_mcan1 { 1185 status = "okay"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&mcu_mcan1_pins_default>; 1188 phys = <&transceiver1>; 1189}; 1190 1191&main_mcan16 { 1192 status = "okay"; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&main_mcan16_pins_default>; 1195 phys = <&transceiver2>; 1196}; 1197 1198&main_mcan4 { 1199 status = "okay"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&main_mcan4_pins_default>; 1202 phys = <&transceiver3>; 1203}; 1204 1205&pcie1_rc { 1206 status = "okay"; 1207 clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1208 clock-names = "fck", "pcie_refclk"; 1209 num-lanes = <2>; 1210 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 1211 phys = <&serdes0_pcie1_link>; 1212 phy-names = "pcie-phy"; 1213 ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; 1214}; 1215 1216&serdes1 { 1217 status = "okay"; 1218 1219 serdes1_pcie0_link: phy@0 { 1220 reg = <0>; 1221 cdns,num-lanes = <4>; 1222 #phy-cells = <0>; 1223 cdns,phy-type = <PHY_TYPE_PCIE>; 1224 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, 1225 <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1226 }; 1227}; 1228 1229&serdes_wiz1 { 1230 status = "okay"; 1231}; 1232 1233&pcie0_rc { 1234 status = "okay"; 1235 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1236 phys = <&serdes1_pcie0_link>; 1237 phy-names = "pcie-phy"; 1238}; 1239 1240&k3_clks { 1241 /* Confiure AUDIO_EXT_REFCLK1 pin as output */ 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 1244}; 1245 1246&main_i2c3 { 1247 status = "okay"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&main_i2c3_pins_default>; 1250 clock-frequency = <400000>; 1251 1252 exp3: gpio@20 { 1253 compatible = "ti,tca6408"; 1254 reg = <0x20>; 1255 gpio-controller; 1256 #gpio-cells = <2>; 1257 }; 1258 1259 pcm3168a_1: audio-codec@44 { 1260 compatible = "ti,pcm3168a"; 1261 reg = <0x44>; 1262 #sound-dai-cells = <1>; 1263 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 1264 clocks = <&audio_refclk1>; 1265 clock-names = "scki"; 1266 VDD1-supply = <&vsys_3v3>; 1267 VDD2-supply = <&vsys_3v3>; 1268 VCCAD1-supply = <&vsys_5v0>; 1269 VCCAD2-supply = <&vsys_5v0>; 1270 VCCDA1-supply = <&vsys_5v0>; 1271 VCCDA2-supply = <&vsys_5v0>; 1272 }; 1273}; 1274 1275&mcasp0 { 1276 status = "okay"; 1277 #sound-dai-cells = <0>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&main_mcasp0_pins_default>; 1280 op-mode = <0>; /* MCASP_IIS_MODE */ 1281 tdm-slots = <2>; 1282 auxclk-fs-ratio = <256>; 1283 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1284 0 0 0 1 1285 2 0 0 0 1286 0 0 0 0 1287 0 0 0 0 1288 >; 1289}; 1290 1291#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi"
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