k3-j784s4-evm-usxgmii-exp1-exp2.dtso

 1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 2/**
 3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
 4 * and ENET-2 Expansion slots of J784S4 EVM.
 5 *
 6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 7 */
 8
 9/dts-v1/;
10/plugin/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/phy/phy-cadence.h>
14#include <dt-bindings/phy/phy.h>
15
16#include "k3-serdes.h"
17
18&{/} {
19	aliases {
20		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
21		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
22		ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
23	};
24};
25
26&main_cpsw0 {
27	status = "okay";
28};
29
30&main_cpsw0_port1 {
31	phy-mode = "usxgmii";
32	mac-address = [00 00 00 00 00 00];
33	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
34	phy-names = "mac", "serdes";
35	status = "okay";
36	fixed-link {
37		speed = <5000>;
38		full-duplex;
39	};
40};
41
42&main_cpsw0_port2 {
43	phy-mode = "usxgmii";
44	mac-address = [00 00 00 00 00 00];
45	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
46	phy-names = "mac", "serdes";
47	status = "okay";
48	fixed-link {
49		speed = <5000>;
50		full-duplex;
51	};
52};
53
54&serdes_wiz2 {
55	assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
56	status = "okay";
57};
58
59&serdes2 {
60	#address-cells = <1>;
61	#size-cells = <0>;
62	status = "okay";
63
64	serdes2_usxgmii_link: phy@2 {
65		reg = <2>;
66		cdns,num-lanes = <2>;
67		#phy-cells = <0>;
68		cdns,phy-type = <PHY_TYPE_USXGMII>;
69		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
70	};
71};
72
73&serdes_ln_ctrl {
74	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
75		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
76		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
77		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
78		      <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
79		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
80};