k3-j784s4-evm-quad-port-eth-exp1.dtso

  1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
  2/**
  3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
  4 * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
  5 * board.
  6 *
  7 * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
  8 *
  9 * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
 10 *
 11 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 12 */
 13
 14/dts-v1/;
 15/plugin/;
 16
 17#include <dt-bindings/gpio/gpio.h>
 18#include <dt-bindings/phy/phy-cadence.h>
 19#include <dt-bindings/phy/phy.h>
 20
 21#include "k3-pinctrl.h"
 22#include "k3-serdes.h"
 23
 24&{/} {
 25	aliases {
 26		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
 27		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
 28		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
 29		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
 30		ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
 31	};
 32};
 33
 34&main_cpsw0 {
 35	status = "okay";
 36};
 37
 38&main_cpsw0_port5 {
 39	phy-handle = <&cpsw9g_phy1>;
 40	phy-mode = "qsgmii";
 41	mac-address = [00 00 00 00 00 00];
 42	phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
 43	phy-names = "mac", "serdes";
 44	status = "okay";
 45};
 46
 47&main_cpsw0_port6 {
 48	phy-handle = <&cpsw9g_phy2>;
 49	phy-mode = "qsgmii";
 50	mac-address = [00 00 00 00 00 00];
 51	phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
 52	phy-names = "mac", "serdes";
 53	status = "okay";
 54};
 55
 56&main_cpsw0_port7 {
 57	phy-handle = <&cpsw9g_phy0>;
 58	phy-mode = "qsgmii";
 59	mac-address = [00 00 00 00 00 00];
 60	phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
 61	phy-names = "mac", "serdes";
 62	status = "okay";
 63};
 64
 65&main_cpsw0_port8 {
 66	phy-handle = <&cpsw9g_phy3>;
 67	phy-mode = "qsgmii";
 68	mac-address = [00 00 00 00 00 00];
 69	phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
 70	phy-names = "mac", "serdes";
 71	status = "okay";
 72};
 73
 74&main_cpsw0_mdio {
 75	pinctrl-names = "default";
 76	pinctrl-0 = <&mdio0_default_pins>;
 77	bus_freq = <1000000>;
 78	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
 79	reset-post-delay-us = <120000>;
 80	#address-cells = <1>;
 81	#size-cells = <0>;
 82	status = "okay";
 83
 84	cpsw9g_phy0: ethernet-phy@16 {
 85		reg = <16>;
 86	};
 87	cpsw9g_phy1: ethernet-phy@17 {
 88		reg = <17>;
 89	};
 90	cpsw9g_phy2: ethernet-phy@18 {
 91		reg = <18>;
 92	};
 93	cpsw9g_phy3: ethernet-phy@19 {
 94		reg = <19>;
 95	};
 96};
 97
 98&exp2 {
 99	/* Power-up ENET1 EXPANDER PHY. */
100	qsgmii-line-hog {
101		gpio-hog;
102		gpios = <16 GPIO_ACTIVE_HIGH>;
103		output-low;
104	};
105};
106
107&main_pmx0 {
108	mdio0_default_pins: mdio0-default-pins {
109		pinctrl-single,pins = <
110			J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
111			J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
112		>;
113	};
114};
115
116&serdes_ln_ctrl {
117	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
118		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
119		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
120		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
121		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
122		      <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
123};
124
125&serdes_wiz2 {
126	status = "okay";
127};
128
129&serdes2 {
130	#address-cells = <1>;
131	#size-cells = <0>;
132	status = "okay";
133	serdes2_qsgmii_link: phy@0 {
134		reg = <2>;
135		cdns,num-lanes = <1>;
136		#phy-cells = <0>;
137		cdns,phy-type = <PHY_TYPE_QSGMII>;
138		resets = <&serdes_wiz2 3>;
139	};
140};