k3-j721s2-ti-ipc-firmware.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/**
  3 * Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs
  4 *
  5 * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8&reserved_memory {
  9	mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
 10		compatible = "shared-dma-pool";
 11		reg = <0x00 0xa1000000 0x00 0x100000>;
 12		no-map;
 13	};
 14
 15	mcu_r5fss0_core1_memory_region: memory@a1100000 {
 16		compatible = "shared-dma-pool";
 17		reg = <0x00 0xa1100000 0x00 0xf00000>;
 18		no-map;
 19	};
 20
 21	main_r5fss0_core0_dma_memory_region: memory@a2000000 {
 22		compatible = "shared-dma-pool";
 23		reg = <0x00 0xa2000000 0x00 0x100000>;
 24		no-map;
 25	};
 26
 27	main_r5fss0_core0_memory_region: memory@a2100000 {
 28		compatible = "shared-dma-pool";
 29		reg = <0x00 0xa2100000 0x00 0xf00000>;
 30		no-map;
 31	};
 32
 33	main_r5fss0_core1_dma_memory_region: memory@a3000000 {
 34		compatible = "shared-dma-pool";
 35		reg = <0x00 0xa3000000 0x00 0x100000>;
 36		no-map;
 37	};
 38
 39	main_r5fss0_core1_memory_region: memory@a3100000 {
 40		compatible = "shared-dma-pool";
 41		reg = <0x00 0xa3100000 0x00 0xf00000>;
 42		no-map;
 43	};
 44
 45	main_r5fss1_core0_dma_memory_region: memory@a4000000 {
 46		compatible = "shared-dma-pool";
 47		reg = <0x00 0xa4000000 0x00 0x100000>;
 48		no-map;
 49	};
 50
 51	main_r5fss1_core0_memory_region: memory@a4100000 {
 52		compatible = "shared-dma-pool";
 53		reg = <0x00 0xa4100000 0x00 0xf00000>;
 54		no-map;
 55	};
 56
 57	main_r5fss1_core1_dma_memory_region: memory@a5000000 {
 58		compatible = "shared-dma-pool";
 59		reg = <0x00 0xa5000000 0x00 0x100000>;
 60		no-map;
 61	};
 62
 63	main_r5fss1_core1_memory_region: memory@a5100000 {
 64		compatible = "shared-dma-pool";
 65		reg = <0x00 0xa5100000 0x00 0xf00000>;
 66		no-map;
 67	};
 68
 69	c71_0_dma_memory_region: memory@a6000000 {
 70		compatible = "shared-dma-pool";
 71		reg = <0x00 0xa6000000 0x00 0x100000>;
 72		no-map;
 73	};
 74
 75	c71_0_memory_region: memory@a6100000 {
 76		compatible = "shared-dma-pool";
 77		reg = <0x00 0xa6100000 0x00 0xf00000>;
 78		no-map;
 79	};
 80
 81	c71_1_dma_memory_region: memory@a7000000 {
 82		compatible = "shared-dma-pool";
 83		reg = <0x00 0xa7000000 0x00 0x100000>;
 84		no-map;
 85	};
 86
 87	c71_1_memory_region: memory@a7100000 {
 88		compatible = "shared-dma-pool";
 89		reg = <0x00 0xa7100000 0x00 0xf00000>;
 90		no-map;
 91	};
 92
 93	rtos_ipc_memory_region: memory@a8000000 {
 94		reg = <0x00 0xa8000000 0x00 0x01c00000>;
 95		alignment = <0x1000>;
 96		no-map;
 97	};
 98};
 99
100&mailbox0_cluster0 {
101	status = "okay";
102	interrupts = <436>;
103
104	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
105		ti,mbox-rx = <0 0 0>;
106		ti,mbox-tx = <1 0 0>;
107	};
108
109	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
110		ti,mbox-rx = <2 0 0>;
111		ti,mbox-tx = <3 0 0>;
112	};
113};
114
115&mailbox0_cluster1 {
116	status = "okay";
117	interrupts = <432>;
118
119	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
120		ti,mbox-rx = <0 0 0>;
121		ti,mbox-tx = <1 0 0>;
122	};
123
124	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
125		ti,mbox-rx = <2 0 0>;
126		ti,mbox-tx = <3 0 0>;
127	};
128};
129
130&mailbox0_cluster2 {
131	status = "okay";
132	interrupts = <428>;
133
134	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
135		ti,mbox-rx = <0 0 0>;
136		ti,mbox-tx = <1 0 0>;
137	};
138
139	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
140		ti,mbox-rx = <2 0 0>;
141		ti,mbox-tx = <3 0 0>;
142	};
143};
144
145&mailbox0_cluster4 {
146	status = "okay";
147	interrupts = <420>;
148
149	mbox_c71_0: mbox-c71-0 {
150		ti,mbox-rx = <0 0 0>;
151		ti,mbox-tx = <1 0 0>;
152	};
153
154	mbox_c71_1: mbox-c71-1 {
155		ti,mbox-rx = <2 0 0>;
156		ti,mbox-tx = <3 0 0>;
157	};
158};
159
160/* Timers are used by Remoteproc firmware */
161&main_timer0 {
162	status = "reserved";
163};
164
165&main_timer1 {
166	status = "reserved";
167};
168
169&main_timer2 {
170	status = "reserved";
171};
172
173&main_timer3 {
174	status = "reserved";
175};
176
177&main_timer4 {
178	status = "reserved";
179};
180
181&main_timer5 {
182	status = "reserved";
183};
184
185&mcu_r5fss0 {
186	status = "okay";
187};
188
189&mcu_r5fss0_core0 {
190	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
191	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
192			<&mcu_r5fss0_core0_memory_region>;
193	status = "okay";
194};
195
196&mcu_r5fss0_core1 {
197	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
198	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
199			<&mcu_r5fss0_core1_memory_region>;
200	status = "okay";
201};
202
203&main_r5fss0 {
204	ti,cluster-mode = <0>;
205	status = "okay";
206};
207
208&main_r5fss0_core0 {
209	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
210	memory-region = <&main_r5fss0_core0_dma_memory_region>,
211			<&main_r5fss0_core0_memory_region>;
212	status = "okay";
213};
214
215&main_r5fss0_core1 {
216	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
217	memory-region = <&main_r5fss0_core1_dma_memory_region>,
218			<&main_r5fss0_core1_memory_region>;
219	status = "okay";
220};
221
222&main_r5fss1 {
223	ti,cluster-mode = <0>;
224	status = "okay";
225};
226
227&main_r5fss1_core0 {
228	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
229	memory-region = <&main_r5fss1_core0_dma_memory_region>,
230			<&main_r5fss1_core0_memory_region>;
231	status = "okay";
232};
233
234&main_r5fss1_core1 {
235	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
236	memory-region = <&main_r5fss1_core1_dma_memory_region>,
237			<&main_r5fss1_core1_memory_region>;
238	status = "okay";
239};
240
241&c71_0 {
242	status = "okay";
243	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
244	memory-region = <&c71_0_dma_memory_region>,
245			<&c71_0_memory_region>;
246};
247
248&c71_1 {
249	status = "okay";
250	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
251	memory-region = <&c71_1_dma_memory_region>,
252			<&c71_1_memory_region>;
253};