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k3-j721s2-mcu-wakeup.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 bootph-all; 25 }; 26 27 k3_clks: clock-controller { 28 compatible = "ti,k2g-sci-clk"; 29 #clock-cells = <2>; 30 bootph-all; 31 }; 32 33 k3_reset: reset-controller { 34 compatible = "ti,sci-reset"; 35 #reset-cells = <2>; 36 bootph-all; 37 }; 38 }; 39 40 wkup_conf: bus@43000000 { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges = <0x0 0x00 0x43000000 0x20000>; 45 46 chipid: chipid@14 { 47 compatible = "ti,am654-chipid"; 48 reg = <0x14 0x4>; 49 bootph-all; 50 }; 51 }; 52 53 secure_proxy_sa3: mailbox@43600000 { 54 compatible = "ti,am654-secure-proxy"; 55 #mbox-cells = <1>; 56 reg-names = "target_data", "rt", "scfg"; 57 reg = <0x00 0x43600000 0x00 0x10000>, 58 <0x00 0x44880000 0x00 0x20000>, 59 <0x00 0x44860000 0x00 0x20000>; 60 bootph-pre-ram; 61 62 /* 63 * Marked Disabled: 64 * Node is incomplete as it is meant for bootloaders and 65 * firmware on non-MPU processors 66 */ 67 status = "disabled"; 68 }; 69 70 mcu_ram: sram@41c00000 { 71 compatible = "mmio-sram"; 72 reg = <0x00 0x41c00000 0x00 0x100000>; 73 ranges = <0x00 0x00 0x41c00000 0x100000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 }; 77 78 wkup_pmx0: pinctrl@4301c000 { 79 compatible = "pinctrl-single"; 80 /* Proxy 0 addressing */ 81 reg = <0x00 0x4301c000 0x00 0x034>; 82 #pinctrl-cells = <1>; 83 pinctrl-single,register-width = <32>; 84 pinctrl-single,function-mask = <0xffffffff>; 85 }; 86 87 wkup_pmx1: pinctrl@4301c038 { 88 compatible = "pinctrl-single"; 89 /* Proxy 0 addressing */ 90 reg = <0x00 0x4301c038 0x00 0x02C>; 91 #pinctrl-cells = <1>; 92 pinctrl-single,register-width = <32>; 93 pinctrl-single,function-mask = <0xffffffff>; 94 }; 95 96 wkup_pmx2: pinctrl@4301c068 { 97 compatible = "pinctrl-single"; 98 /* Proxy 0 addressing */ 99 reg = <0x00 0x4301c068 0x00 0x120>; 100 #pinctrl-cells = <1>; 101 pinctrl-single,register-width = <32>; 102 pinctrl-single,function-mask = <0xffffffff>; 103 }; 104 105 wkup_pmx3: pinctrl@4301c190 { 106 compatible = "pinctrl-single"; 107 /* Proxy 0 addressing */ 108 reg = <0x00 0x4301c190 0x00 0x004>; 109 #pinctrl-cells = <1>; 110 pinctrl-single,register-width = <32>; 111 pinctrl-single,function-mask = <0xffffffff>; 112 }; 113 114 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 115 mcu_timerio_input: pinctrl@40f04200 { 116 compatible = "pinctrl-single"; 117 reg = <0x00 0x40f04200 0x00 0x28>; 118 #pinctrl-cells = <1>; 119 pinctrl-single,register-width = <32>; 120 pinctrl-single,function-mask = <0x0000000f>; 121 /* Non-MPU Firmware usage */ 122 status = "reserved"; 123 }; 124 125 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 126 mcu_timerio_output: pinctrl@40f04280 { 127 compatible = "pinctrl-single"; 128 reg = <0x00 0x40f04280 0x00 0x28>; 129 #pinctrl-cells = <1>; 130 pinctrl-single,register-width = <32>; 131 pinctrl-single,function-mask = <0x0000000f>; 132 /* Non-MPU Firmware usage */ 133 status = "reserved"; 134 }; 135 136 wkup_gpio_intr: interrupt-controller@42200000 { 137 compatible = "ti,sci-intr"; 138 reg = <0x00 0x42200000 0x00 0x400>; 139 ti,intr-trigger-type = <1>; 140 interrupt-controller; 141 interrupt-parent = <&gic500>; 142 #interrupt-cells = <1>; 143 ti,sci = <&sms>; 144 ti,sci-dev-id = <125>; 145 ti,interrupt-ranges = <16 960 16>; 146 }; 147 148 mcu_conf: bus@40f00000 { 149 compatible = "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0x0 0x40f00000 0x20000>; 153 154 cpsw_mac_syscon: ethernet-mac-syscon@200 { 155 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 156 reg = <0x200 0x8>; 157 }; 158 159 phy_gmii_sel: phy@4040 { 160 compatible = "ti,am654-phy-gmii-sel"; 161 reg = <0x4040 0x4>; 162 #phy-cells = <1>; 163 }; 164 165 }; 166 167 mcu_timer0: timer@40400000 { 168 compatible = "ti,am654-timer"; 169 reg = <0x00 0x40400000 0x00 0x400>; 170 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&k3_clks 35 1>; 172 clock-names = "fck"; 173 assigned-clocks = <&k3_clks 35 1>; 174 assigned-clock-parents = <&k3_clks 35 2>; 175 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 176 bootph-pre-ram; 177 ti,timer-pwm; 178 /* Non-MPU Firmware usage */ 179 status = "reserved"; 180 }; 181 182 mcu_timer1: timer@40410000 { 183 compatible = "ti,am654-timer"; 184 reg = <0x00 0x40410000 0x00 0x400>; 185 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&k3_clks 83 1>; 187 clock-names = "fck"; 188 assigned-clocks = <&k3_clks 83 1>; 189 assigned-clock-parents = <&k3_clks 83 2>; 190 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 191 ti,timer-pwm; 192 /* Non-MPU Firmware usage */ 193 status = "reserved"; 194 }; 195 196 mcu_timer2: timer@40420000 { 197 compatible = "ti,am654-timer"; 198 reg = <0x00 0x40420000 0x00 0x400>; 199 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&k3_clks 84 1>; 201 clock-names = "fck"; 202 assigned-clocks = <&k3_clks 84 1>; 203 assigned-clock-parents = <&k3_clks 84 2>; 204 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 205 ti,timer-pwm; 206 /* Non-MPU Firmware usage */ 207 status = "reserved"; 208 }; 209 210 mcu_timer3: timer@40430000 { 211 compatible = "ti,am654-timer"; 212 reg = <0x00 0x40430000 0x00 0x400>; 213 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&k3_clks 85 1>; 215 clock-names = "fck"; 216 assigned-clocks = <&k3_clks 85 1>; 217 assigned-clock-parents = <&k3_clks 85 2>; 218 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 219 ti,timer-pwm; 220 /* Non-MPU Firmware usage */ 221 status = "reserved"; 222 }; 223 224 mcu_timer4: timer@40440000 { 225 compatible = "ti,am654-timer"; 226 reg = <0x00 0x40440000 0x00 0x400>; 227 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&k3_clks 86 1>; 229 clock-names = "fck"; 230 assigned-clocks = <&k3_clks 86 1>; 231 assigned-clock-parents = <&k3_clks 86 2>; 232 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 233 ti,timer-pwm; 234 /* Non-MPU Firmware usage */ 235 status = "reserved"; 236 }; 237 238 mcu_timer5: timer@40450000 { 239 compatible = "ti,am654-timer"; 240 reg = <0x00 0x40450000 0x00 0x400>; 241 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&k3_clks 87 1>; 243 clock-names = "fck"; 244 assigned-clocks = <&k3_clks 87 1>; 245 assigned-clock-parents = <&k3_clks 87 2>; 246 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 247 ti,timer-pwm; 248 /* Non-MPU Firmware usage */ 249 status = "reserved"; 250 }; 251 252 mcu_timer6: timer@40460000 { 253 compatible = "ti,am654-timer"; 254 reg = <0x00 0x40460000 0x00 0x400>; 255 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&k3_clks 88 1>; 257 clock-names = "fck"; 258 assigned-clocks = <&k3_clks 88 1>; 259 assigned-clock-parents = <&k3_clks 88 2>; 260 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 261 ti,timer-pwm; 262 /* Non-MPU Firmware usage */ 263 status = "reserved"; 264 }; 265 266 mcu_timer7: timer@40470000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x40470000 0x00 0x400>; 269 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 89 1>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 89 1>; 273 assigned-clock-parents = <&k3_clks 89 2>; 274 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 /* Non-MPU Firmware usage */ 277 status = "reserved"; 278 }; 279 280 mcu_timer8: timer@40480000 { 281 compatible = "ti,am654-timer"; 282 reg = <0x00 0x40480000 0x00 0x400>; 283 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&k3_clks 90 1>; 285 clock-names = "fck"; 286 assigned-clocks = <&k3_clks 90 1>; 287 assigned-clock-parents = <&k3_clks 90 2>; 288 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 289 ti,timer-pwm; 290 /* Non-MPU Firmware usage */ 291 status = "reserved"; 292 }; 293 294 mcu_timer9: timer@40490000 { 295 compatible = "ti,am654-timer"; 296 reg = <0x00 0x40490000 0x00 0x400>; 297 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&k3_clks 91 1>; 299 clock-names = "fck"; 300 assigned-clocks = <&k3_clks 91 1>; 301 assigned-clock-parents = <&k3_clks 91 2>; 302 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 303 ti,timer-pwm; 304 /* Non-MPU Firmware usage */ 305 status = "reserved"; 306 }; 307 308 wkup_uart0: serial@42300000 { 309 compatible = "ti,j721e-uart", "ti,am654-uart"; 310 reg = <0x00 0x42300000 0x00 0x200>; 311 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 359 3>; 313 clock-names = "fclk"; 314 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 315 status = "disabled"; 316 }; 317 318 mcu_uart0: serial@40a00000 { 319 compatible = "ti,j721e-uart", "ti,am654-uart"; 320 reg = <0x00 0x40a00000 0x00 0x200>; 321 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&k3_clks 149 3>; 323 clock-names = "fclk"; 324 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 325 status = "disabled"; 326 }; 327 328 wkup_gpio0: gpio@42110000 { 329 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 330 reg = <0x00 0x42110000 0x00 0x100>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-parent = <&wkup_gpio_intr>; 334 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 ti,ngpio = <89>; 338 ti,davinci-gpio-unbanked = <0>; 339 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 340 clocks = <&k3_clks 115 0>; 341 clock-names = "gpio"; 342 status = "disabled"; 343 }; 344 345 wkup_gpio1: gpio@42100000 { 346 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 347 reg = <0x00 0x42100000 0x00 0x100>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-parent = <&wkup_gpio_intr>; 351 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 ti,ngpio = <89>; 355 ti,davinci-gpio-unbanked = <0>; 356 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 357 clocks = <&k3_clks 116 0>; 358 clock-names = "gpio"; 359 status = "disabled"; 360 }; 361 362 wkup_i2c0: i2c@42120000 { 363 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 364 reg = <0x00 0x42120000 0x00 0x100>; 365 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&k3_clks 223 1>; 369 clock-names = "fck"; 370 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 371 bootph-all; 372 status = "disabled"; 373 }; 374 375 mcu_i2c0: i2c@40b00000 { 376 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 377 reg = <0x00 0x40b00000 0x00 0x100>; 378 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&k3_clks 221 1>; 382 clock-names = "fck"; 383 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 384 status = "disabled"; 385 }; 386 387 mcu_i2c1: i2c@40b10000 { 388 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 389 reg = <0x00 0x40b10000 0x00 0x100>; 390 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 clocks = <&k3_clks 222 1>; 394 clock-names = "fck"; 395 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 396 status = "disabled"; 397 }; 398 399 mcu_mcan0: can@40528000 { 400 compatible = "bosch,m_can"; 401 reg = <0x00 0x40528000 0x00 0x200>, 402 <0x00 0x40500000 0x00 0x8000>; 403 reg-names = "m_can", "message_ram"; 404 power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>; 405 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>; 406 clock-names = "hclk", "cclk"; 407 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "int0", "int1"; 410 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 411 status = "disabled"; 412 }; 413 414 mcu_mcan1: can@40568000 { 415 compatible = "bosch,m_can"; 416 reg = <0x00 0x40568000 0x00 0x200>, 417 <0x00 0x40540000 0x00 0x8000>; 418 reg-names = "m_can", "message_ram"; 419 power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>; 421 clock-names = "hclk", "cclk"; 422 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-names = "int0", "int1"; 425 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 426 status = "disabled"; 427 }; 428 429 mcu_spi0: spi@40300000 { 430 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 431 reg = <0x00 0x040300000 0x00 0x400>; 432 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 347 2>; 437 status = "disabled"; 438 }; 439 440 mcu_spi1: spi@40310000 { 441 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 442 reg = <0x00 0x040310000 0x00 0x400>; 443 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 447 clocks = <&k3_clks 348 2>; 448 status = "disabled"; 449 }; 450 451 mcu_spi2: spi@40320000 { 452 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 453 reg = <0x00 0x040320000 0x00 0x400>; 454 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 458 clocks = <&k3_clks 349 2>; 459 status = "disabled"; 460 }; 461 462 mcu_navss: bus@28380000 { 463 compatible = "simple-bus"; 464 #address-cells = <2>; 465 #size-cells = <2>; 466 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 467 dma-coherent; 468 dma-ranges; 469 470 ti,sci-dev-id = <267>; 471 472 mcu_ringacc: ringacc@2b800000 { 473 compatible = "ti,am654-navss-ringacc"; 474 reg = <0x0 0x2b800000 0x0 0x400000>, 475 <0x0 0x2b000000 0x0 0x400000>, 476 <0x0 0x28590000 0x0 0x100>, 477 <0x0 0x2a500000 0x0 0x40000>, 478 <0x0 0x28440000 0x0 0x40000>; 479 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 480 bootph-all; 481 ti,num-rings = <286>; 482 ti,sci-rm-range-gp-rings = <0x1>; 483 ti,sci = <&sms>; 484 ti,sci-dev-id = <272>; 485 msi-parent = <&main_udmass_inta>; 486 }; 487 488 mcu_udmap: dma-controller@285c0000 { 489 compatible = "ti,j721e-navss-mcu-udmap"; 490 reg = <0x0 0x285c0000 0x0 0x100>, 491 <0x0 0x2a800000 0x0 0x40000>, 492 <0x0 0x2aa00000 0x0 0x40000>, 493 <0x0 0x284a0000 0x0 0x4000>, 494 <0x0 0x284c0000 0x0 0x4000>, 495 <0x0 0x28400000 0x0 0x2000>; 496 reg-names = "gcfg", "rchanrt", "tchanrt", 497 "tchan", "rchan", "rflow"; 498 msi-parent = <&main_udmass_inta>; 499 #dma-cells = <1>; 500 bootph-all; 501 502 ti,sci = <&sms>; 503 ti,sci-dev-id = <273>; 504 ti,ringacc = <&mcu_ringacc>; 505 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 506 <0x0f>; /* TX_HCHAN */ 507 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 508 <0x0b>; /* RX_HCHAN */ 509 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 510 }; 511 }; 512 513 secure_proxy_mcu: mailbox@2a480000 { 514 compatible = "ti,am654-secure-proxy"; 515 #mbox-cells = <1>; 516 reg-names = "target_data", "rt", "scfg"; 517 reg = <0x00 0x2a480000 0x00 0x80000>, 518 <0x00 0x2a380000 0x00 0x80000>, 519 <0x00 0x2a400000 0x00 0x80000>; 520 bootph-pre-ram; 521 522 /* 523 * Marked Disabled: 524 * Node is incomplete as it is meant for bootloaders and 525 * firmware on non-MPU processors 526 */ 527 status = "disabled"; 528 }; 529 530 mcu_cpsw: ethernet@46000000 { 531 compatible = "ti,j721e-cpsw-nuss"; 532 #address-cells = <2>; 533 #size-cells = <2>; 534 reg = <0x0 0x46000000 0x0 0x200000>; 535 reg-names = "cpsw_nuss"; 536 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 537 dma-coherent; 538 clocks = <&k3_clks 29 28>; 539 clock-names = "fck"; 540 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 541 542 dmas = <&mcu_udmap 0xf000>, 543 <&mcu_udmap 0xf001>, 544 <&mcu_udmap 0xf002>, 545 <&mcu_udmap 0xf003>, 546 <&mcu_udmap 0xf004>, 547 <&mcu_udmap 0xf005>, 548 <&mcu_udmap 0xf006>, 549 <&mcu_udmap 0xf007>, 550 <&mcu_udmap 0x7000>; 551 dma-names = "tx0", "tx1", "tx2", "tx3", 552 "tx4", "tx5", "tx6", "tx7", 553 "rx"; 554 555 status = "disabled"; 556 557 ethernet-ports { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 561 cpsw_port1: port@1 { 562 reg = <1>; 563 ti,mac-only; 564 label = "port1"; 565 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 566 phys = <&phy_gmii_sel 1>; 567 }; 568 }; 569 570 davinci_mdio: mdio@f00 { 571 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 572 reg = <0x0 0xf00 0x0 0x100>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&k3_clks 29 28>; 576 clock-names = "fck"; 577 bus_freq = <1000000>; 578 }; 579 580 cpts@3d000 { 581 compatible = "ti,am65-cpts"; 582 reg = <0x0 0x3d000 0x0 0x400>; 583 clocks = <&k3_clks 29 3>; 584 clock-names = "cpts"; 585 assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ 586 assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ 587 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 588 interrupt-names = "cpts"; 589 ti,cpts-ext-ts-inputs = <4>; 590 ti,cpts-periodic-outputs = <2>; 591 }; 592 }; 593 594 tscadc0: tscadc@40200000 { 595 compatible = "ti,am3359-tscadc"; 596 reg = <0x00 0x40200000 0x00 0x1000>; 597 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 598 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 599 clocks = <&k3_clks 0 0>; 600 assigned-clocks = <&k3_clks 0 2>; 601 assigned-clock-rates = <60000000>; 602 clock-names = "fck"; 603 dmas = <&main_udmap 0x7400>, 604 <&main_udmap 0x7401>; 605 dma-names = "fifo0", "fifo1"; 606 status = "disabled"; 607 608 adc { 609 #io-channel-cells = <1>; 610 compatible = "ti,am3359-adc"; 611 }; 612 }; 613 614 tscadc1: tscadc@40210000 { 615 compatible = "ti,am3359-tscadc"; 616 reg = <0x00 0x40210000 0x00 0x1000>; 617 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 618 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 619 clocks = <&k3_clks 1 0>; 620 assigned-clocks = <&k3_clks 1 2>; 621 assigned-clock-rates = <60000000>; 622 clock-names = "fck"; 623 dmas = <&main_udmap 0x7402>, 624 <&main_udmap 0x7403>; 625 dma-names = "fifo0", "fifo1"; 626 status = "disabled"; 627 628 adc { 629 #io-channel-cells = <1>; 630 compatible = "ti,am3359-adc"; 631 }; 632 }; 633 634 fss: bus@47000000 { 635 compatible = "simple-bus"; 636 #address-cells = <2>; 637 #size-cells = <2>; 638 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 639 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 640 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; 641 642 ospi0: spi@47040000 { 643 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 644 reg = <0x00 0x47040000 0x00 0x100>, 645 <0x05 0x00000000 0x01 0x00000000>; 646 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 647 cdns,fifo-depth = <256>; 648 cdns,fifo-width = <4>; 649 cdns,trigger-address = <0x0>; 650 clocks = <&k3_clks 109 5>; 651 assigned-clocks = <&k3_clks 109 5>; 652 assigned-clock-parents = <&k3_clks 109 7>; 653 assigned-clock-rates = <166666666>; 654 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 658 status = "disabled"; /* Needs pinmux */ 659 }; 660 661 ospi1: spi@47050000 { 662 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 663 reg = <0x00 0x47050000 0x00 0x100>, 664 <0x07 0x00000000 0x01 0x00000000>; 665 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 666 cdns,fifo-depth = <256>; 667 cdns,fifo-width = <4>; 668 cdns,trigger-address = <0x0>; 669 clocks = <&k3_clks 110 5>; 670 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 status = "disabled"; /* Needs pinmux */ 675 }; 676 }; 677 678 wkup_vtm0: temperature-sensor@42040000 { 679 compatible = "ti,j7200-vtm"; 680 reg = <0x00 0x42040000 0x0 0x350>, 681 <0x00 0x42050000 0x0 0x350>; 682 power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; 683 #thermal-sensor-cells = <1>; 684 bootph-pre-ram; 685 }; 686 687 mcu_r5fss0: r5fss@41000000 { 688 compatible = "ti,j721s2-r5fss"; 689 ti,cluster-mode = <1>; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 ranges = <0x41000000 0x00 0x41000000 0x20000>, 693 <0x41400000 0x00 0x41400000 0x20000>; 694 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 695 status = "disabled"; 696 697 mcu_r5fss0_core0: r5f@41000000 { 698 compatible = "ti,j721s2-r5f"; 699 reg = <0x41000000 0x00010000>, 700 <0x41010000 0x00010000>; 701 reg-names = "atcm", "btcm"; 702 ti,sci = <&sms>; 703 ti,sci-dev-id = <284>; 704 ti,sci-proc-ids = <0x01 0xff>; 705 resets = <&k3_reset 284 1>; 706 firmware-name = "j721s2-mcu-r5f0_0-fw"; 707 ti,atcm-enable = <1>; 708 ti,btcm-enable = <1>; 709 ti,loczrama = <1>; 710 status = "disabled"; 711 }; 712 713 mcu_r5fss0_core1: r5f@41400000 { 714 compatible = "ti,j721s2-r5f"; 715 reg = <0x41400000 0x00010000>, 716 <0x41410000 0x00010000>; 717 reg-names = "atcm", "btcm"; 718 ti,sci = <&sms>; 719 ti,sci-dev-id = <285>; 720 ti,sci-proc-ids = <0x02 0xff>; 721 resets = <&k3_reset 285 1>; 722 firmware-name = "j721s2-mcu-r5f0_1-fw"; 723 ti,atcm-enable = <1>; 724 ti,btcm-enable = <1>; 725 ti,loczrama = <1>; 726 status = "disabled"; 727 }; 728 }; 729 730 mcu_esm: esm@40800000 { 731 compatible = "ti,j721e-esm"; 732 reg = <0x00 0x40800000 0x00 0x1000>; 733 ti,esm-pins = <95>; 734 bootph-pre-ram; 735 }; 736 737 wkup_esm: esm@42080000 { 738 compatible = "ti,j721e-esm"; 739 reg = <0x00 0x42080000 0x00 0x1000>; 740 ti,esm-pins = <63>; 741 bootph-pre-ram; 742 }; 743 744 /* 745 * The 2 RTI instances are couple with MCU R5Fs so keeping them 746 * reserved as these will be used by their respective firmware 747 */ 748 mcu_watchdog0: watchdog@40600000 { 749 compatible = "ti,j7-rti-wdt"; 750 reg = <0x00 0x40600000 0x00 0x100>; 751 clocks = <&k3_clks 295 1>; 752 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 753 assigned-clocks = <&k3_clks 295 1>; 754 assigned-clock-parents = <&k3_clks 295 5>; 755 /* reserved for MCU_R5F0_0 */ 756 status = "reserved"; 757 }; 758 759 mcu_watchdog1: watchdog@40610000 { 760 compatible = "ti,j7-rti-wdt"; 761 reg = <0x00 0x40610000 0x00 0x100>; 762 clocks = <&k3_clks 296 1>; 763 power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; 764 assigned-clocks = <&k3_clks 296 1>; 765 assigned-clock-parents = <&k3_clks 296 5>; 766 /* reserved for MCU_R5F0_1 */ 767 status = "reserved"; 768 }; 769};
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