k3-j721s2-main.dtsi

   1// SPDX-License-Identifier: GPL-2.0-only OR MIT
   2/*
   3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
   4 *
   5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
   6 */
   7
   8#include <dt-bindings/phy/phy-cadence.h>
   9#include <dt-bindings/phy/phy-ti.h>
  10
  11/ {
  12	serdes_refclk: clock-cmnrefclk {
  13		#clock-cells = <0>;
  14		compatible = "fixed-clock";
  15		clock-frequency = <0>;
  16	};
  17};
  18
  19&cbass_main {
  20	msmc_ram: sram@70000000 {
  21		compatible = "mmio-sram";
  22		reg = <0x0 0x70000000 0x0 0x400000>;
  23		#address-cells = <1>;
  24		#size-cells = <1>;
  25		ranges = <0x0 0x0 0x70000000 0x400000>;
  26
  27		atf-sram@0 {
  28			reg = <0x0 0x20000>;
  29		};
  30
  31		tifs-sram@1f0000 {
  32			reg = <0x1f0000 0x10000>;
  33		};
  34
  35		l3cache-sram@200000 {
  36			reg = <0x200000 0x200000>;
  37		};
  38	};
  39
  40	scm_conf: syscon@104000 {
  41		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  42		reg = <0x00 0x00104000 0x00 0x18000>;
  43		#address-cells = <1>;
  44		#size-cells = <1>;
  45		ranges = <0x00 0x00 0x00104000 0x18000>;
  46
  47		usb_serdes_mux: mux-controller@0 {
  48			compatible = "reg-mux";
  49			reg = <0x0 0x4>;
  50			#mux-control-cells = <1>;
  51			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  52		};
  53
  54		phy_gmii_sel_cpsw: phy@34 {
  55			compatible = "ti,am654-phy-gmii-sel";
  56			reg = <0x34 0x4>;
  57			#phy-cells = <1>;
  58		};
  59
  60		pcie1_ctrl: pcie-ctrl@74 {
  61			compatible = "ti,j784s4-pcie-ctrl", "syscon";
  62			reg = <0x74 0x4>;
  63		};
  64
  65		serdes_ln_ctrl: mux-controller@80 {
  66			compatible = "reg-mux";
  67			reg = <0x80 0x10>;
  68			#mux-control-cells = <1>;
  69			mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
  70					<0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
  71		};
  72
  73		ehrpwm_tbclk: clock-controller@140 {
  74			compatible = "ti,am654-ehrpwm-tbclk";
  75			reg = <0x140 0x18>;
  76			#clock-cells = <1>;
  77		};
  78	};
  79
  80	main_ehrpwm0: pwm@3000000 {
  81		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
  82		#pwm-cells = <3>;
  83		reg = <0x00 0x3000000 0x00 0x100>;
  84		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
  85		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
  86		clock-names = "tbclk", "fck";
  87		status = "disabled";
  88	};
  89
  90	main_ehrpwm1: pwm@3010000 {
  91		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
  92		#pwm-cells = <3>;
  93		reg = <0x00 0x3010000 0x00 0x100>;
  94		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
  95		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
  96		clock-names = "tbclk", "fck";
  97		status = "disabled";
  98	};
  99
 100	main_ehrpwm2: pwm@3020000 {
 101		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 102		#pwm-cells = <3>;
 103		reg = <0x00 0x3020000 0x00 0x100>;
 104		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
 105		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
 106		clock-names = "tbclk", "fck";
 107		status = "disabled";
 108	};
 109
 110	main_ehrpwm3: pwm@3030000 {
 111		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 112		#pwm-cells = <3>;
 113		reg = <0x00 0x3030000 0x00 0x100>;
 114		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
 115		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
 116		clock-names = "tbclk", "fck";
 117		status = "disabled";
 118	};
 119
 120	main_ehrpwm4: pwm@3040000 {
 121		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 122		#pwm-cells = <3>;
 123		reg = <0x00 0x3040000 0x00 0x100>;
 124		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
 125		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
 126		clock-names = "tbclk", "fck";
 127		status = "disabled";
 128	};
 129
 130	main_ehrpwm5: pwm@3050000 {
 131		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 132		#pwm-cells = <3>;
 133		reg = <0x00 0x3050000 0x00 0x100>;
 134		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
 135		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
 136		clock-names = "tbclk", "fck";
 137		status = "disabled";
 138	};
 139
 140	gic500: interrupt-controller@1800000 {
 141		compatible = "arm,gic-v3";
 142		#address-cells = <2>;
 143		#size-cells = <2>;
 144		ranges;
 145		#interrupt-cells = <3>;
 146		interrupt-controller;
 147		reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
 148		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
 149		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
 150		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
 151		      <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
 152
 153		/* vcpumntirq: virtual CPU interface maintenance interrupt */
 154		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 155
 156		gic_its: msi-controller@1820000 {
 157			compatible = "arm,gic-v3-its";
 158			reg = <0x00 0x01820000 0x00 0x10000>;
 159			socionext,synquacer-pre-its = <0x1000000 0x400000>;
 160			msi-controller;
 161			#msi-cells = <1>;
 162		};
 163	};
 164
 165	main_gpio_intr: interrupt-controller@a00000 {
 166		compatible = "ti,sci-intr";
 167		reg = <0x00 0x00a00000 0x00 0x800>;
 168		ti,intr-trigger-type = <1>;
 169		interrupt-controller;
 170		interrupt-parent = <&gic500>;
 171		#interrupt-cells = <1>;
 172		ti,sci = <&sms>;
 173		ti,sci-dev-id = <148>;
 174		ti,interrupt-ranges = <8 392 56>;
 175	};
 176
 177	main_pmx0: pinctrl@11c000 {
 178		compatible = "pinctrl-single";
 179		/* Proxy 0 addressing */
 180		reg = <0x0 0x11c000 0x0 0x120>;
 181		#pinctrl-cells = <1>;
 182		pinctrl-single,register-width = <32>;
 183		pinctrl-single,function-mask = <0xffffffff>;
 184	};
 185
 186	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 187	main_timerio_input: pinctrl@104200 {
 188		compatible = "pinctrl-single";
 189		reg = <0x00 0x104200 0x00 0x50>;
 190		#pinctrl-cells = <1>;
 191		pinctrl-single,register-width = <32>;
 192		pinctrl-single,function-mask = <0x00000007>;
 193	};
 194
 195	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 196	main_timerio_output: pinctrl@104280 {
 197		compatible = "pinctrl-single";
 198		reg = <0x00 0x104280 0x00 0x20>;
 199		#pinctrl-cells = <1>;
 200		pinctrl-single,register-width = <32>;
 201		pinctrl-single,function-mask = <0x0000001f>;
 202	};
 203
 204	main_crypto: crypto@4e00000 {
 205		compatible = "ti,j721e-sa2ul";
 206		reg = <0x00 0x04e00000 0x00 0x1200>;
 207		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
 208		#address-cells = <2>;
 209		#size-cells = <2>;
 210		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
 211
 212		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
 213		       <&main_udmap 0x4a41>;
 214		dma-names = "tx", "rx1", "rx2";
 215
 216		rng: rng@4e10000 {
 217			compatible = "inside-secure,safexcel-eip76";
 218			reg = <0x00 0x04e10000 0x00 0x7d>;
 219			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 220		};
 221	};
 222
 223	main_timer0: timer@2400000 {
 224		compatible = "ti,am654-timer";
 225		reg = <0x00 0x2400000 0x00 0x400>;
 226		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 227		clocks = <&k3_clks 63 1>;
 228		clock-names = "fck";
 229		assigned-clocks = <&k3_clks 63 1>;
 230		assigned-clock-parents = <&k3_clks 63 2>;
 231		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
 232		ti,timer-pwm;
 233	};
 234
 235	main_timer1: timer@2410000 {
 236		compatible = "ti,am654-timer";
 237		reg = <0x00 0x2410000 0x00 0x400>;
 238		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 239		clocks = <&k3_clks 64 1>;
 240		clock-names = "fck";
 241		assigned-clocks = <&k3_clks 64 1>;
 242		assigned-clock-parents = <&k3_clks 64 2>;
 243		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
 244		ti,timer-pwm;
 245	};
 246
 247	main_timer2: timer@2420000 {
 248		compatible = "ti,am654-timer";
 249		reg = <0x00 0x2420000 0x00 0x400>;
 250		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 251		clocks = <&k3_clks 65 1>;
 252		clock-names = "fck";
 253		assigned-clocks = <&k3_clks 65 1>;
 254		assigned-clock-parents = <&k3_clks 65 2>;
 255		power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
 256		ti,timer-pwm;
 257	};
 258
 259	main_timer3: timer@2430000 {
 260		compatible = "ti,am654-timer";
 261		reg = <0x00 0x2430000 0x00 0x400>;
 262		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 263		clocks = <&k3_clks 66 1>;
 264		clock-names = "fck";
 265		assigned-clocks = <&k3_clks 66 1>;
 266		assigned-clock-parents = <&k3_clks 66 2>;
 267		power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
 268		ti,timer-pwm;
 269	};
 270
 271	main_timer4: timer@2440000 {
 272		compatible = "ti,am654-timer";
 273		reg = <0x00 0x2440000 0x00 0x400>;
 274		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 275		clocks = <&k3_clks 67 1>;
 276		clock-names = "fck";
 277		assigned-clocks = <&k3_clks 67 1>;
 278		assigned-clock-parents = <&k3_clks 67 2>;
 279		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 280		ti,timer-pwm;
 281	};
 282
 283	main_timer5: timer@2450000 {
 284		compatible = "ti,am654-timer";
 285		reg = <0x00 0x2450000 0x00 0x400>;
 286		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 287		clocks = <&k3_clks 68 1>;
 288		clock-names = "fck";
 289		assigned-clocks = <&k3_clks 68 1>;
 290		assigned-clock-parents = <&k3_clks 68 2>;
 291		power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
 292		ti,timer-pwm;
 293	};
 294
 295	main_timer6: timer@2460000 {
 296		compatible = "ti,am654-timer";
 297		reg = <0x00 0x2460000 0x00 0x400>;
 298		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
 299		clocks = <&k3_clks 69 1>;
 300		clock-names = "fck";
 301		assigned-clocks = <&k3_clks 69 1>;
 302		assigned-clock-parents = <&k3_clks 69 2>;
 303		power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
 304		ti,timer-pwm;
 305	};
 306
 307	main_timer7: timer@2470000 {
 308		compatible = "ti,am654-timer";
 309		reg = <0x00 0x2470000 0x00 0x400>;
 310		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 311		clocks = <&k3_clks 70 1>;
 312		clock-names = "fck";
 313		assigned-clocks = <&k3_clks 70 1>;
 314		assigned-clock-parents = <&k3_clks 70 2>;
 315		power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
 316		ti,timer-pwm;
 317	};
 318
 319	main_timer8: timer@2480000 {
 320		compatible = "ti,am654-timer";
 321		reg = <0x00 0x2480000 0x00 0x400>;
 322		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 323		clocks = <&k3_clks 71 1>;
 324		clock-names = "fck";
 325		assigned-clocks = <&k3_clks 71 1>;
 326		assigned-clock-parents = <&k3_clks 71 2>;
 327		power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
 328		ti,timer-pwm;
 329	};
 330
 331	main_timer9: timer@2490000 {
 332		compatible = "ti,am654-timer";
 333		reg = <0x00 0x2490000 0x00 0x400>;
 334		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 335		clocks = <&k3_clks 72 1>;
 336		clock-names = "fck";
 337		assigned-clocks = <&k3_clks 72 1>;
 338		assigned-clock-parents = <&k3_clks 72 2>;
 339		power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
 340		ti,timer-pwm;
 341	};
 342
 343	main_timer10: timer@24a0000 {
 344		compatible = "ti,am654-timer";
 345		reg = <0x00 0x24a0000 0x00 0x400>;
 346		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 347		clocks = <&k3_clks 73 1>;
 348		clock-names = "fck";
 349		assigned-clocks = <&k3_clks 73 1>;
 350		assigned-clock-parents = <&k3_clks 73 2>;
 351		power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
 352		ti,timer-pwm;
 353	};
 354
 355	main_timer11: timer@24b0000 {
 356		compatible = "ti,am654-timer";
 357		reg = <0x00 0x24b0000 0x00 0x400>;
 358		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 359		clocks = <&k3_clks 74 1>;
 360		clock-names = "fck";
 361		assigned-clocks = <&k3_clks 74 1>;
 362		assigned-clock-parents = <&k3_clks 74 2>;
 363		power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
 364		ti,timer-pwm;
 365	};
 366
 367	main_timer12: timer@24c0000 {
 368		compatible = "ti,am654-timer";
 369		reg = <0x00 0x24c0000 0x00 0x400>;
 370		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
 371		clocks = <&k3_clks 75 1>;
 372		clock-names = "fck";
 373		assigned-clocks = <&k3_clks 75 1>;
 374		assigned-clock-parents = <&k3_clks 75 2>;
 375		power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 376		ti,timer-pwm;
 377	};
 378
 379	main_timer13: timer@24d0000 {
 380		compatible = "ti,am654-timer";
 381		reg = <0x00 0x24d0000 0x00 0x400>;
 382		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 383		clocks = <&k3_clks 76 1>;
 384		clock-names = "fck";
 385		assigned-clocks = <&k3_clks 76 1>;
 386		assigned-clock-parents = <&k3_clks 76 2>;
 387		power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
 388		ti,timer-pwm;
 389	};
 390
 391	main_timer14: timer@24e0000 {
 392		compatible = "ti,am654-timer";
 393		reg = <0x00 0x24e0000 0x00 0x400>;
 394		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 395		clocks = <&k3_clks 77 1>;
 396		clock-names = "fck";
 397		assigned-clocks = <&k3_clks 77 1>;
 398		assigned-clock-parents = <&k3_clks 77 2>;
 399		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 400		ti,timer-pwm;
 401	};
 402
 403	main_timer15: timer@24f0000 {
 404		compatible = "ti,am654-timer";
 405		reg = <0x00 0x24f0000 0x00 0x400>;
 406		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 407		clocks = <&k3_clks 78 1>;
 408		clock-names = "fck";
 409		assigned-clocks = <&k3_clks 78 1>;
 410		assigned-clock-parents = <&k3_clks 78 2>;
 411		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 412		ti,timer-pwm;
 413	};
 414
 415	main_timer16: timer@2500000 {
 416		compatible = "ti,am654-timer";
 417		reg = <0x00 0x2500000 0x00 0x400>;
 418		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 419		clocks = <&k3_clks 79 1>;
 420		clock-names = "fck";
 421		assigned-clocks = <&k3_clks 79 1>;
 422		assigned-clock-parents = <&k3_clks 79 2>;
 423		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 424		ti,timer-pwm;
 425	};
 426
 427	main_timer17: timer@2510000 {
 428		compatible = "ti,am654-timer";
 429		reg = <0x00 0x2510000 0x00 0x400>;
 430		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 431		clocks = <&k3_clks 80 1>;
 432		clock-names = "fck";
 433		assigned-clocks = <&k3_clks 80 1>;
 434		assigned-clock-parents = <&k3_clks 80 2>;
 435		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
 436		ti,timer-pwm;
 437	};
 438
 439	main_timer18: timer@2520000 {
 440		compatible = "ti,am654-timer";
 441		reg = <0x00 0x2520000 0x00 0x400>;
 442		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 443		clocks = <&k3_clks 81 1>;
 444		clock-names = "fck";
 445		assigned-clocks = <&k3_clks 81 1>;
 446		assigned-clock-parents = <&k3_clks 81 2>;
 447		power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
 448		ti,timer-pwm;
 449	};
 450
 451	main_timer19: timer@2530000 {
 452		compatible = "ti,am654-timer";
 453		reg = <0x00 0x2530000 0x00 0x400>;
 454		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 455		clocks = <&k3_clks 82 1>;
 456		clock-names = "fck";
 457		assigned-clocks = <&k3_clks 82 1>;
 458		assigned-clock-parents = <&k3_clks 82 2>;
 459		power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
 460		ti,timer-pwm;
 461	};
 462
 463	main_uart0: serial@2800000 {
 464		compatible = "ti,j721e-uart", "ti,am654-uart";
 465		reg = <0x00 0x02800000 0x00 0x200>;
 466		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 467		clocks = <&k3_clks 146 3>;
 468		clock-names = "fclk";
 469		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 470		status = "disabled";
 471	};
 472
 473	main_uart1: serial@2810000 {
 474		compatible = "ti,j721e-uart", "ti,am654-uart";
 475		reg = <0x00 0x02810000 0x00 0x200>;
 476		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 477		clocks = <&k3_clks 350 3>;
 478		clock-names = "fclk";
 479		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
 480		status = "disabled";
 481	};
 482
 483	main_uart2: serial@2820000 {
 484		compatible = "ti,j721e-uart", "ti,am654-uart";
 485		reg = <0x00 0x02820000 0x00 0x200>;
 486		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 487		clocks = <&k3_clks 351 3>;
 488		clock-names = "fclk";
 489		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
 490		status = "disabled";
 491	};
 492
 493	main_uart3: serial@2830000 {
 494		compatible = "ti,j721e-uart", "ti,am654-uart";
 495		reg = <0x00 0x02830000 0x00 0x200>;
 496		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 497		clocks = <&k3_clks 352 3>;
 498		clock-names = "fclk";
 499		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
 500		status = "disabled";
 501	};
 502
 503	main_uart4: serial@2840000 {
 504		compatible = "ti,j721e-uart", "ti,am654-uart";
 505		reg = <0x00 0x02840000 0x00 0x200>;
 506		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 507		clocks = <&k3_clks 353 3>;
 508		clock-names = "fclk";
 509		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
 510		status = "disabled";
 511	};
 512
 513	main_uart5: serial@2850000 {
 514		compatible = "ti,j721e-uart", "ti,am654-uart";
 515		reg = <0x00 0x02850000 0x00 0x200>;
 516		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 517		clocks = <&k3_clks 354 3>;
 518		clock-names = "fclk";
 519		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
 520		status = "disabled";
 521	};
 522
 523	main_uart6: serial@2860000 {
 524		compatible = "ti,j721e-uart", "ti,am654-uart";
 525		reg = <0x00 0x02860000 0x00 0x200>;
 526		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 527		clocks = <&k3_clks 355 3>;
 528		clock-names = "fclk";
 529		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
 530		status = "disabled";
 531	};
 532
 533	main_uart7: serial@2870000 {
 534		compatible = "ti,j721e-uart", "ti,am654-uart";
 535		reg = <0x00 0x02870000 0x00 0x200>;
 536		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 537		clocks = <&k3_clks 356 3>;
 538		clock-names = "fclk";
 539		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
 540		status = "disabled";
 541	};
 542
 543	main_uart8: serial@2880000 {
 544		compatible = "ti,j721e-uart", "ti,am654-uart";
 545		reg = <0x00 0x02880000 0x00 0x200>;
 546		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 547		clocks = <&k3_clks 357 3>;
 548		clock-names = "fclk";
 549		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
 550		status = "disabled";
 551	};
 552
 553	main_uart9: serial@2890000 {
 554		compatible = "ti,j721e-uart", "ti,am654-uart";
 555		reg = <0x00 0x02890000 0x00 0x200>;
 556		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 557		clocks = <&k3_clks 358 3>;
 558		clock-names = "fclk";
 559		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
 560		status = "disabled";
 561	};
 562
 563	main_gpio0: gpio@600000 {
 564		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 565		reg = <0x00 0x00600000 0x00 0x100>;
 566		gpio-controller;
 567		#gpio-cells = <2>;
 568		interrupt-parent = <&main_gpio_intr>;
 569		interrupts = <145>, <146>, <147>, <148>, <149>;
 570		interrupt-controller;
 571		#interrupt-cells = <2>;
 572		ti,ngpio = <66>;
 573		ti,davinci-gpio-unbanked = <0>;
 574		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 575		clocks = <&k3_clks 111 0>;
 576		clock-names = "gpio";
 577		status = "disabled";
 578	};
 579
 580	main_gpio2: gpio@610000 {
 581		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 582		reg = <0x00 0x00610000 0x00 0x100>;
 583		gpio-controller;
 584		#gpio-cells = <2>;
 585		interrupt-parent = <&main_gpio_intr>;
 586		interrupts = <154>, <155>, <156>, <157>, <158>;
 587		interrupt-controller;
 588		#interrupt-cells = <2>;
 589		ti,ngpio = <66>;
 590		ti,davinci-gpio-unbanked = <0>;
 591		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 592		clocks = <&k3_clks 112 0>;
 593		clock-names = "gpio";
 594		status = "disabled";
 595	};
 596
 597	main_gpio4: gpio@620000 {
 598		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 599		reg = <0x00 0x00620000 0x00 0x100>;
 600		gpio-controller;
 601		#gpio-cells = <2>;
 602		interrupt-parent = <&main_gpio_intr>;
 603		interrupts = <163>, <164>, <165>, <166>, <167>;
 604		interrupt-controller;
 605		#interrupt-cells = <2>;
 606		ti,ngpio = <66>;
 607		ti,davinci-gpio-unbanked = <0>;
 608		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 609		clocks = <&k3_clks 113 0>;
 610		clock-names = "gpio";
 611		status = "disabled";
 612	};
 613
 614	main_gpio6: gpio@630000 {
 615		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 616		reg = <0x00 0x00630000 0x00 0x100>;
 617		gpio-controller;
 618		#gpio-cells = <2>;
 619		interrupt-parent = <&main_gpio_intr>;
 620		interrupts = <172>, <173>, <174>, <175>, <176>;
 621		interrupt-controller;
 622		#interrupt-cells = <2>;
 623		ti,ngpio = <66>;
 624		ti,davinci-gpio-unbanked = <0>;
 625		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 626		clocks = <&k3_clks 114 0>;
 627		clock-names = "gpio";
 628		status = "disabled";
 629	};
 630
 631	main_i2c0: i2c@2000000 {
 632		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 633		reg = <0x00 0x02000000 0x00 0x100>;
 634		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 635		#address-cells = <1>;
 636		#size-cells = <0>;
 637		clocks = <&k3_clks 214 1>;
 638		clock-names = "fck";
 639		power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
 640	};
 641
 642	main_i2c1: i2c@2010000 {
 643		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 644		reg = <0x00 0x02010000 0x00 0x100>;
 645		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 646		#address-cells = <1>;
 647		#size-cells = <0>;
 648		clocks = <&k3_clks 215 1>;
 649		clock-names = "fck";
 650		power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
 651		status = "disabled";
 652	};
 653
 654	main_i2c2: i2c@2020000 {
 655		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 656		reg = <0x00 0x02020000 0x00 0x100>;
 657		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 658		#address-cells = <1>;
 659		#size-cells = <0>;
 660		clocks = <&k3_clks 216 1>;
 661		clock-names = "fck";
 662		power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
 663		status = "disabled";
 664	};
 665
 666	main_i2c3: i2c@2030000 {
 667		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 668		reg = <0x00 0x02030000 0x00 0x100>;
 669		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 670		#address-cells = <1>;
 671		#size-cells = <0>;
 672		clocks = <&k3_clks 217 1>;
 673		clock-names = "fck";
 674		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
 675		status = "disabled";
 676	};
 677
 678	main_i2c4: i2c@2040000 {
 679		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 680		reg = <0x00 0x02040000 0x00 0x100>;
 681		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 682		#address-cells = <1>;
 683		#size-cells = <0>;
 684		clocks = <&k3_clks 218 1>;
 685		clock-names = "fck";
 686		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
 687		status = "disabled";
 688	};
 689
 690	main_i2c5: i2c@2050000 {
 691		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 692		reg = <0x00 0x02050000 0x00 0x100>;
 693		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 694		#address-cells = <1>;
 695		#size-cells = <0>;
 696		clocks = <&k3_clks 219 1>;
 697		clock-names = "fck";
 698		power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
 699		status = "disabled";
 700	};
 701
 702	main_i2c6: i2c@2060000 {
 703		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 704		reg = <0x00 0x02060000 0x00 0x100>;
 705		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 706		#address-cells = <1>;
 707		#size-cells = <0>;
 708		clocks = <&k3_clks 220 1>;
 709		clock-names = "fck";
 710		power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
 711		status = "disabled";
 712	};
 713
 714	vpu: video-codec@4210000 {
 715		compatible = "ti,j721s2-wave521c", "cnm,wave521c";
 716		reg = <0x00 0x4210000 0x00 0x10000>;
 717		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 718		clocks = <&k3_clks 179 2>;
 719		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
 720	};
 721
 722	main_sdhci0: mmc@4f80000 {
 723		compatible = "ti,j721e-sdhci-8bit";
 724		reg = <0x00 0x04f80000 0x00 0x1000>,
 725		      <0x00 0x04f88000 0x00 0x400>;
 726		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 727		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 728		clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
 729		clock-names = "clk_ahb", "clk_xin";
 730		assigned-clocks = <&k3_clks 98 1>;
 731		assigned-clock-parents = <&k3_clks 98 2>;
 732		bus-width = <8>;
 733		ti,otap-del-sel-legacy = <0x0>;
 734		ti,otap-del-sel-mmc-hs = <0x0>;
 735		ti,otap-del-sel-ddr52 = <0x6>;
 736		ti,otap-del-sel-hs200 = <0x8>;
 737		ti,otap-del-sel-hs400 = <0x5>;
 738		ti,itap-del-sel-legacy = <0x10>;
 739		ti,itap-del-sel-mmc-hs = <0xa>;
 740		ti,strobe-sel = <0x77>;
 741		ti,clkbuf-sel = <0x7>;
 742		ti,trm-icp = <0x8>;
 743		mmc-ddr-1_8v;
 744		mmc-hs200-1_8v;
 745		mmc-hs400-1_8v;
 746		dma-coherent;
 747		status = "disabled";
 748	};
 749
 750	main_sdhci1: mmc@4fb0000 {
 751		compatible = "ti,j721e-sdhci-4bit";
 752		reg = <0x00 0x04fb0000 0x00 0x1000>,
 753		      <0x00 0x04fb8000 0x00 0x400>;
 754		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 755		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
 756		clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
 757		clock-names = "clk_ahb", "clk_xin";
 758		assigned-clocks = <&k3_clks 99 1>;
 759		assigned-clock-parents = <&k3_clks 99 2>;
 760		bus-width = <4>;
 761		ti,otap-del-sel-legacy = <0x0>;
 762		ti,otap-del-sel-sd-hs = <0x0>;
 763		ti,otap-del-sel-sdr12 = <0xf>;
 764		ti,otap-del-sel-sdr25 = <0xf>;
 765		ti,otap-del-sel-sdr50 = <0xc>;
 766		ti,otap-del-sel-sdr104 = <0x5>;
 767		ti,otap-del-sel-ddr50 = <0xc>;
 768		ti,itap-del-sel-legacy = <0x0>;
 769		ti,itap-del-sel-sd-hs = <0x0>;
 770		ti,itap-del-sel-sdr12 = <0x0>;
 771		ti,itap-del-sel-sdr25 = <0x0>;
 772		ti,itap-del-sel-ddr50 = <0x2>;
 773		ti,clkbuf-sel = <0x7>;
 774		ti,trm-icp = <0x8>;
 775		dma-coherent;
 776		status = "disabled";
 777	};
 778
 779	main_navss: bus@30000000 {
 780		compatible = "simple-bus";
 781		#address-cells = <2>;
 782		#size-cells = <2>;
 783		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
 784		ti,sci-dev-id = <224>;
 785		dma-coherent;
 786		dma-ranges;
 787
 788		main_navss_intr: interrupt-controller@310e0000 {
 789			compatible = "ti,sci-intr";
 790			reg = <0x00 0x310e0000 0x00 0x4000>;
 791			ti,intr-trigger-type = <4>;
 792			interrupt-controller;
 793			interrupt-parent = <&gic500>;
 794			#interrupt-cells = <1>;
 795			ti,sci = <&sms>;
 796			ti,sci-dev-id = <227>;
 797			ti,interrupt-ranges = <0 64 64>,
 798					      <64 448 64>,
 799					      <128 672 64>;
 800		};
 801
 802		main_udmass_inta: msi-controller@33d00000 {
 803			compatible = "ti,sci-inta";
 804			reg = <0x00 0x33d00000 0x00 0x100000>;
 805			interrupt-controller;
 806			#interrupt-cells = <0>;
 807			interrupt-parent = <&main_navss_intr>;
 808			msi-controller;
 809			ti,sci = <&sms>;
 810			ti,sci-dev-id = <265>;
 811			ti,interrupt-ranges = <0 0 256>;
 812			ti,unmapped-event-sources = <&main_bcdma_csi>;
 813		};
 814
 815		secure_proxy_main: mailbox@32c00000 {
 816			compatible = "ti,am654-secure-proxy";
 817			#mbox-cells = <1>;
 818			reg-names = "target_data", "rt", "scfg";
 819			reg = <0x00 0x32c00000 0x00 0x100000>,
 820			      <0x00 0x32400000 0x00 0x100000>,
 821			      <0x00 0x32800000 0x00 0x100000>;
 822			interrupt-names = "rx_011";
 823			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 824			bootph-all;
 825		};
 826
 827		hwspinlock: spinlock@30e00000 {
 828			compatible = "ti,am654-hwspinlock";
 829			reg = <0x00 0x30e00000 0x00 0x1000>;
 830			#hwlock-cells = <1>;
 831		};
 832
 833		mailbox0_cluster0: mailbox@31f80000 {
 834			compatible = "ti,am654-mailbox";
 835			reg = <0x00 0x31f80000 0x00 0x200>;
 836			#mbox-cells = <1>;
 837			ti,mbox-num-users = <4>;
 838			ti,mbox-num-fifos = <16>;
 839			interrupt-parent = <&main_navss_intr>;
 840			status = "disabled";
 841		};
 842
 843		mailbox0_cluster1: mailbox@31f81000 {
 844			compatible = "ti,am654-mailbox";
 845			reg = <0x00 0x31f81000 0x00 0x200>;
 846			#mbox-cells = <1>;
 847			ti,mbox-num-users = <4>;
 848			ti,mbox-num-fifos = <16>;
 849			interrupt-parent = <&main_navss_intr>;
 850			status = "disabled";
 851		};
 852
 853		mailbox0_cluster2: mailbox@31f82000 {
 854			compatible = "ti,am654-mailbox";
 855			reg = <0x00 0x31f82000 0x00 0x200>;
 856			#mbox-cells = <1>;
 857			ti,mbox-num-users = <4>;
 858			ti,mbox-num-fifos = <16>;
 859			interrupt-parent = <&main_navss_intr>;
 860			status = "disabled";
 861		};
 862
 863		mailbox0_cluster3: mailbox@31f83000 {
 864			compatible = "ti,am654-mailbox";
 865			reg = <0x00 0x31f83000 0x00 0x200>;
 866			#mbox-cells = <1>;
 867			ti,mbox-num-users = <4>;
 868			ti,mbox-num-fifos = <16>;
 869			interrupt-parent = <&main_navss_intr>;
 870			status = "disabled";
 871		};
 872
 873		mailbox0_cluster4: mailbox@31f84000 {
 874			compatible = "ti,am654-mailbox";
 875			reg = <0x00 0x31f84000 0x00 0x200>;
 876			#mbox-cells = <1>;
 877			ti,mbox-num-users = <4>;
 878			ti,mbox-num-fifos = <16>;
 879			interrupt-parent = <&main_navss_intr>;
 880			status = "disabled";
 881		};
 882
 883		mailbox0_cluster5: mailbox@31f85000 {
 884			compatible = "ti,am654-mailbox";
 885			reg = <0x00 0x31f85000 0x00 0x200>;
 886			#mbox-cells = <1>;
 887			ti,mbox-num-users = <4>;
 888			ti,mbox-num-fifos = <16>;
 889			interrupt-parent = <&main_navss_intr>;
 890			status = "disabled";
 891		};
 892
 893		mailbox0_cluster6: mailbox@31f86000 {
 894			compatible = "ti,am654-mailbox";
 895			reg = <0x00 0x31f86000 0x00 0x200>;
 896			#mbox-cells = <1>;
 897			ti,mbox-num-users = <4>;
 898			ti,mbox-num-fifos = <16>;
 899			interrupt-parent = <&main_navss_intr>;
 900			status = "disabled";
 901		};
 902
 903		mailbox0_cluster7: mailbox@31f87000 {
 904			compatible = "ti,am654-mailbox";
 905			reg = <0x00 0x31f87000 0x00 0x200>;
 906			#mbox-cells = <1>;
 907			ti,mbox-num-users = <4>;
 908			ti,mbox-num-fifos = <16>;
 909			interrupt-parent = <&main_navss_intr>;
 910			status = "disabled";
 911		};
 912
 913		mailbox0_cluster8: mailbox@31f88000 {
 914			compatible = "ti,am654-mailbox";
 915			reg = <0x00 0x31f88000 0x00 0x200>;
 916			#mbox-cells = <1>;
 917			ti,mbox-num-users = <4>;
 918			ti,mbox-num-fifos = <16>;
 919			interrupt-parent = <&main_navss_intr>;
 920			status = "disabled";
 921		};
 922
 923		mailbox0_cluster9: mailbox@31f89000 {
 924			compatible = "ti,am654-mailbox";
 925			reg = <0x00 0x31f89000 0x00 0x200>;
 926			#mbox-cells = <1>;
 927			ti,mbox-num-users = <4>;
 928			ti,mbox-num-fifos = <16>;
 929			interrupt-parent = <&main_navss_intr>;
 930			status = "disabled";
 931		};
 932
 933		mailbox0_cluster10: mailbox@31f8a000 {
 934			compatible = "ti,am654-mailbox";
 935			reg = <0x00 0x31f8a000 0x00 0x200>;
 936			#mbox-cells = <1>;
 937			ti,mbox-num-users = <4>;
 938			ti,mbox-num-fifos = <16>;
 939			interrupt-parent = <&main_navss_intr>;
 940			status = "disabled";
 941		};
 942
 943		mailbox0_cluster11: mailbox@31f8b000 {
 944			compatible = "ti,am654-mailbox";
 945			reg = <0x00 0x31f8b000 0x00 0x200>;
 946			#mbox-cells = <1>;
 947			ti,mbox-num-users = <4>;
 948			ti,mbox-num-fifos = <16>;
 949			interrupt-parent = <&main_navss_intr>;
 950			status = "disabled";
 951		};
 952
 953		mailbox1_cluster0: mailbox@31f90000 {
 954			compatible = "ti,am654-mailbox";
 955			reg = <0x00 0x31f90000 0x00 0x200>;
 956			#mbox-cells = <1>;
 957			ti,mbox-num-users = <4>;
 958			ti,mbox-num-fifos = <16>;
 959			interrupt-parent = <&main_navss_intr>;
 960			status = "disabled";
 961		};
 962
 963		mailbox1_cluster1: mailbox@31f91000 {
 964			compatible = "ti,am654-mailbox";
 965			reg = <0x00 0x31f91000 0x00 0x200>;
 966			#mbox-cells = <1>;
 967			ti,mbox-num-users = <4>;
 968			ti,mbox-num-fifos = <16>;
 969			interrupt-parent = <&main_navss_intr>;
 970			status = "disabled";
 971		};
 972
 973		mailbox1_cluster2: mailbox@31f92000 {
 974			compatible = "ti,am654-mailbox";
 975			reg = <0x00 0x31f92000 0x00 0x200>;
 976			#mbox-cells = <1>;
 977			ti,mbox-num-users = <4>;
 978			ti,mbox-num-fifos = <16>;
 979			interrupt-parent = <&main_navss_intr>;
 980			status = "disabled";
 981		};
 982
 983		mailbox1_cluster3: mailbox@31f93000 {
 984			compatible = "ti,am654-mailbox";
 985			reg = <0x00 0x31f93000 0x00 0x200>;
 986			#mbox-cells = <1>;
 987			ti,mbox-num-users = <4>;
 988			ti,mbox-num-fifos = <16>;
 989			interrupt-parent = <&main_navss_intr>;
 990			status = "disabled";
 991		};
 992
 993		mailbox1_cluster4: mailbox@31f94000 {
 994			compatible = "ti,am654-mailbox";
 995			reg = <0x00 0x31f94000 0x00 0x200>;
 996			#mbox-cells = <1>;
 997			ti,mbox-num-users = <4>;
 998			ti,mbox-num-fifos = <16>;
 999			interrupt-parent = <&main_navss_intr>;
1000			status = "disabled";
1001		};
1002
1003		mailbox1_cluster5: mailbox@31f95000 {
1004			compatible = "ti,am654-mailbox";
1005			reg = <0x00 0x31f95000 0x00 0x200>;
1006			#mbox-cells = <1>;
1007			ti,mbox-num-users = <4>;
1008			ti,mbox-num-fifos = <16>;
1009			interrupt-parent = <&main_navss_intr>;
1010			status = "disabled";
1011		};
1012
1013		mailbox1_cluster6: mailbox@31f96000 {
1014			compatible = "ti,am654-mailbox";
1015			reg = <0x00 0x31f96000 0x00 0x200>;
1016			#mbox-cells = <1>;
1017			ti,mbox-num-users = <4>;
1018			ti,mbox-num-fifos = <16>;
1019			interrupt-parent = <&main_navss_intr>;
1020			status = "disabled";
1021		};
1022
1023		mailbox1_cluster7: mailbox@31f97000 {
1024			compatible = "ti,am654-mailbox";
1025			reg = <0x00 0x31f97000 0x00 0x200>;
1026			#mbox-cells = <1>;
1027			ti,mbox-num-users = <4>;
1028			ti,mbox-num-fifos = <16>;
1029			interrupt-parent = <&main_navss_intr>;
1030			status = "disabled";
1031		};
1032
1033		mailbox1_cluster8: mailbox@31f98000 {
1034			compatible = "ti,am654-mailbox";
1035			reg = <0x00 0x31f98000 0x00 0x200>;
1036			#mbox-cells = <1>;
1037			ti,mbox-num-users = <4>;
1038			ti,mbox-num-fifos = <16>;
1039			interrupt-parent = <&main_navss_intr>;
1040			status = "disabled";
1041		};
1042
1043		mailbox1_cluster9: mailbox@31f99000 {
1044			compatible = "ti,am654-mailbox";
1045			reg = <0x00 0x31f99000 0x00 0x200>;
1046			#mbox-cells = <1>;
1047			ti,mbox-num-users = <4>;
1048			ti,mbox-num-fifos = <16>;
1049			interrupt-parent = <&main_navss_intr>;
1050			status = "disabled";
1051		};
1052
1053		mailbox1_cluster10: mailbox@31f9a000 {
1054			compatible = "ti,am654-mailbox";
1055			reg = <0x00 0x31f9a000 0x00 0x200>;
1056			#mbox-cells = <1>;
1057			ti,mbox-num-users = <4>;
1058			ti,mbox-num-fifos = <16>;
1059			interrupt-parent = <&main_navss_intr>;
1060			status = "disabled";
1061		};
1062
1063		mailbox1_cluster11: mailbox@31f9b000 {
1064			compatible = "ti,am654-mailbox";
1065			reg = <0x00 0x31f9b000 0x00 0x200>;
1066			#mbox-cells = <1>;
1067			ti,mbox-num-users = <4>;
1068			ti,mbox-num-fifos = <16>;
1069			interrupt-parent = <&main_navss_intr>;
1070			status = "disabled";
1071		};
1072
1073		main_ringacc: ringacc@3c000000 {
1074			compatible = "ti,am654-navss-ringacc";
1075			reg = <0x0 0x3c000000 0x0 0x400000>,
1076			      <0x0 0x38000000 0x0 0x400000>,
1077			      <0x0 0x31120000 0x0 0x100>,
1078			      <0x0 0x33000000 0x0 0x40000>,
1079			      <0x0 0x31080000 0x0 0x40000>;
1080			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1081			ti,num-rings = <1024>;
1082			ti,sci-rm-range-gp-rings = <0x1>;
1083			ti,sci = <&sms>;
1084			ti,sci-dev-id = <259>;
1085			msi-parent = <&main_udmass_inta>;
1086		};
1087
1088		main_udmap: dma-controller@31150000 {
1089			compatible = "ti,j721e-navss-main-udmap";
1090			reg = <0x0 0x31150000 0x0 0x100>,
1091			      <0x0 0x34000000 0x0 0x80000>,
1092			      <0x0 0x35000000 0x0 0x200000>,
1093			      <0x0 0x30b00000 0x0 0x20000>,
1094			      <0x0 0x30c00000 0x0 0x8000>,
1095			      <0x0 0x30d00000 0x0 0x4000>;
1096			reg-names = "gcfg", "rchanrt", "tchanrt",
1097				    "tchan", "rchan", "rflow";
1098			msi-parent = <&main_udmass_inta>;
1099			#dma-cells = <1>;
1100
1101			ti,sci = <&sms>;
1102			ti,sci-dev-id = <263>;
1103			ti,ringacc = <&main_ringacc>;
1104
1105			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1106						<0x0f>, /* TX_HCHAN */
1107						<0x10>; /* TX_UHCHAN */
1108			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1109						<0x0b>, /* RX_HCHAN */
1110						<0x0c>; /* RX_UHCHAN */
1111			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1112		};
1113
1114		main_bcdma_csi: dma-controller@311a0000 {
1115			compatible = "ti,j721s2-dmss-bcdma-csi";
1116			reg = <0x00 0x311a0000 0x00 0x100>,
1117			      <0x00 0x35d00000 0x00 0x20000>,
1118			      <0x00 0x35c00000 0x00 0x10000>,
1119			      <0x00 0x35e00000 0x00 0x80000>;
1120			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1121			msi-parent = <&main_udmass_inta>;
1122			#dma-cells = <3>;
1123			ti,sci = <&sms>;
1124			ti,sci-dev-id = <225>;
1125			ti,sci-rm-range-rchan = <0x21>;
1126			ti,sci-rm-range-tchan = <0x22>;
1127		};
1128
1129		cpts@310d0000 {
1130			compatible = "ti,j721e-cpts";
1131			reg = <0x0 0x310d0000 0x0 0x400>;
1132			reg-names = "cpts";
1133			clocks = <&k3_clks 226 5>;
1134			clock-names = "cpts";
1135			assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1136			assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1137			interrupts-extended = <&main_navss_intr 391>;
1138			interrupt-names = "cpts";
1139			ti,cpts-periodic-outputs = <6>;
1140			ti,cpts-ext-ts-inputs = <8>;
1141		};
1142	};
1143
1144	main_cpsw: ethernet@c200000 {
1145		compatible = "ti,j721e-cpsw-nuss";
1146		reg = <0x00 0xc200000 0x00 0x200000>;
1147		reg-names = "cpsw_nuss";
1148		ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1149		#address-cells = <2>;
1150		#size-cells = <2>;
1151		dma-coherent;
1152		clocks = <&k3_clks 28 28>;
1153		clock-names = "fck";
1154		power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1155
1156		dmas = <&main_udmap 0xc640>,
1157		       <&main_udmap 0xc641>,
1158		       <&main_udmap 0xc642>,
1159		       <&main_udmap 0xc643>,
1160		       <&main_udmap 0xc644>,
1161		       <&main_udmap 0xc645>,
1162		       <&main_udmap 0xc646>,
1163		       <&main_udmap 0xc647>,
1164		       <&main_udmap 0x4640>;
1165		dma-names = "tx0", "tx1", "tx2", "tx3",
1166			    "tx4", "tx5", "tx6", "tx7",
1167			    "rx";
1168
1169		status = "disabled";
1170
1171		ethernet-ports {
1172			#address-cells = <1>;
1173			#size-cells = <0>;
1174
1175			main_cpsw_port1: port@1 {
1176				reg = <1>;
1177				ti,mac-only;
1178				label = "port1";
1179				phys = <&phy_gmii_sel_cpsw 1>;
1180				status = "disabled";
1181			};
1182		};
1183
1184		main_cpsw_mdio: mdio@f00 {
1185			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1186			reg = <0x00 0xf00 0x00 0x100>;
1187			#address-cells = <1>;
1188			#size-cells = <0>;
1189			clocks = <&k3_clks 28 28>;
1190			clock-names = "fck";
1191			bus_freq = <1000000>;
1192			status = "disabled";
1193		};
1194
1195		cpts@3d000 {
1196			compatible = "ti,am65-cpts";
1197			reg = <0x00 0x3d000 0x00 0x400>;
1198			clocks = <&k3_clks 28 3>;
1199			clock-names = "cpts";
1200			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1201			interrupt-names = "cpts";
1202			ti,cpts-ext-ts-inputs = <4>;
1203			ti,cpts-periodic-outputs = <2>;
1204		};
1205	};
1206
1207	usbss0: cdns-usb@4104000 {
1208		compatible = "ti,j721e-usb";
1209		reg = <0x00 0x04104000 0x00 0x100>;
1210		clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
1211		clock-names = "ref", "lpm";
1212		assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1213		assigned-clock-parents = <&k3_clks 360 17>;
1214		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1215		#address-cells = <2>;
1216		#size-cells = <2>;
1217		ranges;
1218		dma-coherent;
1219
1220		status = "disabled"; /* Needs pinmux */
1221
1222		usb0: usb@6000000 {
1223			compatible = "cdns,usb3";
1224			reg = <0x00 0x06000000 0x00 0x10000>,
1225			      <0x00 0x06010000 0x00 0x10000>,
1226			      <0x00 0x06020000 0x00 0x10000>;
1227			reg-names = "otg", "xhci", "dev";
1228			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1229				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1230				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1231			interrupt-names = "host", "peripheral", "otg";
1232			maximum-speed = "super-speed";
1233			dr_mode = "otg";
1234		};
1235	};
1236
1237	ti_csi2rx0: ticsi2rx@4500000 {
1238		compatible = "ti,j721e-csi2rx-shim";
1239		reg = <0x00 0x04500000 0x00 0x1000>;
1240		ranges;
1241		#address-cells = <2>;
1242		#size-cells = <2>;
1243		dmas = <&main_bcdma_csi 0 0x4940 0>;
1244		dma-names = "rx0";
1245		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
1246		status = "disabled";
1247
1248		cdns_csi2rx0: csi-bridge@4504000 {
1249			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1250			reg = <0x00 0x04504000 0x00 0x1000>;
1251			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1252				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1253			interrupt-names = "error_irq", "irq";
1254			clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
1255				<&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
1256			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1257				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1258			phys = <&dphy0>;
1259			phy-names = "dphy";
1260
1261			ports {
1262				#address-cells = <1>;
1263				#size-cells = <0>;
1264
1265				csi0_port0: port@0 {
1266					reg = <0>;
1267					status = "disabled";
1268				};
1269
1270				csi0_port1: port@1 {
1271					reg = <1>;
1272					status = "disabled";
1273				};
1274
1275				csi0_port2: port@2 {
1276					reg = <2>;
1277					status = "disabled";
1278				};
1279
1280				csi0_port3: port@3 {
1281					reg = <3>;
1282					status = "disabled";
1283				};
1284
1285				csi0_port4: port@4 {
1286					reg = <4>;
1287					status = "disabled";
1288				};
1289			};
1290		};
1291	};
1292
1293	ti_csi2rx1: ticsi2rx@4510000 {
1294		compatible = "ti,j721e-csi2rx-shim";
1295		reg = <0x00 0x04510000 0x00 0x1000>;
1296		ranges;
1297		#address-cells = <2>;
1298		#size-cells = <2>;
1299		dmas = <&main_bcdma_csi 0 0x4960 0>;
1300		dma-names = "rx0";
1301		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
1302		status = "disabled";
1303
1304		cdns_csi2rx1: csi-bridge@4514000 {
1305			compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
1306			reg = <0x00 0x04514000 0x00 0x1000>;
1307			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1308				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1309			interrupt-names = "error_irq", "irq";
1310			clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
1311				<&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
1312			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
1313				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
1314			phys = <&dphy1>;
1315			phy-names = "dphy";
1316
1317			ports {
1318				#address-cells = <1>;
1319				#size-cells = <0>;
1320
1321				csi1_port0: port@0 {
1322					reg = <0>;
1323					status = "disabled";
1324				};
1325
1326				csi1_port1: port@1 {
1327					reg = <1>;
1328					status = "disabled";
1329				};
1330
1331				csi1_port2: port@2 {
1332					reg = <2>;
1333					status = "disabled";
1334				};
1335
1336				csi1_port3: port@3 {
1337					reg = <3>;
1338					status = "disabled";
1339				};
1340
1341				csi1_port4: port@4 {
1342					reg = <4>;
1343					status = "disabled";
1344				};
1345			};
1346		};
1347	};
1348
1349	dphy0: phy@4580000 {
1350		compatible = "cdns,dphy-rx";
1351		reg = <0x00 0x04580000 0x00 0x1100>;
1352		#phy-cells = <0>;
1353		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1354		status = "disabled";
1355	};
1356
1357	dphy1: phy@4590000 {
1358		compatible = "cdns,dphy-rx";
1359		reg = <0x00 0x04590000 0x00 0x1100>;
1360		#phy-cells = <0>;
1361		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
1362		status = "disabled";
1363	};
1364
1365	serdes_wiz0: wiz@5060000 {
1366		compatible = "ti,j721s2-wiz-10g";
1367		#address-cells = <1>;
1368		#size-cells = <1>;
1369		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1370		clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1371		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1372		num-lanes = <4>;
1373		#reset-cells = <1>;
1374		#clock-cells = <1>;
1375		ranges = <0x5060000 0x0 0x5060000 0x10000>;
1376
1377		assigned-clocks = <&k3_clks 365 3>;
1378		assigned-clock-parents = <&k3_clks 365 7>;
1379
1380		serdes0: serdes@5060000 {
1381			compatible = "ti,j721e-serdes-10g";
1382			reg = <0x05060000 0x00010000>;
1383			reg-names = "torrent_phy";
1384			resets = <&serdes_wiz0 0>;
1385			reset-names = "torrent_reset";
1386			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1387				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1388			clock-names = "refclk", "phy_en_refclk";
1389			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1390					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1391					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1392			assigned-clock-parents = <&k3_clks 365 3>,
1393						 <&k3_clks 365 3>,
1394						 <&k3_clks 365 3>;
1395			#address-cells = <1>;
1396			#size-cells = <0>;
1397			#clock-cells = <1>;
1398
1399			status = "disabled"; /* Needs lane config */
1400		};
1401	};
1402
1403	pcie1_rc: pcie@2910000 {
1404		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1405		reg = <0x00 0x02910000 0x00 0x1000>,
1406		      <0x00 0x02917000 0x00 0x400>,
1407		      <0x00 0x0d800000 0x00 0x800000>,
1408		      <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */
1409		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1410		interrupt-names = "link_state";
1411		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1412		device_type = "pci";
1413		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
1414		max-link-speed = <3>;
1415		num-lanes = <4>;
1416		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1417		clocks = <&k3_clks 276 41>;
1418		clock-names = "fck";
1419		#address-cells = <3>;
1420		#size-cells = <2>;
1421		bus-range = <0x0 0xff>;
1422		vendor-id = <0x104c>;
1423		device-id = <0xb013>;
1424		msi-map = <0x0 &gic_its 0x0 0x10000>;
1425		dma-coherent;
1426		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
1427			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
1428		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1429		#interrupt-cells = <1>;
1430		interrupt-map-mask = <0 0 0 7>;
1431		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1432				<0 0 0 2 &pcie1_intc 0>, /* INT B */
1433				<0 0 0 3 &pcie1_intc 0>, /* INT C */
1434				<0 0 0 4 &pcie1_intc 0>; /* INT D */
1435
1436		status = "disabled"; /* Needs gpio and serdes info */
1437
1438		pcie1_intc: interrupt-controller {
1439			interrupt-controller;
1440			#address-cells = <0>;
1441			#interrupt-cells = <1>;
1442			interrupt-parent = <&gic500>;
1443			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
1444		};
1445	};
1446
1447	main_mcan0: can@2701000 {
1448		compatible = "bosch,m_can";
1449		reg = <0x00 0x02701000 0x00 0x200>,
1450		      <0x00 0x02708000 0x00 0x8000>;
1451		reg-names = "m_can", "message_ram";
1452		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1453		clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1454		clock-names = "hclk", "cclk";
1455		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1456			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1457		interrupt-names = "int0", "int1";
1458		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1459		status = "disabled";
1460	};
1461
1462	main_mcan1: can@2711000 {
1463		compatible = "bosch,m_can";
1464		reg = <0x00 0x02711000 0x00 0x200>,
1465		      <0x00 0x02718000 0x00 0x8000>;
1466		reg-names = "m_can", "message_ram";
1467		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1468		clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1469		clock-names = "hclk", "cclk";
1470		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1471			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1472		interrupt-names = "int0", "int1";
1473		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1474		status = "disabled";
1475	};
1476
1477	main_mcan2: can@2721000 {
1478		compatible = "bosch,m_can";
1479		reg = <0x00 0x02721000 0x00 0x200>,
1480		      <0x00 0x02728000 0x00 0x8000>;
1481		reg-names = "m_can", "message_ram";
1482		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1483		clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1484		clock-names = "hclk", "cclk";
1485		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1486			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1487		interrupt-names = "int0", "int1";
1488		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1489		status = "disabled";
1490	};
1491
1492	main_mcan3: can@2731000 {
1493		compatible = "bosch,m_can";
1494		reg = <0x00 0x02731000 0x00 0x200>,
1495		      <0x00 0x02738000 0x00 0x8000>;
1496		reg-names = "m_can", "message_ram";
1497		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1498		clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1499		clock-names = "hclk", "cclk";
1500		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1501			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1502		interrupt-names = "int0", "int1";
1503		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1504		status = "disabled";
1505	};
1506
1507	main_mcan4: can@2741000 {
1508		compatible = "bosch,m_can";
1509		reg = <0x00 0x02741000 0x00 0x200>,
1510		      <0x00 0x02748000 0x00 0x8000>;
1511		reg-names = "m_can", "message_ram";
1512		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1513		clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1514		clock-names = "hclk", "cclk";
1515		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1516			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1517		interrupt-names = "int0", "int1";
1518		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1519		status = "disabled";
1520	};
1521
1522	main_mcan5: can@2751000 {
1523		compatible = "bosch,m_can";
1524		reg = <0x00 0x02751000 0x00 0x200>,
1525		      <0x00 0x02758000 0x00 0x8000>;
1526		reg-names = "m_can", "message_ram";
1527		power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1528		clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1529		clock-names = "hclk", "cclk";
1530		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1531			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1532		interrupt-names = "int0", "int1";
1533		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1534		status = "disabled";
1535	};
1536
1537	main_mcan6: can@2761000 {
1538		compatible = "bosch,m_can";
1539		reg = <0x00 0x02761000 0x00 0x200>,
1540		      <0x00 0x02768000 0x00 0x8000>;
1541		reg-names = "m_can", "message_ram";
1542		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1543		clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1544		clock-names = "hclk", "cclk";
1545		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1546			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1547		interrupt-names = "int0", "int1";
1548		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1549		status = "disabled";
1550	};
1551
1552	main_mcan7: can@2771000 {
1553		compatible = "bosch,m_can";
1554		reg = <0x00 0x02771000 0x00 0x200>,
1555		      <0x00 0x02778000 0x00 0x8000>;
1556		reg-names = "m_can", "message_ram";
1557		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1558		clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1559		clock-names = "hclk", "cclk";
1560		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1561			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1562		interrupt-names = "int0", "int1";
1563		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1564		status = "disabled";
1565	};
1566
1567	main_mcan8: can@2781000 {
1568		compatible = "bosch,m_can";
1569		reg = <0x00 0x02781000 0x00 0x200>,
1570		      <0x00 0x02788000 0x00 0x8000>;
1571		reg-names = "m_can", "message_ram";
1572		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1573		clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1574		clock-names = "hclk", "cclk";
1575		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1576			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1577		interrupt-names = "int0", "int1";
1578		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1579		status = "disabled";
1580	};
1581
1582	main_mcan9: can@2791000 {
1583		compatible = "bosch,m_can";
1584		reg = <0x00 0x02791000 0x00 0x200>,
1585		      <0x00 0x02798000 0x00 0x8000>;
1586		reg-names = "m_can", "message_ram";
1587		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1588		clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1589		clock-names = "hclk", "cclk";
1590		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1591			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1592		interrupt-names = "int0", "int1";
1593		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1594		status = "disabled";
1595	};
1596
1597	main_mcan10: can@27a1000 {
1598		compatible = "bosch,m_can";
1599		reg = <0x00 0x027a1000 0x00 0x200>,
1600		      <0x00 0x027a8000 0x00 0x8000>;
1601		reg-names = "m_can", "message_ram";
1602		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1603		clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1604		clock-names = "hclk", "cclk";
1605		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1606			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1607		interrupt-names = "int0", "int1";
1608		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1609		status = "disabled";
1610	};
1611
1612	main_mcan11: can@27b1000 {
1613		compatible = "bosch,m_can";
1614		reg = <0x00 0x027b1000 0x00 0x200>,
1615		      <0x00 0x027b8000 0x00 0x8000>;
1616		reg-names = "m_can", "message_ram";
1617		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1618		clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1619		clock-names = "hclk", "cclk";
1620		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1621			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1622		interrupt-names = "int0", "int1";
1623		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1624		status = "disabled";
1625	};
1626
1627	main_mcan12: can@27c1000 {
1628		compatible = "bosch,m_can";
1629		reg = <0x00 0x027c1000 0x00 0x200>,
1630		      <0x00 0x027c8000 0x00 0x8000>;
1631		reg-names = "m_can", "message_ram";
1632		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1633		clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1634		clock-names = "hclk", "cclk";
1635		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1636			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1637		interrupt-names = "int0", "int1";
1638		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1639		status = "disabled";
1640	};
1641
1642	main_mcan13: can@27d1000 {
1643		compatible = "bosch,m_can";
1644		reg = <0x00 0x027d1000 0x00 0x200>,
1645		      <0x00 0x027d8000 0x00 0x8000>;
1646		reg-names = "m_can", "message_ram";
1647		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1648		clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1649		clock-names = "hclk", "cclk";
1650		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1651			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1652		interrupt-names = "int0", "int1";
1653		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1654		status = "disabled";
1655	};
1656
1657	main_mcan14: can@2681000 {
1658		compatible = "bosch,m_can";
1659		reg = <0x00 0x02681000 0x00 0x200>,
1660		      <0x00 0x02688000 0x00 0x8000>;
1661		reg-names = "m_can", "message_ram";
1662		power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1663		clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1664		clock-names = "hclk", "cclk";
1665		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1666			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1667		interrupt-names = "int0", "int1";
1668		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1669		status = "disabled";
1670	};
1671
1672	main_mcan15: can@2691000 {
1673		compatible = "bosch,m_can";
1674		reg = <0x00 0x02691000 0x00 0x200>,
1675		      <0x00 0x02698000 0x00 0x8000>;
1676		reg-names = "m_can", "message_ram";
1677		power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1678		clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1679		clock-names = "hclk", "cclk";
1680		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1681			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1682		interrupt-names = "int0", "int1";
1683		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1684		status = "disabled";
1685	};
1686
1687	main_mcan16: can@26a1000 {
1688		compatible = "bosch,m_can";
1689		reg = <0x00 0x026a1000 0x00 0x200>,
1690		      <0x00 0x026a8000 0x00 0x8000>;
1691		reg-names = "m_can", "message_ram";
1692		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1693		clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1694		clock-names = "hclk", "cclk";
1695		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1696			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1697		interrupt-names = "int0", "int1";
1698		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1699		status = "disabled";
1700	};
1701
1702	main_mcan17: can@26b1000 {
1703		compatible = "bosch,m_can";
1704		reg = <0x00 0x026b1000 0x00 0x200>,
1705		      <0x00 0x026b8000 0x00 0x8000>;
1706		reg-names = "m_can", "message_ram";
1707		power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1708		clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1709		clock-names = "hclk", "cclk";
1710		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1711			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1712		interrupt-names = "int0", "int1";
1713		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1714		status = "disabled";
1715	};
1716
1717	main_spi0: spi@2100000 {
1718		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1719		reg = <0x00 0x02100000 0x00 0x400>;
1720		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1721		#address-cells = <1>;
1722		#size-cells = <0>;
1723		power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1724		clocks = <&k3_clks 339 2>;
1725		status = "disabled";
1726	};
1727
1728	main_spi1: spi@2110000 {
1729		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1730		reg = <0x00 0x02110000 0x00 0x400>;
1731		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1732		#address-cells = <1>;
1733		#size-cells = <0>;
1734		power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1735		clocks = <&k3_clks 340 2>;
1736		status = "disabled";
1737	};
1738
1739	main_spi2: spi@2120000 {
1740		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1741		reg = <0x00 0x02120000 0x00 0x400>;
1742		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1743		#address-cells = <1>;
1744		#size-cells = <0>;
1745		power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1746		clocks = <&k3_clks 341 2>;
1747		status = "disabled";
1748	};
1749
1750	main_spi3: spi@2130000 {
1751		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1752		reg = <0x00 0x02130000 0x00 0x400>;
1753		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1754		#address-cells = <1>;
1755		#size-cells = <0>;
1756		power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1757		clocks = <&k3_clks 342 2>;
1758		status = "disabled";
1759	};
1760
1761	main_spi4: spi@2140000 {
1762		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1763		reg = <0x00 0x02140000 0x00 0x400>;
1764		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1765		#address-cells = <1>;
1766		#size-cells = <0>;
1767		power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1768		clocks = <&k3_clks 343 2>;
1769		status = "disabled";
1770	};
1771
1772	main_spi5: spi@2150000 {
1773		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1774		reg = <0x00 0x02150000 0x00 0x400>;
1775		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1776		#address-cells = <1>;
1777		#size-cells = <0>;
1778		power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1779		clocks = <&k3_clks 344 2>;
1780		status = "disabled";
1781	};
1782
1783	main_spi6: spi@2160000 {
1784		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1785		reg = <0x00 0x02160000 0x00 0x400>;
1786		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1787		#address-cells = <1>;
1788		#size-cells = <0>;
1789		power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1790		clocks = <&k3_clks 345 2>;
1791		status = "disabled";
1792	};
1793
1794	main_spi7: spi@2170000 {
1795		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1796		reg = <0x00 0x02170000 0x00 0x400>;
1797		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1798		#address-cells = <1>;
1799		#size-cells = <0>;
1800		power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1801		clocks = <&k3_clks 346 2>;
1802		status = "disabled";
1803	};
1804
1805	dphy_tx0: phy@4480000 {
1806		compatible = "ti,j721e-dphy";
1807		reg = <0x00 0x04480000 0x00 0x00001000>;
1808		clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
1809		clock-names = "psm", "pll_ref";
1810		#phy-cells = <0>;
1811		power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
1812		assigned-clocks = <&k3_clks 363 14>;
1813		assigned-clock-parents = <&k3_clks 363 15>;
1814		assigned-clock-rates = <19200000>;
1815		status = "disabled";
1816	};
1817
1818	dsi0: dsi@4800000 {
1819		compatible = "ti,j721e-dsi";
1820		reg = <0x00 0x04800000 0x00 0x00100000>,
1821		      <0x00 0x04710000 0x00 0x00000100>;
1822		clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
1823		clock-names = "dsi_p_clk", "dsi_sys_clk";
1824		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
1825		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1826		phys = <&dphy_tx0>;
1827		phy-names = "dphy";
1828		status = "disabled";
1829
1830		dsi0_ports: ports {
1831			#address-cells = <1>;
1832			#size-cells = <0>;
1833
1834			port@0 {
1835				reg = <0>;
1836			};
1837
1838			port@1 {
1839				reg = <1>;
1840			};
1841		};
1842	};
1843
1844	dss: dss@4a00000 {
1845		compatible = "ti,j721e-dss";
1846		reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1847		      <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1848		      <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1849		      <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1850		      <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1851		      <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1852		      <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1853		      <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1854		      <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1855		      <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1856		      <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1857		      <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1858		      <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1859		      <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1860		      <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1861		      <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1862		      <0x00 0x04af0000 0x00 0x10000>; /* wb */
1863		reg-names = "common_m", "common_s0",
1864			    "common_s1", "common_s2",
1865			    "vidl1", "vidl2","vid1","vid2",
1866			    "ovr1", "ovr2", "ovr3", "ovr4",
1867			    "vp1", "vp2", "vp3", "vp4",
1868			    "wb";
1869		clocks = <&k3_clks 158 0>,
1870			 <&k3_clks 158 2>,
1871			 <&k3_clks 158 5>,
1872			 <&k3_clks 158 14>,
1873			 <&k3_clks 158 18>;
1874		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1875		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1876		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1877			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1878			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1879			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1880		interrupt-names = "common_m",
1881				  "common_s0",
1882				  "common_s1",
1883				  "common_s2";
1884		status = "disabled";
1885
1886		dss_ports: ports {
1887		};
1888	};
1889
1890	main_r5fss0: r5fss@5c00000 {
1891		compatible = "ti,j721s2-r5fss";
1892		ti,cluster-mode = <1>;
1893		#address-cells = <1>;
1894		#size-cells = <1>;
1895		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1896			 <0x5d00000 0x00 0x5d00000 0x20000>;
1897		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1898		status = "disabled";
1899
1900		main_r5fss0_core0: r5f@5c00000 {
1901			compatible = "ti,j721s2-r5f";
1902			reg = <0x5c00000 0x00010000>,
1903			      <0x5c10000 0x00010000>;
1904			reg-names = "atcm", "btcm";
1905			ti,sci = <&sms>;
1906			ti,sci-dev-id = <279>;
1907			ti,sci-proc-ids = <0x06 0xff>;
1908			resets = <&k3_reset 279 1>;
1909			firmware-name = "j721s2-main-r5f0_0-fw";
1910			ti,atcm-enable = <1>;
1911			ti,btcm-enable = <1>;
1912			ti,loczrama = <1>;
1913			status = "disabled";
1914		};
1915
1916		main_r5fss0_core1: r5f@5d00000 {
1917			compatible = "ti,j721s2-r5f";
1918			reg = <0x5d00000 0x00010000>,
1919			      <0x5d10000 0x00010000>;
1920			reg-names = "atcm", "btcm";
1921			ti,sci = <&sms>;
1922			ti,sci-dev-id = <280>;
1923			ti,sci-proc-ids = <0x07 0xff>;
1924			resets = <&k3_reset 280 1>;
1925			firmware-name = "j721s2-main-r5f0_1-fw";
1926			ti,atcm-enable = <1>;
1927			ti,btcm-enable = <1>;
1928			ti,loczrama = <1>;
1929			status = "disabled";
1930		};
1931	};
1932
1933	main_r5fss1: r5fss@5e00000 {
1934		compatible = "ti,j721s2-r5fss";
1935		ti,cluster-mode = <1>;
1936		#address-cells = <1>;
1937		#size-cells = <1>;
1938		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1939			 <0x5f00000 0x00 0x5f00000 0x20000>;
1940		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1941		status = "disabled";
1942
1943		main_r5fss1_core0: r5f@5e00000 {
1944			compatible = "ti,j721s2-r5f";
1945			reg = <0x5e00000 0x00010000>,
1946			      <0x5e10000 0x00010000>;
1947			reg-names = "atcm", "btcm";
1948			ti,sci = <&sms>;
1949			ti,sci-dev-id = <281>;
1950			ti,sci-proc-ids = <0x08 0xff>;
1951			resets = <&k3_reset 281 1>;
1952			firmware-name = "j721s2-main-r5f1_0-fw";
1953			ti,atcm-enable = <1>;
1954			ti,btcm-enable = <1>;
1955			ti,loczrama = <1>;
1956			status = "disabled";
1957		};
1958
1959		main_r5fss1_core1: r5f@5f00000 {
1960			compatible = "ti,j721s2-r5f";
1961			reg = <0x5f00000 0x00010000>,
1962			      <0x5f10000 0x00010000>;
1963			reg-names = "atcm", "btcm";
1964			ti,sci = <&sms>;
1965			ti,sci-dev-id = <282>;
1966			ti,sci-proc-ids = <0x09 0xff>;
1967			resets = <&k3_reset 282 1>;
1968			firmware-name = "j721s2-main-r5f1_1-fw";
1969			ti,atcm-enable = <1>;
1970			ti,btcm-enable = <1>;
1971			ti,loczrama = <1>;
1972			status = "disabled";
1973		};
1974	};
1975
1976	c71_0: dsp@64800000 {
1977		compatible = "ti,j721s2-c71-dsp";
1978		reg = <0x00 0x64800000 0x00 0x00080000>,
1979		      <0x00 0x64e00000 0x00 0x0000c000>;
1980		reg-names = "l2sram", "l1dram";
1981		ti,sci = <&sms>;
1982		ti,sci-dev-id = <8>;
1983		ti,sci-proc-ids = <0x30 0xff>;
1984		resets = <&k3_reset 8 1>;
1985		firmware-name = "j721s2-c71_0-fw";
1986		status = "disabled";
1987	};
1988
1989	c71_1: dsp@65800000 {
1990		compatible = "ti,j721s2-c71-dsp";
1991		reg = <0x00 0x65800000 0x00 0x00080000>,
1992		      <0x00 0x65e00000 0x00 0x0000c000>;
1993		reg-names = "l2sram", "l1dram";
1994		ti,sci = <&sms>;
1995		ti,sci-dev-id = <11>;
1996		ti,sci-proc-ids = <0x31 0xff>;
1997		resets = <&k3_reset 11 1>;
1998		firmware-name = "j721s2-c71_1-fw";
1999		status = "disabled";
2000	};
2001
2002	main_esm: esm@700000 {
2003		compatible = "ti,j721e-esm";
2004		reg = <0x00 0x700000 0x00 0x1000>;
2005		ti,esm-pins = <688>, <689>;
2006		bootph-pre-ram;
2007	};
2008
2009	watchdog0: watchdog@2200000 {
2010		compatible = "ti,j7-rti-wdt";
2011		reg = <0x00 0x2200000 0x00 0x100>;
2012		clocks = <&k3_clks 286 1>;
2013		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
2014		assigned-clocks = <&k3_clks 286 1>;
2015		assigned-clock-parents = <&k3_clks 286 5>;
2016	};
2017
2018	watchdog1: watchdog@2210000 {
2019		compatible = "ti,j7-rti-wdt";
2020		reg = <0x00 0x2210000 0x00 0x100>;
2021		clocks = <&k3_clks 287 1>;
2022		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
2023		assigned-clocks = <&k3_clks 287 1>;
2024		assigned-clock-parents = <&k3_clks 287 5>;
2025	};
2026
2027	/*
2028	 * The following RTI instances are coupled with MCU R5Fs, c7x and
2029	 * GPU so keeping them reserved as these will be used by their
2030	 * respective firmware
2031	 */
2032	watchdog2: watchdog@22f0000 {
2033		compatible = "ti,j7-rti-wdt";
2034		reg = <0x00 0x22f0000 0x00 0x100>;
2035		clocks = <&k3_clks 290 1>;
2036		power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
2037		assigned-clocks = <&k3_clks 290 1>;
2038		assigned-clock-parents = <&k3_clks 290 5>;
2039		/* reserved for GPU */
2040		status = "reserved";
2041	};
2042
2043	watchdog3: watchdog@2300000 {
2044		compatible = "ti,j7-rti-wdt";
2045		reg = <0x00 0x2300000 0x00 0x100>;
2046		clocks = <&k3_clks 288 1>;
2047		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
2048		assigned-clocks = <&k3_clks 288 1>;
2049		assigned-clock-parents = <&k3_clks 288 5>;
2050		/* reserved for C7X_0 */
2051		status = "reserved";
2052	};
2053
2054	watchdog4: watchdog@2310000 {
2055		compatible = "ti,j7-rti-wdt";
2056		reg = <0x00 0x2310000 0x00 0x100>;
2057		clocks = <&k3_clks 289 1>;
2058		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
2059		assigned-clocks = <&k3_clks 289 1>;
2060		assigned-clock-parents = <&k3_clks 289 5>;
2061		/* reserved for C7X_1 */
2062		status = "reserved";
2063	};
2064
2065	watchdog5: watchdog@23c0000 {
2066		compatible = "ti,j7-rti-wdt";
2067		reg = <0x00 0x23c0000 0x00 0x100>;
2068		clocks = <&k3_clks 291 1>;
2069		power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
2070		assigned-clocks = <&k3_clks 291 1>;
2071		assigned-clock-parents = <&k3_clks 291 5>;
2072		/* reserved for MAIN_R5F0_0 */
2073		status = "reserved";
2074	};
2075
2076	watchdog6: watchdog@23d0000 {
2077		compatible = "ti,j7-rti-wdt";
2078		reg = <0x00 0x23d0000 0x00 0x100>;
2079		clocks = <&k3_clks 292 1>;
2080		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
2081		assigned-clocks = <&k3_clks 292 1>;
2082		assigned-clock-parents = <&k3_clks 292 5>;
2083		/* reserved for MAIN_R5F0_1 */
2084		status = "reserved";
2085	};
2086
2087	watchdog7: watchdog@23e0000 {
2088		compatible = "ti,j7-rti-wdt";
2089		reg = <0x00 0x23e0000 0x00 0x100>;
2090		clocks = <&k3_clks 293 1>;
2091		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
2092		assigned-clocks = <&k3_clks 293 1>;
2093		assigned-clock-parents = <&k3_clks 293 5>;
2094		/* reserved for MAIN_R5F1_0 */
2095		status = "reserved";
2096	};
2097
2098	watchdog8: watchdog@23f0000 {
2099		compatible = "ti,j7-rti-wdt";
2100		reg = <0x00 0x23f0000 0x00 0x100>;
2101		clocks = <&k3_clks 294 1>;
2102		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
2103		assigned-clocks = <&k3_clks 294 1>;
2104		assigned-clock-parents = <&k3_clks 294 5>;
2105		/* reserved for MAIN_R5F1_1 */
2106		status = "reserved";
2107	};
2108
2109	gpu: gpu@4e20000000 {
2110		compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
2111		reg = <0x4e 0x20000000 0x00 0x80000>;
2112		clocks = <&k3_clks 130 1>;
2113		clock-names = "core";
2114		assigned-clocks = <&k3_clks 130 1>;
2115		assigned-clock-rates = <800000000>;
2116		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
2117		power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
2118				<&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
2119		power-domain-names = "a", "b";
2120		dma-coherent;
2121	};
2122
2123	mcasp0: mcasp@2b00000 {
2124		compatible = "ti,am33xx-mcasp-audio";
2125		reg = <0x00 0x02b00000 0x00 0x2000>,
2126		      <0x00 0x02b08000 0x00 0x1000>;
2127		reg-names = "mpu","dat";
2128		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
2129			     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
2130		interrupt-names = "tx", "rx";
2131		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
2132		dma-names = "tx", "rx";
2133		clocks = <&k3_clks 209 0>;
2134		clock-names = "fck";
2135		assigned-clocks = <&k3_clks 209 0>;
2136		assigned-clock-parents = <&k3_clks 209 1>;
2137		power-domains = <&k3_pds 209 TI_SCI_PD_EXCLUSIVE>;
2138		status = "disabled";
2139	};
2140
2141	mcasp1: mcasp@2b10000 {
2142		compatible = "ti,am33xx-mcasp-audio";
2143		reg = <0x00 0x02b10000 0x00 0x2000>,
2144		      <0x00 0x02b18000 0x00 0x1000>;
2145		reg-names = "mpu","dat";
2146		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
2147			     <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
2148		interrupt-names = "tx", "rx";
2149		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
2150		dma-names = "tx", "rx";
2151		clocks = <&k3_clks 210 0>;
2152		clock-names = "fck";
2153		assigned-clocks = <&k3_clks 210 0>;
2154		assigned-clock-parents = <&k3_clks 210 1>;
2155		power-domains = <&k3_pds 210 TI_SCI_PD_EXCLUSIVE>;
2156		status = "disabled";
2157	};
2158
2159	mcasp2: mcasp@2b20000 {
2160		compatible = "ti,am33xx-mcasp-audio";
2161		reg = <0x00 0x02b20000 0x00 0x2000>,
2162		      <0x00 0x02b28000 0x00 0x1000>;
2163		reg-names = "mpu","dat";
2164		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
2165			     <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
2166		interrupt-names = "tx", "rx";
2167		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
2168		dma-names = "tx", "rx";
2169		clocks = <&k3_clks 211 0>;
2170		clock-names = "fck";
2171		assigned-clocks = <&k3_clks 211 0>;
2172		assigned-clock-parents = <&k3_clks 211 1>;
2173		power-domains = <&k3_pds 211 TI_SCI_PD_EXCLUSIVE>;
2174		status = "disabled";
2175	};
2176
2177	mcasp3: mcasp@2b30000 {
2178		compatible = "ti,am33xx-mcasp-audio";
2179		reg = <0x00 0x02b30000 0x00 0x2000>,
2180		      <0x00 0x02b38000 0x00 0x1000>;
2181		reg-names = "mpu","dat";
2182		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
2183			     <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
2184		interrupt-names = "tx", "rx";
2185		dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
2186		dma-names = "tx", "rx";
2187		clocks = <&k3_clks 212 0>;
2188		clock-names = "fck";
2189		assigned-clocks = <&k3_clks 212 0>;
2190		assigned-clock-parents = <&k3_clks 212 1>;
2191		power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>;
2192		status = "disabled";
2193	};
2194
2195	mcasp4: mcasp@2b40000 {
2196		compatible = "ti,am33xx-mcasp-audio";
2197		reg = <0x00 0x02b40000 0x00 0x2000>,
2198		      <0x00 0x02b48000 0x00 0x1000>;
2199		reg-names = "mpu","dat";
2200		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
2201			     <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
2202		interrupt-names = "tx", "rx";
2203		dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
2204		dma-names = "tx", "rx";
2205		clocks = <&k3_clks 213 0>;
2206		clock-names = "fck";
2207		assigned-clocks = <&k3_clks 213 0>;
2208		assigned-clock-parents = <&k3_clks 213 1>;
2209		power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
2210		status = "disabled";
2211	};
2212};