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k3-j721e-som-p0.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Product Link: https://www.ti.com/tool/J721EXSOMXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 bootph-all; 16 /* 4G RAM */ 17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 18 <0x00000008 0x80000000 0x00000000 0x80000000>; 19 }; 20 21 reserved_memory: reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 secure_ddr: optee@9e800000 { 27 reg = <0x00 0x9e800000 0x00 0x01800000>; 28 alignment = <0x1000>; 29 no-map; 30 }; 31 32 mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { 33 compatible = "shared-dma-pool"; 34 reg = <0x00 0xa0000000 0x00 0x100000>; 35 no-map; 36 }; 37 38 mcu_r5fss0_core0_memory_region: memory@a0100000 { 39 compatible = "shared-dma-pool"; 40 reg = <0x00 0xa0100000 0x00 0xf00000>; 41 no-map; 42 }; 43 }; 44}; 45 46&wkup_pmx0 { 47 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 48 pinctrl-single,pins = < 49 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 50 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 51 >; 52 bootph-all; 53 }; 54 55 pmic_irq_pins_default: pmic-irq-default-pins { 56 pinctrl-single,pins = < 57 J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ 58 >; 59 }; 60 61 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 62 pinctrl-single,pins = < 63 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ 64 J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ 65 J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ 66 J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ 67 J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ 68 J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ 69 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ 70 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ 71 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ 72 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ 73 J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ 74 >; 75 bootph-all; 76 }; 77 78 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { 79 pinctrl-single,pins = < 80 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ 81 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ 82 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ 83 J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ 84 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ 85 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ 86 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ 87 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ 88 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ 89 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ 90 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ 91 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ 92 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ 93 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ 94 >; 95 bootph-all; 96 }; 97}; 98 99&wkup_i2c0 { 100 status = "okay"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&wkup_i2c0_pins_default>; 103 clock-frequency = <400000>; 104 105 eeprom@50 { 106 /* CAV24C256WE-GT3 */ 107 compatible = "atmel,24c256"; 108 reg = <0x50>; 109 }; 110 111 tps659413: pmic@48 { 112 compatible = "ti,tps6594-q1"; 113 reg = <0x48>; 114 system-power-controller; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pmic_irq_pins_default>; 117 interrupt-parent = <&wkup_gpio0>; 118 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 119 gpio-controller; 120 #gpio-cells = <2>; 121 ti,primary-pmic; 122 buck12-supply = <&vsys_3v3>; 123 buck3-supply = <&vsys_3v3>; 124 buck4-supply = <&vsys_3v3>; 125 buck5-supply = <&vsys_3v3>; 126 ldo1-supply = <&vsys_3v3>; 127 ldo2-supply = <&vsys_3v3>; 128 ldo3-supply = <&vsys_3v3>; 129 ldo4-supply = <&vsys_3v3>; 130 131 regulators { 132 bucka12: buck12 { 133 regulator-name = "vdd_cpu_avs"; 134 regulator-min-microvolt = <600000>; 135 regulator-max-microvolt = <900000>; 136 regulator-boot-on; 137 regulator-always-on; 138 bootph-pre-ram; 139 }; 140 141 bucka3: buck3 { 142 regulator-name = "vdd_mcu_0v85"; 143 regulator-min-microvolt = <850000>; 144 regulator-max-microvolt = <850000>; 145 regulator-boot-on; 146 regulator-always-on; 147 }; 148 149 bucka4: buck4 { 150 regulator-name = "vdd_ddr_1v1"; 151 regulator-min-microvolt = <1100000>; 152 regulator-max-microvolt = <1100000>; 153 regulator-boot-on; 154 regulator-always-on; 155 }; 156 157 bucka5: buck5 { 158 regulator-name = "vdd_phyio_1v8"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <1800000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 ldoa1: ldo1 { 166 regulator-name = "vdd1_lpddr4_1v8"; 167 regulator-min-microvolt = <1800000>; 168 regulator-max-microvolt = <1800000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 ldoa2: ldo2 { 174 regulator-name = "vdd_mcuio_1v8"; 175 regulator-min-microvolt = <1800000>; 176 regulator-max-microvolt = <1800000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 ldoa3: ldo3 { 182 regulator-name = "vdda_dll_0v8"; 183 regulator-min-microvolt = <800000>; 184 regulator-max-microvolt = <800000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 ldoa4: ldo4 { 190 regulator-name = "vda_mcu_1v8"; 191 regulator-min-microvolt = <1800000>; 192 regulator-max-microvolt = <1800000>; 193 regulator-boot-on; 194 regulator-always-on; 195 }; 196 }; 197 }; 198 199 tps659411: pmic@4c { 200 compatible = "ti,tps6594-q1"; 201 reg = <0x4c>; 202 system-power-controller; 203 interrupt-parent = <&wkup_gpio0>; 204 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 buck1234-supply = <&vsys_3v3>; 208 buck5-supply = <&vsys_3v3>; 209 ldo1-supply = <&vsys_3v3>; 210 ldo2-supply = <&vsys_3v3>; 211 ldo3-supply = <&vsys_3v3>; 212 ldo4-supply = <&vsys_3v3>; 213 214 regulators { 215 buckb1234: buck1234 { 216 regulator-name = "vdd_core_0v8"; 217 regulator-min-microvolt = <800000>; 218 regulator-max-microvolt = <800000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 buckb5: buck5 { 224 regulator-name = "vdd_ram_0v85"; 225 regulator-min-microvolt = <850000>; 226 regulator-max-microvolt = <850000>; 227 regulator-boot-on; 228 regulator-always-on; 229 }; 230 231 ldob1: ldo1 { 232 regulator-name = "vdd_sd_dv"; 233 regulator-min-microvolt = <1800000>; 234 regulator-max-microvolt = <3300000>; 235 regulator-boot-on; 236 regulator-always-on; 237 }; 238 239 ldob2: ldo2 { 240 regulator-name = "vdd_usb_3v3"; 241 regulator-min-microvolt = <3300000>; 242 regulator-max-microvolt = <3300000>; 243 regulator-boot-on; 244 regulator-always-on; 245 }; 246 247 ldob3: ldo3 { 248 regulator-name = "vdd_io_1v8"; 249 regulator-min-microvolt = <1800000>; 250 regulator-max-microvolt = <1800000>; 251 regulator-boot-on; 252 regulator-always-on; 253 }; 254 255 ldob4: ldo4 { 256 regulator-name = "vda_pll_1v8"; 257 regulator-min-microvolt = <1800000>; 258 regulator-max-microvolt = <1800000>; 259 regulator-boot-on; 260 regulator-always-on; 261 }; 262 }; 263 }; 264}; 265 266&ospi0 { 267 status = "okay"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 270 271 flash@0 { 272 compatible = "jedec,spi-nor"; 273 reg = <0x0>; 274 spi-tx-bus-width = <8>; 275 spi-rx-bus-width = <8>; 276 spi-max-frequency = <25000000>; 277 cdns,tshsl-ns = <60>; 278 cdns,tsd2d-ns = <60>; 279 cdns,tchsh-ns = <60>; 280 cdns,tslch-ns = <60>; 281 cdns,read-delay = <0>; 282 283 partitions { 284 compatible = "fixed-partitions"; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 288 partition@0 { 289 label = "ospi.tiboot3"; 290 reg = <0x0 0x80000>; 291 }; 292 293 partition@80000 { 294 label = "ospi.tispl"; 295 reg = <0x80000 0x200000>; 296 }; 297 298 partition@280000 { 299 label = "ospi.u-boot"; 300 reg = <0x280000 0x400000>; 301 }; 302 303 partition@680000 { 304 label = "ospi.env"; 305 reg = <0x680000 0x20000>; 306 }; 307 308 partition@6a0000 { 309 label = "ospi.env.backup"; 310 reg = <0x6a0000 0x20000>; 311 }; 312 313 partition@6c0000 { 314 label = "ospi.sysfw"; 315 reg = <0x6c0000 0x100000>; 316 }; 317 318 partition@800000 { 319 label = "ospi.rootfs"; 320 reg = <0x800000 0x37c0000>; 321 }; 322 323 partition@3fe0000 { 324 label = "ospi.phypattern"; 325 reg = <0x3fe0000 0x20000>; 326 bootph-all; 327 }; 328 }; 329 }; 330}; 331 332&hbmc { 333 /* OSPI and HBMC are muxed inside FSS, Bootloader will enable 334 * appropriate node based on board detection 335 */ 336 status = "disabled"; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 339 ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ 340 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ 341 342 flash@0,0 { 343 compatible = "cypress,hyperflash", "cfi-flash"; 344 reg = <0x00 0x00 0x4000000>; 345 bootph-all; 346 347 partitions { 348 compatible = "fixed-partitions"; 349 #address-cells = <1>; 350 #size-cells = <1>; 351 352 partition@0 { 353 label = "hbmc.tiboot3"; 354 reg = <0x0 0x80000>; 355 }; 356 357 partition@80000 { 358 label = "hbmc.tispl"; 359 reg = <0x80000 0x200000>; 360 }; 361 362 partition@280000 { 363 label = "hbmc.u-boot"; 364 reg = <0x280000 0x400000>; 365 }; 366 367 partition@680000 { 368 label = "hbmc.env"; 369 reg = <0x680000 0x40000>; 370 }; 371 372 partition@6c0000 { 373 label = "hbmc.sysfw"; 374 reg = <0x6c0000 0x100000>; 375 }; 376 377 partition@800000 { 378 label = "hbmc.rootfs"; 379 reg = <0x800000 0x3800000>; 380 }; 381 }; 382 }; 383}; 384 385#include "k3-j721e-ti-ipc-firmware.dtsi"
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