k3-j721e-evm-quad-port-eth-exp.dtso

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/**
  3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
  4 * J721E board.
  5 *
  6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  7 */
  8
  9/dts-v1/;
 10/plugin/;
 11
 12#include <dt-bindings/gpio/gpio.h>
 13#include <dt-bindings/phy/phy.h>
 14#include <dt-bindings/phy/phy-cadence.h>
 15
 16#include "k3-pinctrl.h"
 17#include "k3-serdes.h"
 18
 19&{/} {
 20	aliases {
 21		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
 22		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
 23		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
 24		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
 25	};
 26};
 27
 28&cpsw0 {
 29	status = "okay";
 30};
 31
 32&cpsw0_port1 {
 33	status = "okay";
 34	phy-handle = <&cpsw9g_phy0>;
 35	phy-mode = "qsgmii";
 36	mac-address = [00 00 00 00 00 00];
 37	phys = <&cpsw0_phy_gmii_sel 1>;
 38};
 39
 40&cpsw0_port2 {
 41	status = "okay";
 42	phy-handle = <&cpsw9g_phy1>;
 43	phy-mode = "qsgmii";
 44	mac-address = [00 00 00 00 00 00];
 45	phys = <&cpsw0_phy_gmii_sel 2>;
 46};
 47
 48&cpsw0_port3 {
 49	status = "okay";
 50	phy-handle = <&cpsw9g_phy2>;
 51	phy-mode = "qsgmii";
 52	mac-address = [00 00 00 00 00 00];
 53	phys = <&cpsw0_phy_gmii_sel 3>;
 54};
 55
 56&cpsw0_port4 {
 57	status = "okay";
 58	phy-handle = <&cpsw9g_phy3>;
 59	phy-mode = "qsgmii";
 60	mac-address = [00 00 00 00 00 00];
 61	phys = <&cpsw0_phy_gmii_sel 4>;
 62};
 63
 64&cpsw9g_mdio {
 65	status = "okay";
 66	pinctrl-names = "default";
 67	pinctrl-0 = <&mdio0_pins_default>;
 68	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
 69	reset-post-delay-us = <120000>;
 70	#address-cells = <1>;
 71	#size-cells = <0>;
 72
 73	cpsw9g_phy0: ethernet-phy@17 {
 74		reg = <17>;
 75	};
 76	cpsw9g_phy1: ethernet-phy@16 {
 77		reg = <16>;
 78	};
 79	cpsw9g_phy2: ethernet-phy@18 {
 80		reg = <18>;
 81	};
 82	cpsw9g_phy3: ethernet-phy@19 {
 83		reg = <19>;
 84	};
 85};
 86
 87&exp2 {
 88	qsgmii-line-hog {
 89		gpio-hog;
 90		gpios = <16 GPIO_ACTIVE_HIGH>;
 91		output-low;
 92		line-name = "qsgmii-pwrdn-line";
 93	};
 94};
 95
 96&main_pmx0 {
 97	mdio0_pins_default: mdio0-default-pins {
 98		pinctrl-single,pins = <
 99			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
100			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
101		>;
102	};
103};
104
105&serdes_ln_ctrl {
106	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
107		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
108		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
109		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
110		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
111		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
112};
113
114&serdes_wiz0 {
115	status = "okay";
116};
117
118&serdes0 {
119	status = "okay";
120
121	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
122	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
123	#address-cells = <1>;
124	#size-cells = <0>;
125
126	serdes0_qsgmii_link: phy@1 {
127		reg = <1>;
128		cdns,num-lanes = <1>;
129		#phy-cells = <0>;
130		cdns,phy-type = <PHY_TYPE_QSGMII>;
131		resets = <&serdes_wiz0 2>;
132	};
133};