k3-j7200.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for J7200 SoC Family
  4 *
  5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/interrupt-controller/irq.h>
  9#include <dt-bindings/interrupt-controller/arm-gic.h>
 10#include <dt-bindings/soc/ti,sci_pm_domain.h>
 11
 12#include "k3-pinctrl.h"
 13
 14/ {
 15	model = "Texas Instruments K3 J7200 SoC";
 16	compatible = "ti,j7200";
 17	interrupt-parent = <&gic500>;
 18	#address-cells = <2>;
 19	#size-cells = <2>;
 20
 21	chosen { };
 22
 23	cpus {
 24		#address-cells = <1>;
 25		#size-cells = <0>;
 26		cpu-map {
 27			cluster0: cluster0 {
 28				core0 {
 29					cpu = <&cpu0>;
 30				};
 31
 32				core1 {
 33					cpu = <&cpu1>;
 34				};
 35			};
 36
 37		};
 38
 39		cpu0: cpu@0 {
 40			compatible = "arm,cortex-a72";
 41			reg = <0x000>;
 42			device_type = "cpu";
 43			enable-method = "psci";
 44			i-cache-size = <0xc000>;
 45			i-cache-line-size = <64>;
 46			i-cache-sets = <256>;
 47			d-cache-size = <0x8000>;
 48			d-cache-line-size = <64>;
 49			d-cache-sets = <256>;
 50			next-level-cache = <&L2_0>;
 51		};
 52
 53		cpu1: cpu@1 {
 54			compatible = "arm,cortex-a72";
 55			reg = <0x001>;
 56			device_type = "cpu";
 57			enable-method = "psci";
 58			i-cache-size = <0xc000>;
 59			i-cache-line-size = <64>;
 60			i-cache-sets = <256>;
 61			d-cache-size = <0x8000>;
 62			d-cache-line-size = <64>;
 63			d-cache-sets = <256>;
 64			next-level-cache = <&L2_0>;
 65		};
 66	};
 67
 68	L2_0: l2-cache0 {
 69		compatible = "cache";
 70		cache-level = <2>;
 71		cache-unified;
 72		cache-size = <0x100000>;
 73		cache-line-size = <64>;
 74		cache-sets = <1024>;
 75		next-level-cache = <&msmc_l3>;
 76	};
 77
 78	msmc_l3: l3-cache0 {
 79		compatible = "cache";
 80		cache-level = <3>;
 81		cache-unified;
 82	};
 83
 84	firmware {
 85		optee {
 86			compatible = "linaro,optee-tz";
 87			method = "smc";
 88		};
 89
 90		psci: psci {
 91			compatible = "arm,psci-1.0";
 92			method = "smc";
 93		};
 94	};
 95
 96	a72_timer0: timer-cl0-cpu0 {
 97		compatible = "arm,armv8-timer";
 98		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 99			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
100			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
101			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
102	};
103
104	pmu: pmu {
105		compatible = "arm,cortex-a72-pmu";
106		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
107	};
108
109	cbass_main: bus@100000 {
110		compatible = "simple-bus";
111		#address-cells = <2>;
112		#size-cells = <2>;
113		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
114			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
115			 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
116			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
117			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
118			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
119			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
120			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
121			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
122			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
123
124			 /* MCUSS_WKUP Range */
125			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
126			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
127			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
128			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
129			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
130			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
131			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
132			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
133			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
134			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
135			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
136			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
137			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
138
139		cbass_mcu_wakeup: bus@28380000 {
140			compatible = "simple-bus";
141			#address-cells = <2>;
142			#size-cells = <2>;
143			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
144				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
145				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
146				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
147				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
148				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
149				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
150				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
151				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
152				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
153				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
154				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
155				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
156		};
157	};
158
159	#include "k3-j7200-thermal.dtsi"
160};
161
162/* Now include the peripherals for each bus segments */
163#include "k3-j7200-main.dtsi"
164#include "k3-j7200-mcu-wakeup.dtsi"