k3-j7200-som-p0.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  4 */
  5
  6/dts-v1/;
  7
  8#include <dt-bindings/gpio/gpio.h>
  9
 10#include "k3-j7200.dtsi"
 11
 12/ {
 13	memory@80000000 {
 14		device_type = "memory";
 15		bootph-all;
 16		/* 4G RAM */
 17		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
 18		      <0x00000008 0x80000000 0x00000000 0x80000000>;
 19	};
 20
 21	reserved_memory: reserved-memory {
 22		#address-cells = <2>;
 23		#size-cells = <2>;
 24		ranges;
 25
 26		secure_ddr: optee@9e800000 {
 27			reg = <0x00 0x9e800000 0x00 0x01800000>;
 28			alignment = <0x1000>;
 29			no-map;
 30		};
 31
 32		mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
 33			compatible = "shared-dma-pool";
 34			reg = <0x00 0xa0000000 0x00 0x100000>;
 35			no-map;
 36		};
 37
 38		mcu_r5fss0_core0_memory_region: memory@a0100000 {
 39			compatible = "shared-dma-pool";
 40			reg = <0x00 0xa0100000 0x00 0xf00000>;
 41			no-map;
 42		};
 43	};
 44
 45	mux0: mux-controller-0 {
 46		compatible = "gpio-mux";
 47		#mux-state-cells = <1>;
 48		mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
 49	};
 50
 51	mux1: mux-controller-1 {
 52		compatible = "gpio-mux";
 53		#mux-state-cells = <1>;
 54		mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
 55	};
 56
 57	transceiver0: can-phy0 {
 58		/* standby pin has been grounded by default */
 59		compatible = "ti,tcan1042";
 60		#phy-cells = <0>;
 61		max-bitrate = <5000000>;
 62	};
 63};
 64
 65&wkup_pmx0 {
 66	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
 67		pinctrl-single,pins = <
 68			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
 69			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
 70			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
 71			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
 72			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
 73			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
 74			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
 75			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
 76			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
 77			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
 78			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
 79			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
 80			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
 81		>;
 82		bootph-all;
 83	};
 84
 85	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 86		pinctrl-single,pins = <
 87			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
 88			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
 89			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
 90			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
 91			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
 92			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
 93			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
 94			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
 95			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
 96			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
 97			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
 98		>;
 99		bootph-all;
100	};
101};
102
103&wkup_pmx2 {
104	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
105			pinctrl-single,pins = <
106			J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
107			J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
108		>;
109		bootph-all;
110	};
111};
112
113&wkup_pmx3 {
114	pmic_irq_pins_default: pmic-irq-default-pins {
115		pinctrl-single,pins = <
116			J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */
117		>;
118	};
119};
120
121&main_pmx0 {
122	main_i2c0_pins_default: main-i2c0-default-pins {
123		pinctrl-single,pins = <
124			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
125			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
126		>;
127	};
128
129	main_mcan0_pins_default: main-mcan0-default-pins {
130		pinctrl-single,pins = <
131			J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */
132			J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */
133		>;
134	};
135};
136
137&hbmc {
138	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
139	 * appropriate node based on board detection
140	 */
141	status = "disabled";
142	pinctrl-names = "default";
143	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
144	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
145		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
146
147	flash@0,0 {
148		compatible = "cypress,hyperflash", "cfi-flash";
149		reg = <0x00 0x00 0x4000000>;
150		bootph-all;
151
152		partitions {
153			compatible = "fixed-partitions";
154			#address-cells = <1>;
155			#size-cells = <1>;
156
157			partition@0 {
158				label = "hbmc.tiboot3";
159				reg = <0x0 0x100000>;
160			};
161
162			partition@100000 {
163				label = "hbmc.tispl";
164				reg = <0x100000 0x200000>;
165			};
166
167			partition@300000 {
168				label = "hbmc.u-boot";
169				reg = <0x300000 0x400000>;
170			};
171
172			partition@700000 {
173				label = "hbmc.env";
174				reg = <0x700000 0x40000>;
175			};
176
177			partition@800000 {
178				label = "hbmc.rootfs";
179				reg = <0x800000 0x3800000>;
180			};
181		};
182	};
183};
184
185&main_i2c0 {
186	pinctrl-names = "default";
187	pinctrl-0 = <&main_i2c0_pins_default>;
188	clock-frequency = <400000>;
189
190	exp_som: gpio@21 {
191		compatible = "ti,tca6408";
192		reg = <0x21>;
193		gpio-controller;
194		#gpio-cells = <2>;
195		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
196				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
197				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
198				  "GPIO_LIN_EN", "CAN_STB";
199	};
200};
201
202&wkup_i2c0 {
203	status = "okay";
204	pinctrl-names = "default";
205	pinctrl-0 = <&wkup_i2c0_pins_default>;
206	clock-frequency = <400000>;
207
208	eeprom@50 {
209		compatible = "atmel,24c256";
210		reg = <0x50>;
211	};
212
213	tps659414: pmic@48 {
214		compatible = "ti,tps6594-q1";
215		reg = <0x48>;
216		system-power-controller;
217		pinctrl-names = "default";
218		pinctrl-0 = <&pmic_irq_pins_default>;
219		interrupt-parent = <&wkup_gpio0>;
220		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
221		gpio-controller;
222		#gpio-cells = <2>;
223		ti,primary-pmic;
224		buck1-supply = <&vsys_3v3>;
225		buck2-supply = <&vsys_3v3>;
226		buck3-supply = <&vsys_3v3>;
227		buck4-supply = <&vsys_3v3>;
228		buck5-supply = <&vsys_3v3>;
229		ldo1-supply = <&vsys_3v3>;
230		ldo2-supply = <&vsys_3v3>;
231		ldo3-supply = <&vsys_3v3>;
232		ldo4-supply = <&vsys_3v3>;
233
234		regulators {
235			bucka1: buck1 {
236				regulator-name = "vda_mcu_1v8";
237				regulator-min-microvolt = <1800000>;
238				regulator-max-microvolt = <1800000>;
239				regulator-boot-on;
240				regulator-always-on;
241				bootph-all;
242			};
243
244			bucka2: buck2 {
245				regulator-name = "vdd_mcuio_1v8";
246				regulator-min-microvolt = <1800000>;
247				regulator-max-microvolt = <1800000>;
248				regulator-boot-on;
249				regulator-always-on;
250			};
251
252			bucka3: buck3 {
253				regulator-name = "vdd_mcu_0v85";
254				regulator-min-microvolt = <850000>;
255				regulator-max-microvolt = <850000>;
256				regulator-boot-on;
257				regulator-always-on;
258			};
259
260			bucka4: buck4 {
261				regulator-name = "vdd_ddr_1v1";
262				regulator-min-microvolt = <1100000>;
263				regulator-max-microvolt = <1100000>;
264				regulator-boot-on;
265				regulator-always-on;
266			};
267
268			bucka5: buck5 {
269				regulator-name = "vdd_phyio_1v8";
270				regulator-min-microvolt = <1800000>;
271				regulator-max-microvolt = <1800000>;
272				regulator-boot-on;
273				regulator-always-on;
274			};
275
276			ldoa1: ldo1 {
277				regulator-name = "vdd1_lpddr4_1v8";
278				regulator-min-microvolt = <1800000>;
279				regulator-max-microvolt = <1800000>;
280				regulator-boot-on;
281				regulator-always-on;
282			};
283
284			ldoa2: ldo2 {
285				regulator-name = "vda_dll_0v8";
286				regulator-min-microvolt = <800000>;
287				regulator-max-microvolt = <800000>;
288				regulator-boot-on;
289				regulator-always-on;
290			};
291
292			ldoa3: ldo3 {
293				regulator-name = "vdd_wk_0v8";
294				regulator-min-microvolt = <800000>;
295				regulator-max-microvolt = <800000>;
296				regulator-boot-on;
297				regulator-always-on;
298			};
299
300			ldoa4: ldo4 {
301				regulator-name = "vda_pll_1v8";
302				regulator-min-microvolt = <1800000>;
303				regulator-max-microvolt = <1800000>;
304				regulator-boot-on;
305				regulator-always-on;
306			};
307		};
308	};
309
310	lp876441: pmic@4c {
311		compatible = "ti,lp8764-q1";
312		reg = <0x4c>;
313		system-power-controller;
314		interrupt-parent = <&wkup_gpio0>;
315		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
316		gpio-controller;
317		#gpio-cells = <2>;
318		buck1-supply = <&vsys_3v3>;
319		buck2-supply = <&vsys_3v3>;
320		buck3-supply = <&vsys_3v3>;
321		buck4-supply = <&vsys_3v3>;
322
323		regulators: regulators {
324			buckb1: buck1 {
325				regulator-name = "vdd_cpu_avs";
326				regulator-min-microvolt = <600000>;
327				regulator-max-microvolt = <900000>;
328				regulator-always-on;
329				regulator-boot-on;
330				bootph-pre-ram;
331			};
332
333			buckb2: buck2 {
334				regulator-name = "vdd_ram_0v85";
335				regulator-min-microvolt = <850000>;
336				regulator-max-microvolt = <850000>;
337				regulator-boot-on;
338				regulator-always-on;
339			};
340
341			buckb3: buck3 {
342				regulator-name = "vdd_core_0v85";
343				regulator-min-microvolt = <850000>;
344				regulator-max-microvolt = <850000>;
345				regulator-boot-on;
346				regulator-always-on;
347			};
348
349			buckb4: buck4 {
350				regulator-name = "vdd_io_1v8";
351				regulator-min-microvolt = <1800000>;
352				regulator-max-microvolt = <1800000>;
353				regulator-boot-on;
354				regulator-always-on;
355			};
356		};
357	};
358};
359
360&ospi0 {
361	status = "okay";
362	pinctrl-names = "default";
363	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
364
365	flash@0 {
366		compatible = "jedec,spi-nor";
367		reg = <0x0>;
368		spi-tx-bus-width = <8>;
369		spi-rx-bus-width = <8>;
370		spi-max-frequency = <25000000>;
371		cdns,tshsl-ns = <60>;
372		cdns,tsd2d-ns = <60>;
373		cdns,tchsh-ns = <60>;
374		cdns,tslch-ns = <60>;
375		cdns,read-delay = <4>;
376
377		partitions {
378			compatible = "fixed-partitions";
379			#address-cells = <1>;
380			#size-cells = <1>;
381
382			partition@0 {
383				label = "ospi.tiboot3";
384				reg = <0x0 0x100000>;
385			};
386
387			partition@100000 {
388				label = "ospi.tispl";
389				reg = <0x100000 0x200000>;
390			};
391
392			partition@300000 {
393				label = "ospi.u-boot";
394				reg = <0x300000 0x400000>;
395			};
396
397			partition@700000 {
398				label = "ospi.env";
399				reg = <0x700000 0x40000>;
400			};
401
402			partition@740000 {
403				label = "ospi.env.backup";
404				reg = <0x740000 0x40000>;
405			};
406
407			partition@800000 {
408				label = "ospi.rootfs";
409				reg = <0x800000 0x37c0000>;
410			};
411
412			partition@3fc0000 {
413				label = "ospi.phypattern";
414				reg = <0x3fc0000 0x40000>;
415				bootph-all;
416			};
417		};
418	};
419};
420
421&main_mcan0 {
422	status = "okay";
423	pinctrl-0 = <&main_mcan0_pins_default>;
424	pinctrl-names = "default";
425	phys = <&transceiver0>;
426};
427
428#include "k3-j7200-ti-ipc-firmware.dtsi"