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k3-j7200-mcu-wakeup.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 bootph-all; 25 }; 26 27 k3_clks: clock-controller { 28 compatible = "ti,k2g-sci-clk"; 29 #clock-cells = <2>; 30 bootph-all; 31 }; 32 33 k3_reset: reset-controller { 34 compatible = "ti,sci-reset"; 35 #reset-cells = <2>; 36 bootph-all; 37 }; 38 }; 39 40 mcu_timer0: timer@40400000 { 41 status = "reserved"; 42 compatible = "ti,am654-timer"; 43 reg = <0x00 0x40400000 0x00 0x400>; 44 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&k3_clks 35 1>; 46 clock-names = "fck"; 47 assigned-clocks = <&k3_clks 35 1>; 48 assigned-clock-parents = <&k3_clks 35 2>; 49 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 50 bootph-pre-ram; 51 ti,timer-pwm; 52 }; 53 54 mcu_timer1: timer@40410000 { 55 status = "reserved"; 56 compatible = "ti,am654-timer"; 57 reg = <0x00 0x40410000 0x00 0x400>; 58 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 59 clocks = <&k3_clks 71 1>; 60 clock-names = "fck"; 61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; 62 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; 63 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 64 ti,timer-pwm; 65 }; 66 67 mcu_timer2: timer@40420000 { 68 status = "reserved"; 69 compatible = "ti,am654-timer"; 70 reg = <0x00 0x40420000 0x00 0x400>; 71 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 72 clocks = <&k3_clks 72 1>; 73 clock-names = "fck"; 74 assigned-clocks = <&k3_clks 72 1>; 75 assigned-clock-parents = <&k3_clks 72 2>; 76 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 77 ti,timer-pwm; 78 }; 79 80 mcu_timer3: timer@40430000 { 81 status = "reserved"; 82 compatible = "ti,am654-timer"; 83 reg = <0x00 0x40430000 0x00 0x400>; 84 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 85 clocks = <&k3_clks 73 1>; 86 clock-names = "fck"; 87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; 88 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; 89 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 90 ti,timer-pwm; 91 }; 92 93 mcu_timer4: timer@40440000 { 94 status = "reserved"; 95 compatible = "ti,am654-timer"; 96 reg = <0x00 0x40440000 0x00 0x400>; 97 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&k3_clks 74 1>; 99 clock-names = "fck"; 100 assigned-clocks = <&k3_clks 74 1>; 101 assigned-clock-parents = <&k3_clks 74 2>; 102 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 103 ti,timer-pwm; 104 }; 105 106 mcu_timer5: timer@40450000 { 107 status = "reserved"; 108 compatible = "ti,am654-timer"; 109 reg = <0x00 0x40450000 0x00 0x400>; 110 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&k3_clks 75 1>; 112 clock-names = "fck"; 113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; 114 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; 115 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 116 ti,timer-pwm; 117 }; 118 119 mcu_timer6: timer@40460000 { 120 status = "reserved"; 121 compatible = "ti,am654-timer"; 122 reg = <0x00 0x40460000 0x00 0x400>; 123 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&k3_clks 76 1>; 125 clock-names = "fck"; 126 assigned-clocks = <&k3_clks 76 1>; 127 assigned-clock-parents = <&k3_clks 76 2>; 128 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 129 ti,timer-pwm; 130 }; 131 132 mcu_timer7: timer@40470000 { 133 status = "reserved"; 134 compatible = "ti,am654-timer"; 135 reg = <0x00 0x40470000 0x00 0x400>; 136 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&k3_clks 77 1>; 138 clock-names = "fck"; 139 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; 140 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; 141 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 142 ti,timer-pwm; 143 }; 144 145 mcu_timer8: timer@40480000 { 146 status = "reserved"; 147 compatible = "ti,am654-timer"; 148 reg = <0x00 0x40480000 0x00 0x400>; 149 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&k3_clks 78 1>; 151 clock-names = "fck"; 152 assigned-clocks = <&k3_clks 78 1>; 153 assigned-clock-parents = <&k3_clks 78 2>; 154 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 155 ti,timer-pwm; 156 }; 157 158 mcu_timer9: timer@40490000 { 159 status = "reserved"; 160 compatible = "ti,am654-timer"; 161 reg = <0x00 0x40490000 0x00 0x400>; 162 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&k3_clks 79 1>; 164 clock-names = "fck"; 165 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; 166 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; 167 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 168 ti,timer-pwm; 169 }; 170 171 mcu_conf: bus@40f00000 { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0x0 0x0 0x40f00000 0x20000>; 176 177 cpsw_mac_syscon: ethernet-mac-syscon@200 { 178 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 179 reg = <0x200 0x8>; 180 }; 181 182 phy_gmii_sel: phy@4040 { 183 compatible = "ti,am654-phy-gmii-sel"; 184 reg = <0x4040 0x4>; 185 #phy-cells = <1>; 186 }; 187 188 spi1_linkdis: mux-controller@4060 { 189 compatible = "reg-mux"; 190 reg = <0x4060 0x4>; 191 #mux-control-cells = <1>; 192 mux-reg-masks = <0x0 0x1>; 193 }; 194 }; 195 196 wkup_conf: bus@43000000 { 197 compatible = "simple-bus"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0x0 0x00 0x43000000 0x20000>; 201 202 chipid: chipid@14 { 203 compatible = "ti,am654-chipid"; 204 reg = <0x14 0x4>; 205 bootph-all; 206 }; 207 }; 208 209 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 210 mcu_timerio_input: pinctrl@40f04200 { 211 compatible = "ti,j7200-padconf", "pinctrl-single"; 212 reg = <0x0 0x40f04200 0x0 0x28>; 213 #pinctrl-cells = <1>; 214 pinctrl-single,register-width = <32>; 215 pinctrl-single,function-mask = <0x0000000F>; 216 status = "reserved"; 217 }; 218 219 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 220 mcu_timerio_output: pinctrl@40f04280 { 221 compatible = "ti,j7200-padconf", "pinctrl-single"; 222 reg = <0x0 0x40f04280 0x0 0x28>; 223 #pinctrl-cells = <1>; 224 pinctrl-single,register-width = <32>; 225 pinctrl-single,function-mask = <0x0000000F>; 226 status = "reserved"; 227 }; 228 229 wkup_pmx0: pinctrl@4301c000 { 230 compatible = "ti,j7200-padconf", "pinctrl-single"; 231 /* Proxy 0 addressing */ 232 reg = <0x00 0x4301c000 0x00 0x34>; 233 #pinctrl-cells = <1>; 234 pinctrl-single,register-width = <32>; 235 pinctrl-single,function-mask = <0xffffffff>; 236 }; 237 238 wkup_pmx1: pinctrl@4301c038 { 239 compatible = "ti,j7200-padconf", "pinctrl-single"; 240 /* Proxy 0 addressing */ 241 reg = <0x00 0x4301c038 0x00 0x8>; 242 #pinctrl-cells = <1>; 243 pinctrl-single,register-width = <32>; 244 pinctrl-single,function-mask = <0xffffffff>; 245 }; 246 247 wkup_pmx2: pinctrl@4301c068 { 248 compatible = "ti,j7200-padconf", "pinctrl-single"; 249 /* Proxy 0 addressing */ 250 reg = <0x00 0x4301c068 0x00 0xec>; 251 #pinctrl-cells = <1>; 252 pinctrl-single,register-width = <32>; 253 pinctrl-single,function-mask = <0xffffffff>; 254 }; 255 256 wkup_pmx3: pinctrl@4301c174 { 257 compatible = "ti,j7200-padconf", "pinctrl-single"; 258 /* Proxy 0 addressing */ 259 reg = <0x00 0x4301c174 0x00 0x20>; 260 #pinctrl-cells = <1>; 261 pinctrl-single,register-width = <32>; 262 pinctrl-single,function-mask = <0xffffffff>; 263 }; 264 265 mcu_ram: sram@41c00000 { 266 compatible = "mmio-sram"; 267 reg = <0x00 0x41c00000 0x00 0x100000>; 268 ranges = <0x00 0x00 0x41c00000 0x100000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 }; 272 273 wkup_uart0: serial@42300000 { 274 compatible = "ti,j721e-uart", "ti,am654-uart"; 275 reg = <0x00 0x42300000 0x00 0x100>; 276 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 277 clock-frequency = <48000000>; 278 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 279 clocks = <&k3_clks 287 2>; 280 clock-names = "fclk"; 281 status = "disabled"; 282 }; 283 284 mcu_uart0: serial@40a00000 { 285 compatible = "ti,j721e-uart", "ti,am654-uart"; 286 reg = <0x00 0x40a00000 0x00 0x100>; 287 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 288 clock-frequency = <96000000>; 289 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 290 clocks = <&k3_clks 149 2>; 291 clock-names = "fclk"; 292 status = "disabled"; 293 }; 294 295 wkup_gpio_intr: interrupt-controller@42200000 { 296 compatible = "ti,sci-intr"; 297 reg = <0x00 0x42200000 0x00 0x400>; 298 ti,intr-trigger-type = <1>; 299 interrupt-controller; 300 interrupt-parent = <&gic500>; 301 #interrupt-cells = <1>; 302 ti,sci = <&dmsc>; 303 ti,sci-dev-id = <137>; 304 ti,interrupt-ranges = <16 960 16>; 305 }; 306 307 wkup_gpio0: gpio@42110000 { 308 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 309 reg = <0x00 0x42110000 0x00 0x100>; 310 gpio-controller; 311 #gpio-cells = <2>; 312 interrupt-parent = <&wkup_gpio_intr>; 313 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 ti,ngpio = <85>; 317 ti,davinci-gpio-unbanked = <0>; 318 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 319 clocks = <&k3_clks 113 0>; 320 clock-names = "gpio"; 321 status = "disabled"; 322 }; 323 324 wkup_gpio1: gpio@42100000 { 325 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 326 reg = <0x00 0x42100000 0x00 0x100>; 327 gpio-controller; 328 #gpio-cells = <2>; 329 interrupt-parent = <&wkup_gpio_intr>; 330 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 ti,ngpio = <85>; 334 ti,davinci-gpio-unbanked = <0>; 335 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 114 0>; 337 clock-names = "gpio"; 338 status = "disabled"; 339 }; 340 341 mcu_navss: bus@28380000 { 342 compatible = "simple-bus"; 343 #address-cells = <2>; 344 #size-cells = <2>; 345 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 346 dma-coherent; 347 dma-ranges; 348 ti,sci-dev-id = <232>; 349 350 mcu_ringacc: ringacc@2b800000 { 351 compatible = "ti,am654-navss-ringacc"; 352 reg = <0x00 0x2b800000 0x00 0x400000>, 353 <0x00 0x2b000000 0x00 0x400000>, 354 <0x00 0x28590000 0x00 0x100>, 355 <0x00 0x2a500000 0x00 0x40000>, 356 <0x00 0x28440000 0x00 0x40000>; 357 reg-names = "rt", "fifos", "proxy_gcfg", 358 "proxy_target", "cfg"; 359 bootph-all; 360 ti,num-rings = <286>; 361 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 362 ti,sci = <&dmsc>; 363 ti,sci-dev-id = <235>; 364 msi-parent = <&main_udmass_inta>; 365 }; 366 367 mcu_udmap: dma-controller@285c0000 { 368 compatible = "ti,j721e-navss-mcu-udmap"; 369 reg = <0x00 0x285c0000 0x00 0x100>, 370 <0x00 0x2a800000 0x00 0x40000>, 371 <0x00 0x2aa00000 0x00 0x40000>, 372 <0x00 0x284a0000 0x00 0x4000>, 373 <0x00 0x284c0000 0x00 0x4000>, 374 <0x00 0x28400000 0x00 0x2000>; 375 reg-names = "gcfg", "rchanrt", "tchanrt", 376 "tchan", "rchan", "rflow"; 377 msi-parent = <&main_udmass_inta>; 378 #dma-cells = <1>; 379 bootph-all; 380 381 ti,sci = <&dmsc>; 382 ti,sci-dev-id = <236>; 383 ti,ringacc = <&mcu_ringacc>; 384 385 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 386 <0x0f>; /* TX_HCHAN */ 387 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 388 <0x0b>; /* RX_HCHAN */ 389 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 390 }; 391 }; 392 393 secure_proxy_mcu: mailbox@2a480000 { 394 compatible = "ti,am654-secure-proxy"; 395 #mbox-cells = <1>; 396 reg-names = "target_data", "rt", "scfg"; 397 reg = <0x0 0x2a480000 0x0 0x80000>, 398 <0x0 0x2a380000 0x0 0x80000>, 399 <0x0 0x2a400000 0x0 0x80000>; 400 bootph-pre-ram; 401 402 /* 403 * Marked Disabled: 404 * Node is incomplete as it is meant for bootloaders and 405 * firmware on non-MPU processors 406 */ 407 status = "disabled"; 408 }; 409 410 mcu_cpsw: ethernet@46000000 { 411 compatible = "ti,j721e-cpsw-nuss"; 412 #address-cells = <2>; 413 #size-cells = <2>; 414 reg = <0x00 0x46000000 0x00 0x200000>; 415 reg-names = "cpsw_nuss"; 416 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 417 dma-coherent; 418 clocks = <&k3_clks 18 21>; 419 clock-names = "fck"; 420 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 421 422 dmas = <&mcu_udmap 0xf000>, 423 <&mcu_udmap 0xf001>, 424 <&mcu_udmap 0xf002>, 425 <&mcu_udmap 0xf003>, 426 <&mcu_udmap 0xf004>, 427 <&mcu_udmap 0xf005>, 428 <&mcu_udmap 0xf006>, 429 <&mcu_udmap 0xf007>, 430 <&mcu_udmap 0x7000>; 431 dma-names = "tx0", "tx1", "tx2", "tx3", 432 "tx4", "tx5", "tx6", "tx7", 433 "rx"; 434 435 status = "disabled"; 436 437 ethernet-ports { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 441 cpsw_port1: port@1 { 442 reg = <1>; 443 ti,mac-only; 444 label = "port1"; 445 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 446 phys = <&phy_gmii_sel 1>; 447 }; 448 }; 449 450 davinci_mdio: mdio@f00 { 451 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 452 reg = <0x00 0xf00 0x00 0x100>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&k3_clks 18 21>; 456 clock-names = "fck"; 457 bus_freq = <1000000>; 458 }; 459 460 cpts@3d000 { 461 compatible = "ti,am65-cpts"; 462 reg = <0x00 0x3d000 0x00 0x400>; 463 clocks = <&k3_clks 18 2>; 464 clock-names = "cpts"; 465 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "cpts"; 467 ti,cpts-ext-ts-inputs = <4>; 468 ti,cpts-periodic-outputs = <2>; 469 }; 470 }; 471 472 mcu_i2c0: i2c@40b00000 { 473 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 474 reg = <0x00 0x40b00000 0x00 0x100>; 475 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 clock-names = "fck"; 479 clocks = <&k3_clks 194 1>; 480 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 481 status = "disabled"; 482 }; 483 484 mcu_i2c1: i2c@40b10000 { 485 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 486 reg = <0x00 0x40b10000 0x00 0x100>; 487 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clock-names = "fck"; 491 clocks = <&k3_clks 195 1>; 492 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 493 status = "disabled"; 494 }; 495 496 wkup_i2c0: i2c@42120000 { 497 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 498 reg = <0x00 0x42120000 0x00 0x100>; 499 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clock-names = "fck"; 503 clocks = <&k3_clks 197 1>; 504 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 505 status = "disabled"; 506 }; 507 508 mcu_spi0: spi@40300000 { 509 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 510 reg = <0x00 0x040300000 0x00 0x400>; 511 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 515 clocks = <&k3_clks 274 4>; 516 status = "disabled"; 517 }; 518 519 mcu_spi1: spi@40310000 { 520 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 521 reg = <0x00 0x040310000 0x00 0x400>; 522 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 526 clocks = <&k3_clks 275 4>; 527 status = "disabled"; 528 }; 529 530 mcu_spi2: spi@40320000 { 531 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 532 reg = <0x00 0x040320000 0x00 0x400>; 533 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 537 clocks = <&k3_clks 276 2>; 538 status = "disabled"; 539 }; 540 541 fss: bus@47000000 { 542 compatible = "simple-bus"; 543 #address-cells = <2>; 544 #size-cells = <2>; 545 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 546 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */ 547 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 548 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */ 549 550 hbmc_mux: mux-controller@47000004 { 551 compatible = "reg-mux"; 552 reg = <0x00 0x47000004 0x00 0x4>; 553 #mux-control-cells = <1>; 554 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 555 bootph-all; 556 }; 557 558 hbmc: hyperbus@47034000 { 559 compatible = "ti,am654-hbmc"; 560 reg = <0x00 0x47034000 0x00 0x100>, 561 <0x05 0x00000000 0x01 0x0000000>; 562 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 563 clocks = <&k3_clks 102 0>; 564 assigned-clocks = <&k3_clks 102 5>; 565 assigned-clock-rates = <333333333>; 566 #address-cells = <2>; 567 #size-cells = <1>; 568 mux-controls = <&hbmc_mux 0>; 569 }; 570 571 ospi0: spi@47040000 { 572 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 573 reg = <0x0 0x47040000 0x0 0x100>, 574 <0x5 0x00000000 0x1 0x0000000>; 575 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 576 cdns,fifo-depth = <256>; 577 cdns,fifo-width = <4>; 578 cdns,trigger-address = <0x0>; 579 clocks = <&k3_clks 103 0>; 580 assigned-clocks = <&k3_clks 103 0>; 581 assigned-clock-parents = <&k3_clks 103 2>; 582 assigned-clock-rates = <166666666>; 583 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 }; 589 590 tscadc0: tscadc@40200000 { 591 compatible = "ti,am3359-tscadc"; 592 reg = <0x00 0x40200000 0x00 0x1000>; 593 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 594 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 595 clocks = <&k3_clks 0 1>; 596 assigned-clocks = <&k3_clks 0 3>; 597 assigned-clock-rates = <60000000>; 598 clock-names = "fck"; 599 dmas = <&main_udmap 0x7400>, 600 <&main_udmap 0x7401>; 601 dma-names = "fifo0", "fifo1"; 602 603 adc { 604 #io-channel-cells = <1>; 605 compatible = "ti,am3359-adc"; 606 }; 607 }; 608 609 mcu_r5fss0: r5fss@41000000 { 610 compatible = "ti,j7200-r5fss"; 611 ti,cluster-mode = <1>; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 ranges = <0x41000000 0x00 0x41000000 0x20000>, 615 <0x41400000 0x00 0x41400000 0x20000>; 616 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 617 status = "disabled"; 618 619 mcu_r5fss0_core0: r5f@41000000 { 620 compatible = "ti,j7200-r5f"; 621 reg = <0x41000000 0x00010000>, 622 <0x41010000 0x00010000>; 623 reg-names = "atcm", "btcm"; 624 ti,sci = <&dmsc>; 625 ti,sci-dev-id = <250>; 626 ti,sci-proc-ids = <0x01 0xff>; 627 resets = <&k3_reset 250 1>; 628 firmware-name = "j7200-mcu-r5f0_0-fw"; 629 ti,atcm-enable = <1>; 630 ti,btcm-enable = <1>; 631 ti,loczrama = <1>; 632 status = "disabled"; 633 }; 634 635 mcu_r5fss0_core1: r5f@41400000 { 636 compatible = "ti,j7200-r5f"; 637 reg = <0x41400000 0x00008000>, 638 <0x41410000 0x00008000>; 639 reg-names = "atcm", "btcm"; 640 ti,sci = <&dmsc>; 641 ti,sci-dev-id = <251>; 642 ti,sci-proc-ids = <0x02 0xff>; 643 resets = <&k3_reset 251 1>; 644 firmware-name = "j7200-mcu-r5f0_1-fw"; 645 ti,atcm-enable = <1>; 646 ti,btcm-enable = <1>; 647 ti,loczrama = <1>; 648 status = "disabled"; 649 }; 650 }; 651 652 mcu_crypto: crypto@40900000 { 653 compatible = "ti,j721e-sa2ul"; 654 reg = <0x00 0x40900000 0x00 0x1200>; 655 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 656 #address-cells = <2>; 657 #size-cells = <2>; 658 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 659 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 660 <&mcu_udmap 0x7503>; 661 dma-names = "tx", "rx1", "rx2"; 662 663 rng: rng@40910000 { 664 compatible = "inside-secure,safexcel-eip76"; 665 reg = <0x00 0x40910000 0x00 0x7d>; 666 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 667 status = "disabled"; /* Used by OP-TEE */ 668 }; 669 }; 670 671 wkup_vtm0: temperature-sensor@42040000 { 672 compatible = "ti,j7200-vtm"; 673 reg = <0x00 0x42040000 0x00 0x350>, 674 <0x00 0x42050000 0x00 0x350>; 675 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 676 #thermal-sensor-cells = <1>; 677 bootph-pre-ram; 678 }; 679 680 mcu_esm: esm@40800000 { 681 compatible = "ti,j721e-esm"; 682 reg = <0x00 0x40800000 0x00 0x1000>; 683 ti,esm-pins = <95>; 684 bootph-pre-ram; 685 }; 686 687 mcu_mcan0: can@40528000 { 688 compatible = "bosch,m_can"; 689 reg = <0x00 0x40528000 0x00 0x200>, 690 <0x00 0x40500000 0x00 0x8000>; 691 reg-names = "m_can", "message_ram"; 692 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 693 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; 694 clock-names = "hclk", "cclk"; 695 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 697 interrupt-names = "int0", "int1"; 698 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 699 status = "disabled"; 700 }; 701 702 mcu_mcan1: can@40568000 { 703 compatible = "bosch,m_can"; 704 reg = <0x00 0x40568000 0x00 0x200>, 705 <0x00 0x40540000 0x00 0x8000>; 706 reg-names = "m_can", "message_ram"; 707 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 708 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; 709 clock-names = "hclk", "cclk"; 710 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-names = "int0", "int1"; 713 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 714 status = "disabled"; 715 }; 716};
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