k3-am65-ti-ipc-firmware.dtsi

 1// SPDX-License-Identifier: GPL-2.0-only OR MIT
 2/**
 3 * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs
 4 *
 5 * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/
 6 */
 7
 8&reserved_memory {
 9	mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
10		compatible = "shared-dma-pool";
11		reg = <0 0xa1000000 0 0x100000>;
12		no-map;
13	};
14
15	mcu_r5fss0_core1_memory_region: memory@a1100000 {
16		compatible = "shared-dma-pool";
17		reg = <0 0xa1100000 0 0xf00000>;
18		no-map;
19	};
20
21	rtos_ipc_memory_region: memory@a2000000 {
22		reg = <0x00 0xa2000000 0x00 0x00100000>;
23		alignment = <0x1000>;
24		no-map;
25	};
26};
27
28&mailbox0_cluster0 {
29	status = "okay";
30	interrupts = <436>;
31
32	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
33		ti,mbox-tx = <1 0 0>;
34		ti,mbox-rx = <0 0 0>;
35	};
36};
37
38&mailbox0_cluster1 {
39	status = "okay";
40	interrupts = <432>;
41
42	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
43		ti,mbox-tx = <1 0 0>;
44		ti,mbox-rx = <0 0 0>;
45	};
46};
47
48&mcu_r5fss0 {
49	status = "okay";
50};
51
52&mcu_r5fss0_core0 {
53	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
54			<&mcu_r5fss0_core0_memory_region>;
55	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
56	status = "okay";
57};
58
59&mcu_r5fss0_core1 {
60	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
61			<&mcu_r5fss0_core1_memory_region>;
62	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
63	status = "okay";
64};