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k3-am65-main.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 main_esm: esm@700000 { 58 compatible = "ti,j721e-esm"; 59 reg = <0x00 0x700000 0x00 0x1000>; 60 bootph-pre-ram; 61 /* Interrupt sources: rti0, rti1, rti2, rti3 */ 62 ti,esm-pins = <224>, <225>, <226>, <227>; 63 }; 64 65 serdes0: serdes@900000 { 66 compatible = "ti,phy-am654-serdes"; 67 reg = <0x0 0x900000 0x0 0x2000>; 68 reg-names = "serdes"; 69 #phy-cells = <2>; 70 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 71 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 72 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 73 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 74 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 75 ti,serdes-clk = <&serdes0_clk>; 76 #clock-cells = <1>; 77 mux-controls = <&serdes0_mux 0>; 78 }; 79 80 serdes1: serdes@910000 { 81 compatible = "ti,phy-am654-serdes"; 82 reg = <0x0 0x910000 0x0 0x2000>; 83 reg-names = "serdes"; 84 #phy-cells = <2>; 85 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 86 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 87 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 88 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 89 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 90 ti,serdes-clk = <&serdes1_clk>; 91 #clock-cells = <1>; 92 mux-controls = <&serdes1_mux 0>; 93 }; 94 95 main_uart0: serial@2800000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02800000 0x00 0x100>; 98 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 99 clock-frequency = <48000000>; 100 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 101 status = "disabled"; 102 }; 103 104 main_uart1: serial@2810000 { 105 compatible = "ti,am654-uart"; 106 reg = <0x00 0x02810000 0x00 0x100>; 107 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 108 clock-frequency = <48000000>; 109 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 110 status = "disabled"; 111 }; 112 113 main_uart2: serial@2820000 { 114 compatible = "ti,am654-uart"; 115 reg = <0x00 0x02820000 0x00 0x100>; 116 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 117 clock-frequency = <48000000>; 118 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 119 status = "disabled"; 120 }; 121 122 crypto: crypto@4e00000 { 123 compatible = "ti,am654-sa2ul"; 124 reg = <0x0 0x4e00000 0x0 0x1200>; 125 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>; 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 129 130 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 131 <&main_udmap 0x4003>; 132 dma-names = "tx", "rx1", "rx2"; 133 134 rng: rng@4e10000 { 135 compatible = "inside-secure,safexcel-eip76"; 136 reg = <0x0 0x4e10000 0x0 0x7d>; 137 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 138 status = "disabled"; /* Used by OP-TEE */ 139 }; 140 }; 141 142 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 143 main_timerio_input: pinctrl@104200 { 144 compatible = "pinctrl-single"; 145 reg = <0x0 0x104200 0x0 0x30>; 146 #pinctrl-cells = <1>; 147 pinctrl-single,register-width = <32>; 148 pinctrl-single,function-mask = <0x0000001ff>; 149 }; 150 151 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 152 main_timerio_output: pinctrl@104280 { 153 compatible = "pinctrl-single"; 154 reg = <0x0 0x104280 0x0 0x20>; 155 #pinctrl-cells = <1>; 156 pinctrl-single,register-width = <32>; 157 pinctrl-single,function-mask = <0x0000000f>; 158 }; 159 160 main_pmx0: pinctrl@11c000 { 161 compatible = "pinctrl-single"; 162 reg = <0x0 0x11c000 0x0 0x2e4>; 163 #pinctrl-cells = <1>; 164 pinctrl-single,register-width = <32>; 165 pinctrl-single,function-mask = <0xffffffff>; 166 }; 167 168 main_pmx1: pinctrl@11c2e8 { 169 compatible = "pinctrl-single"; 170 reg = <0x0 0x11c2e8 0x0 0x24>; 171 #pinctrl-cells = <1>; 172 pinctrl-single,register-width = <32>; 173 pinctrl-single,function-mask = <0xffffffff>; 174 }; 175 176 main_i2c0: i2c@2000000 { 177 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 178 reg = <0x0 0x2000000 0x0 0x100>; 179 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 clock-names = "fck"; 183 clocks = <&k3_clks 110 1>; 184 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 185 status = "disabled"; 186 }; 187 188 main_i2c1: i2c@2010000 { 189 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 190 reg = <0x0 0x2010000 0x0 0x100>; 191 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 clock-names = "fck"; 195 clocks = <&k3_clks 111 1>; 196 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 197 status = "disabled"; 198 }; 199 200 main_i2c2: i2c@2020000 { 201 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 202 reg = <0x0 0x2020000 0x0 0x100>; 203 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 clock-names = "fck"; 207 clocks = <&k3_clks 112 1>; 208 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 209 status = "disabled"; 210 }; 211 212 main_i2c3: i2c@2030000 { 213 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 214 reg = <0x0 0x2030000 0x0 0x100>; 215 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 clock-names = "fck"; 219 clocks = <&k3_clks 113 1>; 220 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 221 status = "disabled"; 222 }; 223 224 ecap0: pwm@3100000 { 225 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 226 #pwm-cells = <3>; 227 reg = <0x0 0x03100000 0x0 0x60>; 228 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 229 clocks = <&k3_clks 39 0>; 230 clock-names = "fck"; 231 status = "disabled"; 232 }; 233 234 main_spi0: spi@2100000 { 235 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 236 reg = <0x0 0x2100000 0x0 0x400>; 237 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&k3_clks 137 1>; 239 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 243 dma-names = "tx0", "rx0"; 244 status = "disabled"; 245 }; 246 247 main_spi1: spi@2110000 { 248 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 249 reg = <0x0 0x2110000 0x0 0x400>; 250 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 138 1>; 252 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 assigned-clocks = <&k3_clks 137 1>; 256 assigned-clock-rates = <48000000>; 257 status = "disabled"; 258 }; 259 260 main_spi2: spi@2120000 { 261 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 262 reg = <0x0 0x2120000 0x0 0x400>; 263 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&k3_clks 139 1>; 265 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 main_spi3: spi@2130000 { 272 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 273 reg = <0x0 0x2130000 0x0 0x400>; 274 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 140 1>; 276 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 main_spi4: spi@2140000 { 283 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 284 reg = <0x0 0x2140000 0x0 0x400>; 285 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&k3_clks 141 1>; 287 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 main_timer0: timer@2400000 { 294 compatible = "ti,am654-timer"; 295 reg = <0x00 0x2400000 0x00 0x400>; 296 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&k3_clks 23 0>; 298 clock-names = "fck"; 299 assigned-clocks = <&k3_clks 23 0>; 300 assigned-clock-parents = <&k3_clks 23 1>; 301 power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; 302 ti,timer-pwm; 303 }; 304 305 main_timer1: timer@2410000 { 306 compatible = "ti,am654-timer"; 307 reg = <0x00 0x2410000 0x00 0x400>; 308 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&k3_clks 24 0>; 310 clock-names = "fck"; 311 assigned-clocks = <&k3_clks 24 0>; 312 assigned-clock-parents = <&k3_clks 24 1>; 313 power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; 314 ti,timer-pwm; 315 }; 316 317 main_timer2: timer@2420000 { 318 compatible = "ti,am654-timer"; 319 reg = <0x00 0x2420000 0x00 0x400>; 320 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&k3_clks 27 0>; 322 clock-names = "fck"; 323 assigned-clocks = <&k3_clks 27 0>; 324 assigned-clock-parents = <&k3_clks 27 1>; 325 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 326 ti,timer-pwm; 327 }; 328 329 main_timer3: timer@2430000 { 330 compatible = "ti,am654-timer"; 331 reg = <0x00 0x2430000 0x00 0x400>; 332 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&k3_clks 28 0>; 334 clock-names = "fck"; 335 assigned-clocks = <&k3_clks 28 0>; 336 assigned-clock-parents = <&k3_clks 28 1>; 337 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 338 ti,timer-pwm; 339 }; 340 341 main_timer4: timer@2440000 { 342 compatible = "ti,am654-timer"; 343 reg = <0x00 0x2440000 0x00 0x400>; 344 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&k3_clks 29 0>; 346 clock-names = "fck"; 347 assigned-clocks = <&k3_clks 29 0>; 348 assigned-clock-parents = <&k3_clks 29 1>; 349 power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; 350 ti,timer-pwm; 351 }; 352 353 main_timer5: timer@2450000 { 354 compatible = "ti,am654-timer"; 355 reg = <0x00 0x2450000 0x00 0x400>; 356 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&k3_clks 30 0>; 358 clock-names = "fck"; 359 assigned-clocks = <&k3_clks 30 0>; 360 assigned-clock-parents = <&k3_clks 30 1>; 361 power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; 362 ti,timer-pwm; 363 }; 364 365 main_timer6: timer@2460000 { 366 compatible = "ti,am654-timer"; 367 reg = <0x00 0x2460000 0x00 0x400>; 368 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&k3_clks 31 0>; 370 assigned-clocks = <&k3_clks 31 0>; 371 assigned-clock-parents = <&k3_clks 31 1>; 372 clock-names = "fck"; 373 power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; 374 ti,timer-pwm; 375 }; 376 377 main_timer7: timer@2470000 { 378 compatible = "ti,am654-timer"; 379 reg = <0x00 0x2470000 0x00 0x400>; 380 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&k3_clks 32 0>; 382 clock-names = "fck"; 383 assigned-clocks = <&k3_clks 32 0>; 384 assigned-clock-parents = <&k3_clks 32 1>; 385 power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; 386 ti,timer-pwm; 387 }; 388 389 main_timer8: timer@2480000 { 390 compatible = "ti,am654-timer"; 391 reg = <0x00 0x2480000 0x00 0x400>; 392 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&k3_clks 33 0>; 394 clock-names = "fck"; 395 assigned-clocks = <&k3_clks 33 0>; 396 assigned-clock-parents = <&k3_clks 33 1>; 397 power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; 398 ti,timer-pwm; 399 }; 400 401 main_timer9: timer@2490000 { 402 compatible = "ti,am654-timer"; 403 reg = <0x00 0x2490000 0x00 0x400>; 404 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&k3_clks 34 0>; 406 clock-names = "fck"; 407 assigned-clocks = <&k3_clks 34 0>; 408 assigned-clock-parents = <&k3_clks 34 1>; 409 power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; 410 ti,timer-pwm; 411 }; 412 413 main_timer10: timer@24a0000 { 414 compatible = "ti,am654-timer"; 415 reg = <0x00 0x24a0000 0x00 0x400>; 416 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&k3_clks 25 0>; 418 clock-names = "fck"; 419 assigned-clocks = <&k3_clks 25 0>; 420 assigned-clock-parents = <&k3_clks 25 1>; 421 power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; 422 ti,timer-pwm; 423 }; 424 425 main_timer11: timer@24b0000 { 426 compatible = "ti,am654-timer"; 427 reg = <0x00 0x24b0000 0x00 0x400>; 428 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&k3_clks 26 0>; 430 clock-names = "fck"; 431 assigned-clocks = <&k3_clks 26 0>; 432 assigned-clock-parents = <&k3_clks 26 1>; 433 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 434 ti,timer-pwm; 435 }; 436 437 sdhci0: mmc@4f80000 { 438 compatible = "ti,am654-sdhci-5.1"; 439 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 440 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 441 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 442 clock-names = "clk_ahb", "clk_xin"; 443 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 444 mmc-ddr-1_8v; 445 mmc-hs200-1_8v; 446 ti,clkbuf-sel = <0x7>; 447 ti,trm-icp = <0x8>; 448 ti,otap-del-sel-legacy = <0x0>; 449 ti,otap-del-sel-mmc-hs = <0x0>; 450 ti,otap-del-sel-ddr52 = <0x5>; 451 ti,otap-del-sel-hs200 = <0x5>; 452 ti,itap-del-sel-legacy = <0xa>; 453 ti,itap-del-sel-mmc-hs = <0x1>; 454 ti,itap-del-sel-ddr52 = <0x0>; 455 dma-coherent; 456 status = "disabled"; 457 }; 458 459 sdhci1: mmc@4fa0000 { 460 compatible = "ti,am654-sdhci-5.1"; 461 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 462 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 463 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 464 clock-names = "clk_ahb", "clk_xin"; 465 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 466 ti,clkbuf-sel = <0x7>; 467 ti,trm-icp = <0x8>; 468 ti,otap-del-sel-legacy = <0x0>; 469 ti,otap-del-sel-sd-hs = <0x0>; 470 ti,otap-del-sel-sdr12 = <0xf>; 471 ti,otap-del-sel-sdr25 = <0xf>; 472 ti,otap-del-sel-sdr50 = <0x8>; 473 ti,otap-del-sel-sdr104 = <0x7>; 474 ti,otap-del-sel-ddr50 = <0x4>; 475 ti,itap-del-sel-legacy = <0xa>; 476 ti,itap-del-sel-sd-hs = <0x1>; 477 ti,itap-del-sel-sdr12 = <0xa>; 478 ti,itap-del-sel-sdr25 = <0x1>; 479 dma-coherent; 480 status = "disabled"; 481 }; 482 483 scm_conf: scm-conf@100000 { 484 compatible = "ti,am654-system-controller", "syscon", "simple-mfd"; 485 reg = <0 0x00100000 0 0x1c000>; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 ranges = <0x0 0x0 0x00100000 0x1c000>; 489 490 serdes0_clk: clock@4080 { 491 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd"; 492 reg = <0x4080 0x4>; 493 494 serdes0_mux: mux-controller { 495 compatible = "mmio-mux"; 496 #mux-control-cells = <1>; 497 mux-reg-masks = <0x0 0x3>; /* lane select */ 498 }; 499 }; 500 501 serdes1_clk: clock@4090 { 502 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd"; 503 reg = <0x4090 0x4>; 504 505 serdes1_mux: mux-controller { 506 compatible = "mmio-mux"; 507 #mux-control-cells = <1>; 508 mux-reg-masks = <0x0 0x3>; /* lane select */ 509 }; 510 }; 511 512 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 513 compatible = "ti,am654-dss-oldi-io-ctrl", "syscon"; 514 reg = <0x41e0 0x14>; 515 }; 516 517 ehrpwm_tbclk: clock-controller@4140 { 518 compatible = "ti,am654-ehrpwm-tbclk"; 519 reg = <0x4140 0x18>; 520 #clock-cells = <1>; 521 }; 522 }; 523 524 dwc3_0: dwc3@4000000 { 525 compatible = "ti,am654-dwc3"; 526 reg = <0x0 0x4000000 0x0 0x4000>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0x0 0x0 0x4000000 0x20000>; 530 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 531 dma-coherent; 532 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 533 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 534 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 535 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 536 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 537 538 usb0: usb@10000 { 539 compatible = "snps,dwc3"; 540 reg = <0x10000 0x10000>; 541 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 544 interrupt-names = "peripheral", 545 "host", 546 "otg"; 547 maximum-speed = "high-speed"; 548 dr_mode = "otg"; 549 phys = <&usb0_phy>; 550 phy-names = "usb2-phy"; 551 snps,dis_u3_susphy_quirk; 552 }; 553 }; 554 555 usb0_phy: phy@4100000 { 556 compatible = "ti,am654-usb2", "ti,omap-usb2"; 557 reg = <0x0 0x4100000 0x0 0x54>; 558 syscon-phy-power = <&scm_conf 0x4000>; 559 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 560 clock-names = "wkupclk", "refclk"; 561 #phy-cells = <0>; 562 }; 563 564 dwc3_1: dwc3@4020000 { 565 compatible = "ti,am654-dwc3"; 566 reg = <0x0 0x4020000 0x0 0x4000>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges = <0x0 0x0 0x4020000 0x20000>; 570 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 571 dma-coherent; 572 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 573 clocks = <&k3_clks 152 2>; 574 assigned-clocks = <&k3_clks 152 2>; 575 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 576 577 usb1: usb@10000 { 578 compatible = "snps,dwc3"; 579 reg = <0x10000 0x10000>; 580 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "peripheral", 584 "host", 585 "otg"; 586 maximum-speed = "high-speed"; 587 dr_mode = "otg"; 588 phys = <&usb1_phy>; 589 phy-names = "usb2-phy"; 590 }; 591 }; 592 593 usb1_phy: phy@4110000 { 594 compatible = "ti,am654-usb2", "ti,omap-usb2"; 595 reg = <0x0 0x4110000 0x0 0x54>; 596 syscon-phy-power = <&scm_conf 0x4020>; 597 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 598 clock-names = "wkupclk", "refclk"; 599 #phy-cells = <0>; 600 }; 601 602 intr_main_gpio: interrupt-controller@a00000 { 603 compatible = "ti,sci-intr"; 604 reg = <0x0 0x00a00000 0x0 0x400>; 605 ti,intr-trigger-type = <1>; 606 interrupt-controller; 607 interrupt-parent = <&gic500>; 608 #interrupt-cells = <1>; 609 ti,sci = <&dmsc>; 610 ti,sci-dev-id = <100>; 611 ti,interrupt-ranges = <0 392 32>; 612 }; 613 614 main_navss: bus@30800000 { 615 compatible = "simple-bus"; 616 #address-cells = <2>; 617 #size-cells = <2>; 618 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 619 dma-coherent; 620 dma-ranges; 621 622 ti,sci-dev-id = <118>; 623 624 intr_main_navss: interrupt-controller@310e0000 { 625 compatible = "ti,sci-intr"; 626 reg = <0x0 0x310e0000 0x0 0x2000>; 627 ti,intr-trigger-type = <4>; 628 interrupt-controller; 629 interrupt-parent = <&gic500>; 630 #interrupt-cells = <1>; 631 ti,sci = <&dmsc>; 632 ti,sci-dev-id = <182>; 633 ti,interrupt-ranges = <0 64 64>, 634 <64 448 64>; 635 }; 636 637 inta_main_udmass: interrupt-controller@33d00000 { 638 compatible = "ti,sci-inta"; 639 reg = <0x0 0x33d00000 0x0 0x100000>; 640 interrupt-controller; 641 interrupt-parent = <&intr_main_navss>; 642 msi-controller; 643 #interrupt-cells = <0>; 644 ti,sci = <&dmsc>; 645 ti,sci-dev-id = <179>; 646 ti,interrupt-ranges = <0 0 256>; 647 }; 648 649 secure_proxy_main: mailbox@32c00000 { 650 compatible = "ti,am654-secure-proxy"; 651 #mbox-cells = <1>; 652 reg-names = "target_data", "rt", "scfg"; 653 reg = <0x00 0x32c00000 0x00 0x100000>, 654 <0x00 0x32400000 0x00 0x100000>, 655 <0x00 0x32800000 0x00 0x100000>; 656 interrupt-names = "rx_011"; 657 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 658 bootph-all; 659 }; 660 661 hwspinlock: spinlock@30e00000 { 662 compatible = "ti,am654-hwspinlock"; 663 reg = <0x00 0x30e00000 0x00 0x1000>; 664 #hwlock-cells = <1>; 665 }; 666 667 mailbox0_cluster0: mailbox@31f80000 { 668 compatible = "ti,am654-mailbox"; 669 reg = <0x00 0x31f80000 0x00 0x200>; 670 #mbox-cells = <1>; 671 ti,mbox-num-users = <4>; 672 ti,mbox-num-fifos = <16>; 673 interrupt-parent = <&intr_main_navss>; 674 status = "disabled"; 675 }; 676 677 mailbox0_cluster1: mailbox@31f81000 { 678 compatible = "ti,am654-mailbox"; 679 reg = <0x00 0x31f81000 0x00 0x200>; 680 #mbox-cells = <1>; 681 ti,mbox-num-users = <4>; 682 ti,mbox-num-fifos = <16>; 683 interrupt-parent = <&intr_main_navss>; 684 status = "disabled"; 685 }; 686 687 mailbox0_cluster2: mailbox@31f82000 { 688 compatible = "ti,am654-mailbox"; 689 reg = <0x00 0x31f82000 0x00 0x200>; 690 #mbox-cells = <1>; 691 ti,mbox-num-users = <4>; 692 ti,mbox-num-fifos = <16>; 693 interrupt-parent = <&intr_main_navss>; 694 status = "disabled"; 695 }; 696 697 mailbox0_cluster3: mailbox@31f83000 { 698 compatible = "ti,am654-mailbox"; 699 reg = <0x00 0x31f83000 0x00 0x200>; 700 #mbox-cells = <1>; 701 ti,mbox-num-users = <4>; 702 ti,mbox-num-fifos = <16>; 703 interrupt-parent = <&intr_main_navss>; 704 status = "disabled"; 705 }; 706 707 mailbox0_cluster4: mailbox@31f84000 { 708 compatible = "ti,am654-mailbox"; 709 reg = <0x00 0x31f84000 0x00 0x200>; 710 #mbox-cells = <1>; 711 ti,mbox-num-users = <4>; 712 ti,mbox-num-fifos = <16>; 713 interrupt-parent = <&intr_main_navss>; 714 status = "disabled"; 715 }; 716 717 mailbox0_cluster5: mailbox@31f85000 { 718 compatible = "ti,am654-mailbox"; 719 reg = <0x00 0x31f85000 0x00 0x200>; 720 #mbox-cells = <1>; 721 ti,mbox-num-users = <4>; 722 ti,mbox-num-fifos = <16>; 723 interrupt-parent = <&intr_main_navss>; 724 status = "disabled"; 725 }; 726 727 mailbox0_cluster6: mailbox@31f86000 { 728 compatible = "ti,am654-mailbox"; 729 reg = <0x00 0x31f86000 0x00 0x200>; 730 #mbox-cells = <1>; 731 ti,mbox-num-users = <4>; 732 ti,mbox-num-fifos = <16>; 733 interrupt-parent = <&intr_main_navss>; 734 status = "disabled"; 735 }; 736 737 mailbox0_cluster7: mailbox@31f87000 { 738 compatible = "ti,am654-mailbox"; 739 reg = <0x00 0x31f87000 0x00 0x200>; 740 #mbox-cells = <1>; 741 ti,mbox-num-users = <4>; 742 ti,mbox-num-fifos = <16>; 743 interrupt-parent = <&intr_main_navss>; 744 status = "disabled"; 745 }; 746 747 mailbox0_cluster8: mailbox@31f88000 { 748 compatible = "ti,am654-mailbox"; 749 reg = <0x00 0x31f88000 0x00 0x200>; 750 #mbox-cells = <1>; 751 ti,mbox-num-users = <4>; 752 ti,mbox-num-fifos = <16>; 753 interrupt-parent = <&intr_main_navss>; 754 status = "disabled"; 755 }; 756 757 mailbox0_cluster9: mailbox@31f89000 { 758 compatible = "ti,am654-mailbox"; 759 reg = <0x00 0x31f89000 0x00 0x200>; 760 #mbox-cells = <1>; 761 ti,mbox-num-users = <4>; 762 ti,mbox-num-fifos = <16>; 763 interrupt-parent = <&intr_main_navss>; 764 status = "disabled"; 765 }; 766 767 mailbox0_cluster10: mailbox@31f8a000 { 768 compatible = "ti,am654-mailbox"; 769 reg = <0x00 0x31f8a000 0x00 0x200>; 770 #mbox-cells = <1>; 771 ti,mbox-num-users = <4>; 772 ti,mbox-num-fifos = <16>; 773 interrupt-parent = <&intr_main_navss>; 774 status = "disabled"; 775 }; 776 777 mailbox0_cluster11: mailbox@31f8b000 { 778 compatible = "ti,am654-mailbox"; 779 reg = <0x00 0x31f8b000 0x00 0x200>; 780 #mbox-cells = <1>; 781 ti,mbox-num-users = <4>; 782 ti,mbox-num-fifos = <16>; 783 interrupt-parent = <&intr_main_navss>; 784 status = "disabled"; 785 }; 786 787 ringacc: ringacc@3c000000 { 788 compatible = "ti,am654-navss-ringacc"; 789 reg = <0x0 0x3c000000 0x0 0x400000>, 790 <0x0 0x38000000 0x0 0x400000>, 791 <0x0 0x31120000 0x0 0x100>, 792 <0x0 0x33000000 0x0 0x40000>, 793 <0x0 0x31080000 0x0 0x40000>; 794 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 795 ti,num-rings = <818>; 796 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 797 ti,sci = <&dmsc>; 798 ti,sci-dev-id = <187>; 799 msi-parent = <&inta_main_udmass>; 800 }; 801 802 main_udmap: dma-controller@31150000 { 803 compatible = "ti,am654-navss-main-udmap"; 804 reg = <0x0 0x31150000 0x0 0x100>, 805 <0x0 0x34000000 0x0 0x100000>, 806 <0x0 0x35000000 0x0 0x100000>, 807 <0x0 0x30b00000 0x0 0x10000>, 808 <0x0 0x30c00000 0x0 0x10000>, 809 <0x0 0x30d00000 0x0 0x8000>; 810 reg-names = "gcfg", "rchanrt", "tchanrt", 811 "tchan", "rchan", "rflow"; 812 msi-parent = <&inta_main_udmass>; 813 #dma-cells = <1>; 814 815 ti,sci = <&dmsc>; 816 ti,sci-dev-id = <188>; 817 ti,ringacc = <&ringacc>; 818 819 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 820 <0xd>; /* TX_CHAN */ 821 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 822 <0xa>; /* RX_CHAN */ 823 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 824 }; 825 826 cpts@310d0000 { 827 compatible = "ti,am65-cpts"; 828 reg = <0x0 0x310d0000 0x0 0x400>; 829 reg-names = "cpts"; 830 clocks = <&main_cpts_mux>; 831 clock-names = "cpts"; 832 interrupts-extended = <&intr_main_navss 391>; 833 interrupt-names = "cpts"; 834 ti,cpts-periodic-outputs = <6>; 835 ti,cpts-ext-ts-inputs = <8>; 836 837 main_cpts_mux: refclk-mux { 838 #clock-cells = <0>; 839 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 840 <&k3_clks 118 6>, <&k3_clks 118 3>, 841 <&k3_clks 118 8>, <&k3_clks 118 14>, 842 <&k3_clks 120 3>, <&k3_clks 121 3>; 843 assigned-clocks = <&main_cpts_mux>; 844 assigned-clock-parents = <&k3_clks 118 5>; 845 }; 846 }; 847 }; 848 849 main_gpio0: gpio@600000 { 850 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 851 reg = <0x0 0x600000 0x0 0x100>; 852 gpio-controller; 853 #gpio-cells = <2>; 854 interrupt-parent = <&intr_main_gpio>; 855 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 856 interrupt-controller; 857 #interrupt-cells = <2>; 858 ti,ngpio = <96>; 859 ti,davinci-gpio-unbanked = <0>; 860 clocks = <&k3_clks 57 0>; 861 clock-names = "gpio"; 862 }; 863 864 main_gpio1: gpio@601000 { 865 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 866 reg = <0x0 0x601000 0x0 0x100>; 867 gpio-controller; 868 #gpio-cells = <2>; 869 interrupt-parent = <&intr_main_gpio>; 870 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 871 interrupt-controller; 872 #interrupt-cells = <2>; 873 ti,ngpio = <90>; 874 ti,davinci-gpio-unbanked = <0>; 875 clocks = <&k3_clks 58 0>; 876 clock-names = "gpio"; 877 }; 878 879 pcie0_rc: pcie@5500000 { 880 compatible = "ti,am654-pcie-rc"; 881 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 882 reg-names = "app", "dbics", "config", "atu"; 883 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 884 #address-cells = <3>; 885 #size-cells = <2>; 886 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 887 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 888 ti,syscon-pcie-id = <&scm_conf 0x210>; 889 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 890 bus-range = <0x0 0xff>; 891 num-viewport = <16>; 892 max-link-speed = <2>; 893 dma-coherent; 894 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 895 msi-map = <0x0 &gic_its 0x0 0x10000>; 896 device_type = "pci"; 897 status = "disabled"; 898 }; 899 900 pcie1_rc: pcie@5600000 { 901 compatible = "ti,am654-pcie-rc"; 902 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 903 reg-names = "app", "dbics", "config", "atu"; 904 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 905 #address-cells = <3>; 906 #size-cells = <2>; 907 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 908 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 909 ti,syscon-pcie-id = <&scm_conf 0x210>; 910 ti,syscon-pcie-mode = <&scm_conf 0x4070>; 911 bus-range = <0x0 0xff>; 912 num-viewport = <16>; 913 max-link-speed = <2>; 914 dma-coherent; 915 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 916 msi-map = <0x0 &gic_its 0x10000 0x10000>; 917 device_type = "pci"; 918 status = "disabled"; 919 }; 920 921 mcasp0: mcasp@2b00000 { 922 compatible = "ti,am33xx-mcasp-audio"; 923 reg = <0x0 0x02b00000 0x0 0x2000>, 924 <0x0 0x02b08000 0x0 0x1000>; 925 reg-names = "mpu","dat"; 926 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "tx", "rx"; 929 930 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 931 dma-names = "tx", "rx"; 932 933 clocks = <&k3_clks 104 0>; 934 clock-names = "fck"; 935 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 936 status = "disabled"; 937 }; 938 939 mcasp1: mcasp@2b10000 { 940 compatible = "ti,am33xx-mcasp-audio"; 941 reg = <0x0 0x02b10000 0x0 0x2000>, 942 <0x0 0x02b18000 0x0 0x1000>; 943 reg-names = "mpu","dat"; 944 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "tx", "rx"; 947 948 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 949 dma-names = "tx", "rx"; 950 951 clocks = <&k3_clks 105 0>; 952 clock-names = "fck"; 953 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 954 status = "disabled"; 955 }; 956 957 mcasp2: mcasp@2b20000 { 958 compatible = "ti,am33xx-mcasp-audio"; 959 reg = <0x0 0x02b20000 0x0 0x2000>, 960 <0x0 0x02b28000 0x0 0x1000>; 961 reg-names = "mpu","dat"; 962 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "tx", "rx"; 965 966 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 967 dma-names = "tx", "rx"; 968 969 clocks = <&k3_clks 106 0>; 970 clock-names = "fck"; 971 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 972 status = "disabled"; 973 }; 974 975 cal: cal@6f03000 { 976 compatible = "ti,am654-cal"; 977 reg = <0x0 0x06f03000 0x0 0x400>, 978 <0x0 0x06f03800 0x0 0x40>; 979 reg-names = "cal_top", 980 "cal_rx_core0"; 981 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 982 ti,camerrx-control = <&scm_conf 0x40c0>; 983 clock-names = "fck"; 984 clocks = <&k3_clks 2 0>; 985 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 986 987 ports { 988 #address-cells = <1>; 989 #size-cells = <0>; 990 991 csi2_0: port@0 { 992 reg = <0>; 993 }; 994 }; 995 }; 996 997 dss: dss@4a00000 { 998 compatible = "ti,am65x-dss"; 999 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1000 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1001 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1002 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1003 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1004 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1005 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ 1006 <0x0 0x04a01000 0x0 0x1000>; /* common1 */ 1007 reg-names = "common", "vidl1", "vid", 1008 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1009 1010 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 1011 1012 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1013 1014 clocks = <&k3_clks 67 1>, 1015 <&k3_clks 216 1>, 1016 <&k3_clks 67 2>; 1017 clock-names = "fck", "vp1", "vp2"; 1018 1019 /* 1020 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 1021 * DIV1. See "Figure 12-3365. DSS Integration" 1022 * in AM65x TRM for details. 1023 */ 1024 assigned-clocks = <&k3_clks 67 2>; 1025 assigned-clock-parents = <&k3_clks 67 5>; 1026 1027 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1028 1029 dma-coherent; 1030 1031 dss_ports: ports { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 }; 1035 }; 1036 1037 gpu: gpu@7000000 { 1038 compatible = "ti,am6548-gpu", "img,powervr-sgx544"; 1039 reg = <0x0 0x7000000 0x0 0x10000>; 1040 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1041 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1042 }; 1043 1044 ehrpwm0: pwm@3000000 { 1045 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1046 #pwm-cells = <3>; 1047 reg = <0x0 0x3000000 0x0 0x100>; 1048 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 1049 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 1050 clock-names = "tbclk", "fck"; 1051 status = "disabled"; 1052 }; 1053 1054 ehrpwm1: pwm@3010000 { 1055 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1056 #pwm-cells = <3>; 1057 reg = <0x0 0x3010000 0x0 0x100>; 1058 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 1059 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 1060 clock-names = "tbclk", "fck"; 1061 status = "disabled"; 1062 }; 1063 1064 ehrpwm2: pwm@3020000 { 1065 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1066 #pwm-cells = <3>; 1067 reg = <0x0 0x3020000 0x0 0x100>; 1068 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 1069 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 1070 clock-names = "tbclk", "fck"; 1071 status = "disabled"; 1072 }; 1073 1074 ehrpwm3: pwm@3030000 { 1075 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1076 #pwm-cells = <3>; 1077 reg = <0x0 0x3030000 0x0 0x100>; 1078 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 1079 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 1080 clock-names = "tbclk", "fck"; 1081 status = "disabled"; 1082 }; 1083 1084 ehrpwm4: pwm@3040000 { 1085 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1086 #pwm-cells = <3>; 1087 reg = <0x0 0x3040000 0x0 0x100>; 1088 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 1089 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 1090 clock-names = "tbclk", "fck"; 1091 status = "disabled"; 1092 }; 1093 1094 ehrpwm5: pwm@3050000 { 1095 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 1096 #pwm-cells = <3>; 1097 reg = <0x0 0x3050000 0x0 0x100>; 1098 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 1099 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 1100 clock-names = "tbclk", "fck"; 1101 status = "disabled"; 1102 }; 1103 1104 icssg0: icssg@b000000 { 1105 compatible = "ti,am654-icssg"; 1106 reg = <0x00 0xb000000 0x00 0x80000>; 1107 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1108 #address-cells = <1>; 1109 #size-cells = <1>; 1110 ranges = <0x0 0x00 0xb000000 0x80000>; 1111 1112 icssg0_mem: memories@0 { 1113 reg = <0x0 0x2000>, 1114 <0x2000 0x2000>, 1115 <0x10000 0x10000>; 1116 reg-names = "dram0", "dram1", 1117 "shrdram2"; 1118 }; 1119 1120 icssg0_cfg: cfg@26000 { 1121 compatible = "ti,pruss-cfg", "syscon"; 1122 reg = <0x26000 0x200>; 1123 #address-cells = <1>; 1124 #size-cells = <1>; 1125 ranges = <0x0 0x26000 0x2000>; 1126 1127 clocks { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 1131 icssg0_coreclk_mux: coreclk-mux@3c { 1132 reg = <0x3c>; 1133 #clock-cells = <0>; 1134 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 1135 <&k3_clks 62 3>; /* icssg0_iclk */ 1136 assigned-clocks = <&icssg0_coreclk_mux>; 1137 assigned-clock-parents = <&k3_clks 62 3>; 1138 }; 1139 1140 icssg0_iepclk_mux: iepclk-mux@30 { 1141 reg = <0x30>; 1142 #clock-cells = <0>; 1143 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 1144 <&icssg0_coreclk_mux>; /* core_clk */ 1145 assigned-clocks = <&icssg0_iepclk_mux>; 1146 assigned-clock-parents = <&icssg0_coreclk_mux>; 1147 }; 1148 }; 1149 }; 1150 1151 icssg0_iep0: iep@2e000 { 1152 compatible = "ti,am654-icss-iep"; 1153 reg = <0x2e000 0x1000>; 1154 clocks = <&icssg0_iepclk_mux>; 1155 }; 1156 1157 icssg0_iep1: iep@2f000 { 1158 compatible = "ti,am654-icss-iep"; 1159 reg = <0x2f000 0x1000>; 1160 clocks = <&icssg0_iepclk_mux>; 1161 }; 1162 1163 icssg0_mii_rt: mii-rt@32000 { 1164 compatible = "ti,pruss-mii", "syscon"; 1165 reg = <0x32000 0x100>; 1166 }; 1167 1168 icssg0_mii_g_rt: mii-g-rt@33000 { 1169 compatible = "ti,pruss-mii-g", "syscon"; 1170 reg = <0x33000 0x1000>; 1171 }; 1172 1173 icssg0_pa_stats: pa-stats@2c000 { 1174 compatible = "ti,pruss-pa-st", "syscon"; 1175 reg = <0x2c000 0x1000>; 1176 }; 1177 1178 icssg0_intc: interrupt-controller@20000 { 1179 compatible = "ti,icssg-intc"; 1180 reg = <0x20000 0x2000>; 1181 interrupt-controller; 1182 #interrupt-cells = <3>; 1183 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1191 interrupt-names = "host_intr0", "host_intr1", 1192 "host_intr2", "host_intr3", 1193 "host_intr4", "host_intr5", 1194 "host_intr6", "host_intr7"; 1195 }; 1196 1197 pru0_0: pru@34000 { 1198 compatible = "ti,am654-pru"; 1199 reg = <0x34000 0x4000>, 1200 <0x22000 0x100>, 1201 <0x22400 0x100>; 1202 reg-names = "iram", "control", "debug"; 1203 firmware-name = "am65x-pru0_0-fw"; 1204 interrupt-parent = <&icssg0_intc>; 1205 interrupts = <16 2 2>; 1206 interrupt-names = "vring"; 1207 }; 1208 1209 rtu0_0: rtu@4000 { 1210 compatible = "ti,am654-rtu"; 1211 reg = <0x4000 0x2000>, 1212 <0x23000 0x100>, 1213 <0x23400 0x100>; 1214 reg-names = "iram", "control", "debug"; 1215 firmware-name = "am65x-rtu0_0-fw"; 1216 interrupt-parent = <&icssg0_intc>; 1217 interrupts = <20 4 4>; 1218 interrupt-names = "vring"; 1219 }; 1220 1221 tx_pru0_0: txpru@a000 { 1222 compatible = "ti,am654-tx-pru"; 1223 reg = <0xa000 0x1800>, 1224 <0x25000 0x100>, 1225 <0x25400 0x100>; 1226 reg-names = "iram", "control", "debug"; 1227 firmware-name = "am65x-txpru0_0-fw"; 1228 }; 1229 1230 pru0_1: pru@38000 { 1231 compatible = "ti,am654-pru"; 1232 reg = <0x38000 0x4000>, 1233 <0x24000 0x100>, 1234 <0x24400 0x100>; 1235 reg-names = "iram", "control", "debug"; 1236 firmware-name = "am65x-pru0_1-fw"; 1237 interrupt-parent = <&icssg0_intc>; 1238 interrupts = <18 3 3>; 1239 interrupt-names = "vring"; 1240 }; 1241 1242 rtu0_1: rtu@6000 { 1243 compatible = "ti,am654-rtu"; 1244 reg = <0x6000 0x2000>, 1245 <0x23800 0x100>, 1246 <0x23c00 0x100>; 1247 reg-names = "iram", "control", "debug"; 1248 firmware-name = "am65x-rtu0_1-fw"; 1249 interrupt-parent = <&icssg0_intc>; 1250 interrupts = <22 5 5>; 1251 interrupt-names = "vring"; 1252 }; 1253 1254 tx_pru0_1: txpru@c000 { 1255 compatible = "ti,am654-tx-pru"; 1256 reg = <0xc000 0x1800>, 1257 <0x25800 0x100>, 1258 <0x25c00 0x100>; 1259 reg-names = "iram", "control", "debug"; 1260 firmware-name = "am65x-txpru0_1-fw"; 1261 }; 1262 1263 icssg0_mdio: mdio@32400 { 1264 compatible = "ti,davinci_mdio"; 1265 reg = <0x32400 0x100>; 1266 clocks = <&k3_clks 62 3>; 1267 clock-names = "fck"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 bus_freq = <1000000>; 1271 status = "disabled"; 1272 }; 1273 }; 1274 1275 icssg1: icssg@b100000 { 1276 compatible = "ti,am654-icssg"; 1277 reg = <0x00 0xb100000 0x00 0x80000>; 1278 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1279 #address-cells = <1>; 1280 #size-cells = <1>; 1281 ranges = <0x0 0x00 0xb100000 0x80000>; 1282 1283 icssg1_mem: memories@0 { 1284 reg = <0x0 0x2000>, 1285 <0x2000 0x2000>, 1286 <0x10000 0x10000>; 1287 reg-names = "dram0", "dram1", 1288 "shrdram2"; 1289 }; 1290 1291 icssg1_cfg: cfg@26000 { 1292 compatible = "ti,pruss-cfg", "syscon"; 1293 reg = <0x26000 0x200>; 1294 #address-cells = <1>; 1295 #size-cells = <1>; 1296 ranges = <0x0 0x26000 0x2000>; 1297 1298 clocks { 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 icssg1_coreclk_mux: coreclk-mux@3c { 1303 reg = <0x3c>; 1304 #clock-cells = <0>; 1305 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1306 <&k3_clks 63 3>; /* icssg1_iclk */ 1307 assigned-clocks = <&icssg1_coreclk_mux>; 1308 assigned-clock-parents = <&k3_clks 63 3>; 1309 }; 1310 1311 icssg1_iepclk_mux: iepclk-mux@30 { 1312 reg = <0x30>; 1313 #clock-cells = <0>; 1314 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1315 <&icssg1_coreclk_mux>; /* core_clk */ 1316 assigned-clocks = <&icssg1_iepclk_mux>; 1317 assigned-clock-parents = <&icssg1_coreclk_mux>; 1318 }; 1319 }; 1320 }; 1321 1322 icssg1_iep0: iep@2e000 { 1323 compatible = "ti,am654-icss-iep"; 1324 reg = <0x2e000 0x1000>; 1325 clocks = <&icssg1_iepclk_mux>; 1326 }; 1327 1328 icssg1_iep1: iep@2f000 { 1329 compatible = "ti,am654-icss-iep"; 1330 reg = <0x2f000 0x1000>; 1331 clocks = <&icssg1_iepclk_mux>; 1332 }; 1333 1334 icssg1_mii_rt: mii-rt@32000 { 1335 compatible = "ti,pruss-mii", "syscon"; 1336 reg = <0x32000 0x100>; 1337 }; 1338 1339 icssg1_mii_g_rt: mii-g-rt@33000 { 1340 compatible = "ti,pruss-mii-g", "syscon"; 1341 reg = <0x33000 0x1000>; 1342 }; 1343 1344 icssg1_pa_stats: pa-stats@2c000 { 1345 compatible = "ti,pruss-pa-st", "syscon"; 1346 reg = <0x2c000 0x1000>; 1347 }; 1348 1349 icssg1_intc: interrupt-controller@20000 { 1350 compatible = "ti,icssg-intc"; 1351 reg = <0x20000 0x2000>; 1352 interrupt-controller; 1353 #interrupt-cells = <3>; 1354 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1362 interrupt-names = "host_intr0", "host_intr1", 1363 "host_intr2", "host_intr3", 1364 "host_intr4", "host_intr5", 1365 "host_intr6", "host_intr7"; 1366 }; 1367 1368 pru1_0: pru@34000 { 1369 compatible = "ti,am654-pru"; 1370 reg = <0x34000 0x4000>, 1371 <0x22000 0x100>, 1372 <0x22400 0x100>; 1373 reg-names = "iram", "control", "debug"; 1374 firmware-name = "am65x-pru1_0-fw"; 1375 interrupt-parent = <&icssg1_intc>; 1376 interrupts = <16 2 2>; 1377 interrupt-names = "vring"; 1378 }; 1379 1380 rtu1_0: rtu@4000 { 1381 compatible = "ti,am654-rtu"; 1382 reg = <0x4000 0x2000>, 1383 <0x23000 0x100>, 1384 <0x23400 0x100>; 1385 reg-names = "iram", "control", "debug"; 1386 firmware-name = "am65x-rtu1_0-fw"; 1387 interrupt-parent = <&icssg1_intc>; 1388 interrupts = <20 4 4>; 1389 interrupt-names = "vring"; 1390 }; 1391 1392 tx_pru1_0: txpru@a000 { 1393 compatible = "ti,am654-tx-pru"; 1394 reg = <0xa000 0x1800>, 1395 <0x25000 0x100>, 1396 <0x25400 0x100>; 1397 reg-names = "iram", "control", "debug"; 1398 firmware-name = "am65x-txpru1_0-fw"; 1399 }; 1400 1401 pru1_1: pru@38000 { 1402 compatible = "ti,am654-pru"; 1403 reg = <0x38000 0x4000>, 1404 <0x24000 0x100>, 1405 <0x24400 0x100>; 1406 reg-names = "iram", "control", "debug"; 1407 firmware-name = "am65x-pru1_1-fw"; 1408 interrupt-parent = <&icssg1_intc>; 1409 interrupts = <18 3 3>; 1410 interrupt-names = "vring"; 1411 }; 1412 1413 rtu1_1: rtu@6000 { 1414 compatible = "ti,am654-rtu"; 1415 reg = <0x6000 0x2000>, 1416 <0x23800 0x100>, 1417 <0x23c00 0x100>; 1418 reg-names = "iram", "control", "debug"; 1419 firmware-name = "am65x-rtu1_1-fw"; 1420 interrupt-parent = <&icssg1_intc>; 1421 interrupts = <22 5 5>; 1422 interrupt-names = "vring"; 1423 }; 1424 1425 tx_pru1_1: txpru@c000 { 1426 compatible = "ti,am654-tx-pru"; 1427 reg = <0xc000 0x1800>, 1428 <0x25800 0x100>, 1429 <0x25c00 0x100>; 1430 reg-names = "iram", "control", "debug"; 1431 firmware-name = "am65x-txpru1_1-fw"; 1432 }; 1433 1434 icssg1_mdio: mdio@32400 { 1435 compatible = "ti,davinci_mdio"; 1436 reg = <0x32400 0x100>; 1437 clocks = <&k3_clks 63 3>; 1438 clock-names = "fck"; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 bus_freq = <1000000>; 1442 status = "disabled"; 1443 }; 1444 }; 1445 1446 icssg2: icssg@b200000 { 1447 compatible = "ti,am654-icssg"; 1448 reg = <0x00 0xb200000 0x00 0x80000>; 1449 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1450 #address-cells = <1>; 1451 #size-cells = <1>; 1452 ranges = <0x0 0x00 0xb200000 0x80000>; 1453 1454 icssg2_mem: memories@0 { 1455 reg = <0x0 0x2000>, 1456 <0x2000 0x2000>, 1457 <0x10000 0x10000>; 1458 reg-names = "dram0", "dram1", 1459 "shrdram2"; 1460 }; 1461 1462 icssg2_cfg: cfg@26000 { 1463 compatible = "ti,pruss-cfg", "syscon"; 1464 reg = <0x26000 0x200>; 1465 #address-cells = <1>; 1466 #size-cells = <1>; 1467 ranges = <0x0 0x26000 0x2000>; 1468 1469 clocks { 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 1473 icssg2_coreclk_mux: coreclk-mux@3c { 1474 reg = <0x3c>; 1475 #clock-cells = <0>; 1476 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1477 <&k3_clks 64 3>; /* icssg1_iclk */ 1478 assigned-clocks = <&icssg2_coreclk_mux>; 1479 assigned-clock-parents = <&k3_clks 64 3>; 1480 }; 1481 1482 icssg2_iepclk_mux: iepclk-mux@30 { 1483 reg = <0x30>; 1484 #clock-cells = <0>; 1485 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1486 <&icssg2_coreclk_mux>; /* core_clk */ 1487 assigned-clocks = <&icssg2_iepclk_mux>; 1488 assigned-clock-parents = <&icssg2_coreclk_mux>; 1489 }; 1490 }; 1491 }; 1492 1493 icssg2_iep0: iep@2e000 { 1494 compatible = "ti,am654-icss-iep"; 1495 reg = <0x2e000 0x1000>; 1496 clocks = <&icssg2_iepclk_mux>; 1497 }; 1498 1499 icssg2_iep1: iep@2f000 { 1500 compatible = "ti,am654-icss-iep"; 1501 reg = <0x2f000 0x1000>; 1502 clocks = <&icssg2_iepclk_mux>; 1503 }; 1504 1505 icssg2_mii_rt: mii-rt@32000 { 1506 compatible = "ti,pruss-mii", "syscon"; 1507 reg = <0x32000 0x100>; 1508 }; 1509 1510 icssg2_mii_g_rt: mii-g-rt@33000 { 1511 compatible = "ti,pruss-mii-g", "syscon"; 1512 reg = <0x33000 0x1000>; 1513 }; 1514 1515 icssg2_pa_stats: pa-stats@2c000 { 1516 compatible = "ti,pruss-pa-st", "syscon"; 1517 reg = <0x2c000 0x1000>; 1518 }; 1519 1520 icssg2_intc: interrupt-controller@20000 { 1521 compatible = "ti,icssg-intc"; 1522 reg = <0x20000 0x2000>; 1523 interrupt-controller; 1524 #interrupt-cells = <3>; 1525 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1533 interrupt-names = "host_intr0", "host_intr1", 1534 "host_intr2", "host_intr3", 1535 "host_intr4", "host_intr5", 1536 "host_intr6", "host_intr7"; 1537 }; 1538 1539 pru2_0: pru@34000 { 1540 compatible = "ti,am654-pru"; 1541 reg = <0x34000 0x4000>, 1542 <0x22000 0x100>, 1543 <0x22400 0x100>; 1544 reg-names = "iram", "control", "debug"; 1545 firmware-name = "am65x-pru2_0-fw"; 1546 interrupt-parent = <&icssg2_intc>; 1547 interrupts = <16 2 2>; 1548 interrupt-names = "vring"; 1549 }; 1550 1551 rtu2_0: rtu@4000 { 1552 compatible = "ti,am654-rtu"; 1553 reg = <0x4000 0x2000>, 1554 <0x23000 0x100>, 1555 <0x23400 0x100>; 1556 reg-names = "iram", "control", "debug"; 1557 firmware-name = "am65x-rtu2_0-fw"; 1558 interrupt-parent = <&icssg2_intc>; 1559 interrupts = <20 4 4>; 1560 interrupt-names = "vring"; 1561 }; 1562 1563 tx_pru2_0: txpru@a000 { 1564 compatible = "ti,am654-tx-pru"; 1565 reg = <0xa000 0x1800>, 1566 <0x25000 0x100>, 1567 <0x25400 0x100>; 1568 reg-names = "iram", "control", "debug"; 1569 firmware-name = "am65x-txpru2_0-fw"; 1570 }; 1571 1572 pru2_1: pru@38000 { 1573 compatible = "ti,am654-pru"; 1574 reg = <0x38000 0x4000>, 1575 <0x24000 0x100>, 1576 <0x24400 0x100>; 1577 reg-names = "iram", "control", "debug"; 1578 firmware-name = "am65x-pru2_1-fw"; 1579 interrupt-parent = <&icssg2_intc>; 1580 interrupts = <18 3 3>; 1581 interrupt-names = "vring"; 1582 }; 1583 1584 rtu2_1: rtu@6000 { 1585 compatible = "ti,am654-rtu"; 1586 reg = <0x6000 0x2000>, 1587 <0x23800 0x100>, 1588 <0x23c00 0x100>; 1589 reg-names = "iram", "control", "debug"; 1590 firmware-name = "am65x-rtu2_1-fw"; 1591 interrupt-parent = <&icssg2_intc>; 1592 interrupts = <22 5 5>; 1593 interrupt-names = "vring"; 1594 }; 1595 1596 tx_pru2_1: txpru@c000 { 1597 compatible = "ti,am654-tx-pru"; 1598 reg = <0xc000 0x1800>, 1599 <0x25800 0x100>, 1600 <0x25c00 0x100>; 1601 reg-names = "iram", "control", "debug"; 1602 firmware-name = "am65x-txpru2_1-fw"; 1603 }; 1604 1605 icssg2_mdio: mdio@32400 { 1606 compatible = "ti,davinci_mdio"; 1607 reg = <0x32400 0x100>; 1608 clocks = <&k3_clks 64 3>; 1609 clock-names = "fck"; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 bus_freq = <1000000>; 1613 status = "disabled"; 1614 }; 1615 }; 1616};
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