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k3-am642-sr-som.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> 4 * 5 */ 6 7#include <dt-bindings/net/ti-dp83869.h> 8 9/ { 10 model = "SolidRun AM642 SoM"; 11 compatible = "solidrun,am642-sr-som", "ti,am642"; 12 13 aliases { 14 ethernet0 = &cpsw_port1; 15 ethernet1 = &icssg1_emac0; 16 ethernet2 = &icssg1_emac1; 17 mmc0 = &sdhci0; 18 mmc1 = &sdhci1; 19 serial2 = &main_uart0; 20 }; 21 22 chosen { 23 /* SoC default UART console */ 24 stdout-path = "serial2:115200n8"; 25 }; 26 27 /* PRU Ethernet Controller */ 28 ethernet { 29 compatible = "ti,am642-icssg-prueth"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>; 32 33 sram = <&oc_sram>; 34 ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; 35 firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 36 "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 37 "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 38 "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 39 "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 40 "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; 41 42 /* configure internal pinmux for mii mode */ 43 ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>; 44 45 ti,mii-g-rt = <&icssg1_mii_g_rt>; 46 ti,mii-rt = <&icssg1_mii_rt>; 47 ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; 48 49 /* 50 * Configure icssg interrupt controller to map pru-internal 51 * interrupts 8/9 via channels 0/1 to host interrupts 0/1. 52 * 53 * For details see interrupt controller documentation: 54 * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml 55 */ 56 interrupt-parent = <&icssg1_intc>; 57 interrupts = <24 0 2>, <25 1 3>; 58 interrupt-names = "tx_ts0", "tx_ts1"; 59 60 dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ 61 <&main_pktdma 0xc201 15>, /* egress slice 0 */ 62 <&main_pktdma 0xc202 15>, /* egress slice 0 */ 63 <&main_pktdma 0xc203 15>, /* egress slice 0 */ 64 <&main_pktdma 0xc204 15>, /* egress slice 1 */ 65 <&main_pktdma 0xc205 15>, /* egress slice 1 */ 66 <&main_pktdma 0xc206 15>, /* egress slice 1 */ 67 <&main_pktdma 0xc207 15>, /* egress slice 1 */ 68 <&main_pktdma 0x4200 15>, /* ingress slice 0 */ 69 <&main_pktdma 0x4201 15>; /* ingress slice 1 */ 70 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", 71 "tx1-0", "tx1-1", "tx1-2", "tx1-3", 72 "rx0", "rx1"; 73 74 ethernet-ports { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 icssg1_emac0: port@0 { 79 reg = <0>; 80 ti,syscon-rgmii-delay = <&main_conf 0x4110>; 81 /* Filled in by bootloader */ 82 local-mac-address = [00 00 00 00 00 00]; 83 phy-handle = <ðernet_phy2>; 84 phy-mode = "rgmii-id"; 85 }; 86 87 icssg1_emac1: port@1 { 88 reg = <1>; 89 ti,syscon-rgmii-delay = <&main_conf 0x4114>; 90 /* Filled in by bootloader */ 91 local-mac-address = [00 00 00 00 00 00]; 92 phy-handle = <ðernet_phy1>; 93 phy-mode = "rgmii-id"; 94 }; 95 }; 96 }; 97 98 /* DDR16SS0: 99 * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space 100 * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space 101 */ 102 memory@80000000 { 103 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 104 <0x00000008 0x80000000 0x00000001 0x80000000>; 105 device_type = "memory"; 106 }; 107 108 reserved_memory: reserved-memory { 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 secure_ddr: optee@9e800000 { 114 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 115 no-map; 116 }; 117 118 main_r5fss0_core0_dma_memory_region: memory@a0000000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa0000000 0x00 0x100000>; 121 no-map; 122 }; 123 124 main_r5fss0_core0_memory_region: memory@a0100000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa0100000 0x00 0xf00000>; 127 no-map; 128 }; 129 }; 130 131 vdd_mmc0: regulator-vdd-mmc0 { 132 compatible = "regulator-fixed"; 133 regulator-name = "vdd-mmc0"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <1800000>; 136 regulator-always-on; 137 regulator-boot-on; 138 }; 139}; 140 141&cpsw3g { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&rgmii1_default_pins>; 144 status = "okay"; 145}; 146 147&cpsw3g_mdio { 148 pinctrl-names = "default"; 149 pinctrl-0 = <&mdio0_default_pins>; 150 status = "okay"; 151 152 ethernet_phy0: ethernet-phy@0 { 153 compatible = "ethernet-phy-id2000.a0f1"; 154 reg = <0>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <ðernet_phy0_default_pins>; 157 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; 158 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 159 /* 160 * Disable interrupts because ISR never clears 0x0040 161 * 162 * interrupt-parent = <&main_gpio1>; 163 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 164 */ 165 /* 166 * Disable HW Reset because clock signal is daisy-chained 167 * 168 * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>; 169 * reset-assert-us = <1>; 170 * reset-deassert-us = <30>; 171 */ 172 }; 173}; 174 175&cpsw_port1 { 176 phy-mode = "rgmii-id"; 177 phy-handle = <ðernet_phy0>; 178 status = "okay"; 179}; 180 181&icssg1_mdio { 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pru1_mdio0_default_pins>; 184 status = "okay"; 185 186 ethernet_phy1: ethernet-phy@3 { 187 compatible = "ethernet-phy-id2000.a0f1"; 188 reg = <3>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <ðernet_phy1_default_pins>; 191 ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; 192 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 193 /* 194 * Disable interrupts because ISR never clears 0x0040 195 * 196 * interrupt-parent = <&main_gpio1>; 197 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 198 */ 199 /* 200 * Disable HW Reset because clock signal is daisy-chained 201 * 202 * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; 203 * reset-assert-us = <1>; 204 * reset-deassert-us = <30>; 205 */ 206 }; 207 208 ethernet_phy2: ethernet-phy@f { 209 compatible = "ethernet-phy-id2000.a0f1"; 210 reg = <0xf>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <ðernet_phy2_default_pins>; 213 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; 214 /* 215 * Disable interrupts because ISR never clears 0x0040 216 * 217 * interrupt-parent = <&main_gpio1>; 218 * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; 219 */ 220 /* 221 * Disable HW Reset because clock signal is daisy-chained 222 * 223 * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>; 224 * reset-assert-us = <1>; 225 * reset-deassert-us = <30>; 226 */ 227 }; 228}; 229 230&main_i2c0 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&main_i2c0_default_pins>; 233 status = "okay"; 234 235 som_eeprom: eeprom@50 { 236 compatible = "atmel,24c01"; 237 reg = <0x50>; 238 pagesize = <8>; 239 }; 240}; 241 242&main_pmx0 { 243 /* hog global functions */ 244 pinctrl-names = "default"; 245 pinctrl-0 = <ðernet_phy_default_pins>; 246 247 ethernet_phy_default_pins: ethernet-phy-default-pins { 248 pinctrl-single,pins = < 249 /* interrupt / power-down, external pull-up on SoM */ 250 AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */ 251 >; 252 }; 253 254 ethernet_phy0_default_pins: ethernet-phy0-default-pins { 255 pinctrl-single,pins = < 256 /* reset */ 257 AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */ 258 /* reference clock */ 259 AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */ 260 >; 261 }; 262 263 ethernet_phy1_default_pins: ethernet-phy1-default-pins { 264 pinctrl-single,pins = < 265 /* reset */ 266 AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */ 267 /* led0, external pull-down on SoM */ 268 AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */ 269 /* led1/rxer */ 270 AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */ 271 >; 272 }; 273 274 ethernet_phy2_default_pins: ethernet-phy2-default-pins { 275 pinctrl-single,pins = < 276 /* reset */ 277 AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */ 278 /* led0, external pull-down on SoM */ 279 AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */ 280 /* led1/rxer */ 281 AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */ 282 >; 283 }; 284 285 main_i2c0_default_pins: main-i2c0-default-pins { 286 pinctrl-single,pins = < 287 /* external pull-up on SoM */ 288 AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */ 289 AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */ 290 >; 291 }; 292 293 /* 294 * main_mmc0_default_pins: main-mmc0-default-pins 295 * 296 * MMC0_CMD: no padconfig 297 * MMC0_CLK: no padconfig, external pull-up on SoM 298 * MMC0_DAT0: no padconfig 299 * MMC0_DAT1: no padconfig 300 * MMC0_DAT2: no padconfig 301 * MMC0_DAT3: no padconfig 302 * MMC0_DAT4: no padconfig 303 * MMC0_DAT5: no padconfig 304 * MMC0_DAT6: no padconfig 305 * MMC0_DAT7: no padconfig 306 * MMC0_DS: no padconfig, external pull-down on SoM 307 */ 308 309 main_mmc1_default_pins: main-mmc1-default-pins { 310 pinctrl-single,pins = < 311 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 312 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */ 313 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */ 314 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */ 315 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */ 316 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */ 317 /* external pull-down on SoM & Carrier */ 318 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */ 319 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */ 320 >; 321 }; 322 323 main_uart0_default_pins: main-uart0-default-pins { 324 pinctrl-single,pins = < 325 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */ 326 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */ 327 >; 328 }; 329 330 mdio0_default_pins: mdio0-default-pins { 331 pinctrl-single,pins = < 332 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */ 333 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */ 334 >; 335 }; 336 337 ospi0_default_pins: ospi0-default-pins { 338 pinctrl-single,pins = < 339 /* external pull-down on SoM */ 340 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */ 341 AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */ 342 /* external pull-up on SoM */ 343 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */ 344 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */ 345 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */ 346 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */ 347 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */ 348 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */ 349 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */ 350 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */ 351 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */ 352 >; 353 }; 354 355 ospi0_flash0_default_pins: ospi0-flash0-default-pins { 356 pinctrl-single,pins = < 357 AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */ 358 AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */ 359 >; 360 }; 361 362 pru1_mdio0_default_pins: pru1-mdio0-default-pins { 363 pinctrl-single,pins = < 364 AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */ 365 AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */ 366 >; 367 }; 368 369 pru_rgmii1_default_pins: pru-rgmii1-default-pins { 370 pinctrl-single,pins = < 371 AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 372 AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 373 AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 374 AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 375 AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 376 AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 377 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ 378 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ 379 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ 380 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ 381 AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 382 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ 383 >; 384 }; 385 386 pru_rgmii2_default_pins: pru-rgmii2-default-pins { 387 pinctrl-single,pins = < 388 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */ 389 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */ 390 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */ 391 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */ 392 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */ 393 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 394 AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */ 395 AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */ 396 AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */ 397 AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */ 398 AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */ 399 AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 400 >; 401 }; 402 403 rgmii1_default_pins: rgmii1-default-pins { 404 pinctrl-single,pins = < 405 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */ 406 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */ 407 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */ 408 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */ 409 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */ 410 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 411 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */ 412 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */ 413 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */ 414 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */ 415 AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */ 416 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 417 >; 418 }; 419 420 usb0_default_pins: usb0-default-pins { 421 pinctrl-single,pins = < 422 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ 423 >; 424 }; 425}; 426 427/* SoC default UART console */ 428&main_uart0 { 429 pinctrl-names = "default"; 430 pinctrl-0 = <&main_uart0_default_pins>; 431 status = "okay"; 432}; 433 434&ospi0 { 435 pinctrl-names = "default"; 436 pinctrl-0 = <&ospi0_default_pins>; 437 num-cs = <1>; 438 status = "okay"; 439 440 flash@0 { 441 compatible = "jedec,spi-nor"; 442 reg = <0>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&ospi0_flash0_default_pins>; 445 spi-tx-bus-width = <8>; 446 spi-rx-bus-width = <8>; 447 spi-max-frequency = <200000000>; 448 cdns,tshsl-ns = <50>; 449 cdns,tsd2d-ns = <50>; 450 cdns,tchsh-ns = <4>; 451 cdns,tslch-ns = <4>; 452 cdns,read-delay = <0>; 453 interrupt-parent = <&main_gpio0>; 454 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 455 reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>; 456 }; 457}; 458 459&sdhci0 { 460 /* mmc0 pins have no padconfig */ 461 bus-width = <8>; 462 ti,driver-strength-ohm = <50>; 463 disable-wp; 464 non-removable; 465 cap-mmc-hw-reset; 466 no-sd; 467 /* 468 * MMC controller supports switching between 1.8V and 3.3V signalling. 469 * However MMC0 (unlike MMC1) does not integrate an LDO. 470 * Explicitly link a regulator node for indicating to the driver which 471 * voltages are actually usable. 472 */ 473 vqmmc-supply = <&vdd_mmc0>; 474 status = "okay"; 475}; 476 477/* 478 * microSD is on carrier - however since SoC can boot from it, 479 * configure it just in case. 480 */ 481&sdhci1 { 482 pinctrl-names = "default"; 483 pinctrl-0 = <&main_mmc1_default_pins>; 484 bus-width = <4>; 485 ti,driver-strength-ohm = <50>; 486 disable-wp; 487 status = "okay"; 488}; 489 490/* 491 * USB settings are a carrier choice - however since SoC can boot from it, 492 * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled. 493 */ 494&usb0 { 495 pinctrl-names = "default"; 496 pinctrl-0 = <&usb0_default_pins>; 497 dr_mode = "otg"; 498 maximum-speed = "high-speed"; 499}; 500 501&usbss0 { 502 ti,vbus-divider; 503 ti,usb2-only; 504}; 505 506#include "k3-am64-ti-ipc-firmware.dtsi"
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