k3-am642-phyboard-electra-peb-c-010.dtso

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Copyright (C) 2025 PHYTEC America LLC
  4 * Author: Garrett Giordano <ggiordano@phytec.com>
  5 */
  6
  7/dts-v1/;
  8/plugin/;
  9
 10#include <dt-bindings/net/ti-dp83869.h>
 11#include "k3-pinctrl.h"
 12
 13&{/} {
 14	aliases {
 15		ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0";
 16		ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1";
 17	};
 18
 19	icssg1-ethernet {
 20		compatible = "ti,am642-icssg-prueth";
 21		pinctrl-names = "default";
 22		pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
 23
 24		dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
 25				<&main_pktdma 0xc201 15>, /* egress slice 0 */
 26				<&main_pktdma 0xc202 15>, /* egress slice 0 */
 27				<&main_pktdma 0xc203 15>, /* egress slice 0 */
 28				<&main_pktdma 0xc204 15>, /* egress slice 1 */
 29				<&main_pktdma 0xc205 15>, /* egress slice 1 */
 30				<&main_pktdma 0xc206 15>, /* egress slice 1 */
 31				<&main_pktdma 0xc207 15>, /* egress slice 1 */
 32				<&main_pktdma 0x4200 15>, /* ingress slice 0 */
 33				<&main_pktdma 0x4201 15>; /* ingress slice 1 */
 34		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
 35					"tx1-0", "tx1-1", "tx1-2", "tx1-3",
 36					"rx0", "rx1";
 37
 38		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
 39				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
 40				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
 41				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
 42				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
 43				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
 44
 45		interrupt-parent = <&icssg1_intc>;
 46		interrupts = <24 0 2>, <25 1 3>;
 47		interrupt-names = "tx_ts0", "tx_ts1";
 48		sram = <&oc_sram>;
 49
 50		ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
 51		ti,mii-g-rt = <&icssg1_mii_g_rt>;
 52		ti,mii-rt = <&icssg1_mii_rt>;
 53		ti,pa-stats = <&icssg1_pa_stats>;
 54		ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
 55		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
 56				      <2>,
 57				      <2>,
 58				      <2>,	/* MII mode */
 59				      <2>,
 60				      <2>;
 61
 62		ethernet-ports {
 63			#address-cells = <1>;
 64			#size-cells = <0>;
 65			icssg1_emac0: port@0 {
 66				reg = <0>;
 67				phy-handle = <&icssg1_phy1>;
 68				phy-mode = "rgmii-id";
 69				/* Filled in by bootloader */
 70				local-mac-address = [00 00 00 00 00 00];
 71				ti,syscon-rgmii-delay = <&main_conf 0x4110>;
 72			};
 73
 74			icssg1_emac1: port@1 {
 75				reg = <1>;
 76				phy-handle = <&icssg1_phy2>;
 77				phy-mode = "rgmii-id";
 78				/* Filled in by bootloader */
 79				local-mac-address = [00 00 00 00 00 00];
 80				ti,syscon-rgmii-delay = <&main_conf 0x4114>;
 81			};
 82		};
 83	};
 84};
 85
 86&main_pmx0 {
 87	icssg1_mdio_pins_default: icssg1-mdio-default-pins {
 88		pinctrl-single,pins = <
 89			AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
 90			AM64X_IOPAD(0x0158, PIN_INPUT, 0)  /* (AA6) PRG1_MDIO0_MDIO */
 91		>;
 92	};
 93
 94	icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
 95		pinctrl-single,pins = <
 96			AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
 97			AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
 98			AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
 99			AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
100			AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
101			AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
102			AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
103			AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
104			AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
105			AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
106			AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
107			AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
108		>;
109	};
110
111	icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
112		pinctrl-single,pins = <
113			AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
114			AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
115			AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
116			AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
117			AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
118			AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
119			AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */
120			AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */
121			AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */
122			AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */
123			AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */
124			AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
125		>;
126	};
127};
128
129&icssg1_mdio {
130	pinctrl-names = "default";
131	pinctrl-0 = <&icssg1_mdio_pins_default>;
132	#address-cells = <1>;
133	#size-cells = <0>;
134	status = "okay";
135
136	icssg1_phy1: ethernet-phy@1 {
137		reg = <0x1>;
138		rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
139		tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
140		rx-internal-delay-ps = <2000>;
141		tx-internal-delay-ps = <2000>;
142		ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
143		ti,min-output-impedance;
144	};
145
146	icssg1_phy2: ethernet-phy@2 {
147		reg = <0x2>;
148		rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
149		tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
150		rx-internal-delay-ps = <2000>;
151		tx-internal-delay-ps = <2000>;
152		ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
153		ti,min-output-impedance;
154	};
155};