k3-am64.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for AM642 SoC Family
  4 *
  5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/interrupt-controller/irq.h>
 10#include <dt-bindings/interrupt-controller/arm-gic.h>
 11#include <dt-bindings/soc/ti,sci_pm_domain.h>
 12
 13#include "k3-pinctrl.h"
 14
 15/ {
 16	model = "Texas Instruments K3 AM642 SoC";
 17	compatible = "ti,am642";
 18	interrupt-parent = <&gic500>;
 19	#address-cells = <2>;
 20	#size-cells = <2>;
 21
 22	chosen { };
 23
 24	firmware {
 25		optee {
 26			compatible = "linaro,optee-tz";
 27			method = "smc";
 28		};
 29
 30		psci: psci {
 31			compatible = "arm,psci-1.0";
 32			method = "smc";
 33		};
 34	};
 35
 36	a53_timer0: timer-cl0-cpu0 {
 37		compatible = "arm,armv8-timer";
 38		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 39			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 40			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 41			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 42	};
 43
 44	pmu: pmu {
 45		compatible = "arm,cortex-a53-pmu";
 46		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 47	};
 48
 49	cbass_main: bus@f4000 {
 50		bootph-all;
 51		compatible = "simple-bus";
 52		#address-cells = <2>;
 53		#size-cells = <2>;
 54		ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
 55			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
 56			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
 57			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
 58			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
 59			 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
 60			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 61			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
 62			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
 63			 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
 64			 <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
 65			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
 66			 <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
 67			 <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
 68			 <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
 69			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
 70			 <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
 71			 <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
 72			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
 73			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
 74			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
 75			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
 76			 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
 77			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
 78			 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
 79			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
 80			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
 81			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
 82			 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
 83			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
 84
 85			 /* MCU Domain Range */
 86			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
 87
 88		cbass_mcu: bus@4000000 {
 89			bootph-all;
 90			compatible = "simple-bus";
 91			#address-cells = <2>;
 92			#size-cells = <2>;
 93			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
 94		};
 95	};
 96
 97	#include "k3-am64-thermal.dtsi"
 98};
 99
100/* Now include the peripherals for each bus segments */
101#include "k3-am64-main.dtsi"
102#include "k3-am64-mcu.dtsi"