k3-am62p5.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree file for the AM62P5 SoC family (quad core)
  4 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  5 *
  6 * TRM: https://www.ti.com/lit/pdf/spruj83
  7 */
  8
  9/dts-v1/;
 10
 11#include "k3-am62p.dtsi"
 12
 13/ {
 14	cpus {
 15		#address-cells = <1>;
 16		#size-cells = <0>;
 17
 18		cpu-map {
 19			cluster0: cluster0 {
 20				core0 {
 21					cpu = <&cpu0>;
 22				};
 23
 24				core1 {
 25					cpu = <&cpu1>;
 26				};
 27
 28				core2 {
 29					cpu = <&cpu2>;
 30				};
 31
 32				core3 {
 33					cpu = <&cpu3>;
 34				};
 35			};
 36		};
 37
 38		cpu0: cpu@0 {
 39			compatible = "arm,cortex-a53";
 40			reg = <0x000>;
 41			device_type = "cpu";
 42			enable-method = "psci";
 43			i-cache-size = <0x8000>;
 44			i-cache-line-size = <64>;
 45			i-cache-sets = <256>;
 46			d-cache-size = <0x8000>;
 47			d-cache-line-size = <64>;
 48			d-cache-sets = <128>;
 49			next-level-cache = <&l2_0>;
 50			operating-points-v2 = <&a53_opp_table>;
 51			clocks = <&k3_clks 135 0>;
 52			#cooling-cells = <2>;
 53		};
 54
 55		cpu1: cpu@1 {
 56			compatible = "arm,cortex-a53";
 57			reg = <0x001>;
 58			device_type = "cpu";
 59			enable-method = "psci";
 60			i-cache-size = <0x8000>;
 61			i-cache-line-size = <64>;
 62			i-cache-sets = <256>;
 63			d-cache-size = <0x8000>;
 64			d-cache-line-size = <64>;
 65			d-cache-sets = <128>;
 66			next-level-cache = <&l2_0>;
 67			operating-points-v2 = <&a53_opp_table>;
 68			clocks = <&k3_clks 136 0>;
 69			#cooling-cells = <2>;
 70		};
 71
 72		cpu2: cpu@2 {
 73			compatible = "arm,cortex-a53";
 74			reg = <0x002>;
 75			device_type = "cpu";
 76			enable-method = "psci";
 77			i-cache-size = <0x8000>;
 78			i-cache-line-size = <64>;
 79			i-cache-sets = <256>;
 80			d-cache-size = <0x8000>;
 81			d-cache-line-size = <64>;
 82			d-cache-sets = <128>;
 83			next-level-cache = <&l2_0>;
 84			operating-points-v2 = <&a53_opp_table>;
 85			clocks = <&k3_clks 137 0>;
 86			#cooling-cells = <2>;
 87		};
 88
 89		cpu3: cpu@3 {
 90			compatible = "arm,cortex-a53";
 91			reg = <0x003>;
 92			device_type = "cpu";
 93			enable-method = "psci";
 94			i-cache-size = <0x8000>;
 95			i-cache-line-size = <64>;
 96			i-cache-sets = <256>;
 97			d-cache-size = <0x8000>;
 98			d-cache-line-size = <64>;
 99			d-cache-sets = <128>;
100			next-level-cache = <&l2_0>;
101			operating-points-v2 = <&a53_opp_table>;
102			clocks = <&k3_clks 138 0>;
103			#cooling-cells = <2>;
104		};
105	};
106
107	a53_opp_table: opp-table {
108		compatible = "operating-points-v2-ti-cpu";
109		opp-shared;
110		syscon = <&opp_efuse_table>;
111
112		opp-200000000 {
113			opp-hz = /bits/ 64 <200000000>;
114			opp-supported-hw = <0x01 0x0007>;
115			clock-latency-ns = <6000000>;
116		};
117
118		opp-400000000 {
119			opp-hz = /bits/ 64 <400000000>;
120			opp-supported-hw = <0x01 0x0007>;
121			clock-latency-ns = <6000000>;
122		};
123
124		opp-600000000 {
125			opp-hz = /bits/ 64 <600000000>;
126			opp-supported-hw = <0x01 0x0007>;
127			clock-latency-ns = <6000000>;
128		};
129
130		opp-800000000 {
131			opp-hz = /bits/ 64 <800000000>;
132			opp-supported-hw = <0x01 0x0007>;
133			clock-latency-ns = <6000000>;
134		};
135
136		opp-1000000000 {
137			opp-hz = /bits/ 64 <1000000000>;
138			opp-supported-hw = <0x01 0x0007>;
139			clock-latency-ns = <6000000>;
140		};
141
142		opp-1250000000 {
143			opp-hz = /bits/ 64 <1250000000>;
144			opp-supported-hw = <0x01 0x0004>;
145			clock-latency-ns = <6000000>;
146			opp-suspend;
147		};
148	};
149
150	l2_0: l2-cache0 {
151		compatible = "cache";
152		cache-unified;
153		cache-level = <2>;
154		cache-size = <0x80000>;
155		cache-line-size = <64>;
156		cache-sets = <512>;
157	};
158};