k3-am62p.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for AM62P SoC Family
  4 *
  5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/interrupt-controller/irq.h>
 10#include <dt-bindings/interrupt-controller/arm-gic.h>
 11#include <dt-bindings/soc/ti,sci_pm_domain.h>
 12
 13#include "k3-pinctrl.h"
 14
 15/ {
 16	model = "Texas Instruments K3 AM62P5 SoC";
 17	compatible = "ti,am62p5";
 18	interrupt-parent = <&gic500>;
 19	#address-cells = <2>;
 20	#size-cells = <2>;
 21
 22	firmware {
 23		optee {
 24			compatible = "linaro,optee-tz";
 25			method = "smc";
 26		};
 27
 28		psci: psci {
 29			compatible = "arm,psci-1.0";
 30			method = "smc";
 31		};
 32	};
 33
 34	a53_timer0: timer-cl0-cpu0 {
 35		compatible = "arm,armv8-timer";
 36		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 37			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 38			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 39			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 40	};
 41
 42	pmu: pmu {
 43		compatible = "arm,cortex-a53-pmu";
 44		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 45	};
 46
 47	system-idle-states {
 48		system_partial_io: system-partial-io {
 49			compatible = "system-idle-state";
 50			idle-state-name = "off-wake";
 51		};
 52
 53		system_io_ddr: system-io-ddr {
 54			compatible = "system-idle-state";
 55			idle-state-name = "mem-deep";
 56		};
 57
 58		system_deep_sleep: system-deep-sleep {
 59			compatible = "system-idle-state";
 60			idle-state-name = "mem";
 61		};
 62
 63		system_mcu_only: system-mcu-only {
 64			compatible = "system-idle-state";
 65			idle-state-name = "mem-mcu-active";
 66		};
 67
 68		system_standby: system-standby {
 69			compatible = "system-idle-state";
 70			idle-state-name = "standby";
 71		};
 72	};
 73
 74	cbass_main: bus@f0000 {
 75		compatible = "simple-bus";
 76		#address-cells = <2>;
 77		#size-cells = <2>;
 78		bootph-all;
 79
 80		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
 81			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
 82			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
 83			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
 84			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
 85			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
 86			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
 87			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 88			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
 89			 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
 90			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
 91			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
 92			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
 93			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
 94			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
 95			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
 96			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
 97			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
 98			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
 99			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
100			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
101			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
102			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
103			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
104			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
105			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
106
107			 /* MCU Domain Range */
108			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
109			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
110			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
111			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
112			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
113
114			 /* Wakeup Domain Range */
115			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
116			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
117			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
118			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
119			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
120
121		cbass_mcu: bus@4000000 {
122			compatible = "simple-bus";
123			#address-cells = <2>;
124			#size-cells = <2>;
125			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
126				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
127				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
128				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
129				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
130			bootph-all;
131		};
132
133		cbass_wakeup: bus@b00000 {
134			compatible = "simple-bus";
135			#address-cells = <2>;
136			#size-cells = <2>;
137			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
138				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
139				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
140				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
141				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
142			bootph-all;
143		};
144	};
145
146	#include "k3-am62p-j722s-common-thermal.dtsi"
147};
148
149/* Now include peripherals for each bus segment */
150#include "k3-am62p-j722s-common-main.dtsi"
151#include "k3-am62p-j722s-common-mcu.dtsi"
152#include "k3-am62p-j722s-common-wakeup.dtsi"
153
154/* Include AM62P specific peripherals */
155#include "k3-am62p-main.dtsi"