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k3-am62p-j722s-common-main.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S 4 * 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 }; 14 15 gic500: interrupt-controller@1800000 { 16 compatible = "arm,gic-v3"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 #interrupt-cells = <3>; 21 interrupt-controller; 22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 24 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 25 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 26 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 27 /* 28 * vcpumntirq: 29 * virtual CPU interface maintenance interrupt 30 */ 31 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 32 33 gic_its: msi-controller@1820000 { 34 compatible = "arm,gic-v3-its"; 35 reg = <0x00 0x01820000 0x00 0x10000>; 36 socionext,synquacer-pre-its = <0x1000000 0x400000>; 37 msi-controller; 38 #msi-cells = <1>; 39 }; 40 }; 41 42 main_conf: bus@100000 { 43 compatible = "simple-bus"; 44 reg = <0x00 0x00100000 0x00 0x20000>; 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges = <0x00 0x00 0x00100000 0x20000>; 48 49 audio_refclk0: clock-controller@82e0 { 50 compatible = "ti,am62-audio-refclk"; 51 reg = <0x82e0 0x4>; 52 clocks = <&k3_clks 157 0>; 53 assigned-clocks = <&k3_clks 157 0>; 54 assigned-clock-parents = <&k3_clks 157 16>; 55 #clock-cells = <0>; 56 }; 57 58 audio_refclk1: clock-controller@82e4 { 59 compatible = "ti,am62-audio-refclk"; 60 reg = <0x82e4 0x4>; 61 clocks = <&k3_clks 157 18>; 62 assigned-clocks = <&k3_clks 157 18>; 63 assigned-clock-parents = <&k3_clks 157 34>; 64 #clock-cells = <0>; 65 }; 66 67 phy_gmii_sel: phy@4044 { 68 compatible = "ti,am654-phy-gmii-sel"; 69 reg = <0x4044 0x8>; 70 #phy-cells = <1>; 71 }; 72 73 epwm_tbclk: clock-controller@4130 { 74 compatible = "ti,am62-epwm-tbclk"; 75 reg = <0x4130 0x4>; 76 #clock-cells = <1>; 77 }; 78 }; 79 80 dmss: bus@48000000 { 81 compatible = "simple-bus"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 dma-ranges; 85 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 86 bootph-all; 87 88 ti,sci-dev-id = <25>; 89 90 secure_proxy_main: mailbox@4d000000 { 91 compatible = "ti,am654-secure-proxy"; 92 #mbox-cells = <1>; 93 reg-names = "target_data", "rt", "scfg"; 94 reg = <0x00 0x4d000000 0x00 0x80000>, 95 <0x00 0x4a600000 0x00 0x80000>, 96 <0x00 0x4a400000 0x00 0x80000>; 97 interrupt-names = "rx_012"; 98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 99 bootph-all; 100 }; 101 102 inta_main_dmss: interrupt-controller@48000000 { 103 compatible = "ti,sci-inta"; 104 reg = <0x00 0x48000000 0x00 0x100000>; 105 #interrupt-cells = <0>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 msi-controller; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <28>; 111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 112 }; 113 114 main_bcdma: dma-controller@485c0100 { 115 compatible = "ti,am64-dmss-bcdma"; 116 reg = <0x00 0x485c0100 0x00 0x100>, 117 <0x00 0x4c000000 0x00 0x20000>, 118 <0x00 0x4a820000 0x00 0x20000>, 119 <0x00 0x4aa40000 0x00 0x20000>, 120 <0x00 0x4bc00000 0x00 0x100000>, 121 <0x00 0x48600000 0x00 0x8000>, 122 <0x00 0x484a4000 0x00 0x2000>, 123 <0x00 0x484c2000 0x00 0x2000>, 124 <0x00 0x48420000 0x00 0x2000>; 125 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 126 "ring", "tchan", "rchan", "bchan"; 127 msi-parent = <&inta_main_dmss>; 128 #dma-cells = <3>; 129 130 ti,sci = <&dmsc>; 131 ti,sci-dev-id = <26>; 132 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 133 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 134 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 135 bootph-all; 136 }; 137 138 main_pktdma: dma-controller@485c0000 { 139 compatible = "ti,am64-dmss-pktdma"; 140 reg = <0x00 0x485c0000 0x00 0x100>, 141 <0x00 0x4a800000 0x00 0x20000>, 142 <0x00 0x4aa00000 0x00 0x20000>, 143 <0x00 0x4b800000 0x00 0x200000>, 144 <0x00 0x485e0000 0x00 0x10000>, 145 <0x00 0x484a0000 0x00 0x2000>, 146 <0x00 0x484c0000 0x00 0x2000>, 147 <0x00 0x48430000 0x00 0x1000>; 148 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 149 "ring", "tchan", "rchan", "rflow"; 150 msi-parent = <&inta_main_dmss>; 151 #dma-cells = <2>; 152 bootph-all; 153 154 ti,sci = <&dmsc>; 155 ti,sci-dev-id = <30>; 156 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 157 <0x24>, /* CPSW_TX_CHAN */ 158 <0x25>, /* SAUL_TX_0_CHAN */ 159 <0x26>; /* SAUL_TX_1_CHAN */ 160 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 161 <0x11>, /* RING_CPSW_TX_CHAN */ 162 <0x12>, /* RING_SAUL_TX_0_CHAN */ 163 <0x13>; /* RING_SAUL_TX_1_CHAN */ 164 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 165 <0x2b>, /* CPSW_RX_CHAN */ 166 <0x2d>, /* SAUL_RX_0_CHAN */ 167 <0x2f>, /* SAUL_RX_1_CHAN */ 168 <0x31>, /* SAUL_RX_2_CHAN */ 169 <0x33>; /* SAUL_RX_3_CHAN */ 170 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 171 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 172 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 173 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 174 }; 175 }; 176 177 dmss_csi: bus@4e000000 { 178 compatible = "simple-bus"; 179 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 dma-ranges; 183 ti,sci-dev-id = <198>; 184 185 inta_main_dmss_csi: interrupt-controller@4e400000 { 186 compatible = "ti,sci-inta"; 187 reg = <0x00 0x4e400000 0x00 0x8000>; 188 #interrupt-cells = <0>; 189 interrupt-controller; 190 interrupt-parent = <&gic500>; 191 msi-controller; 192 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 193 ti,sci = <&dmsc>; 194 ti,sci-dev-id = <200>; 195 ti,interrupt-ranges = <0 237 8>; 196 ti,unmapped-event-sources = <&main_bcdma_csi>; 197 }; 198 199 main_bcdma_csi: dma-controller@4e230000 { 200 compatible = "ti,am62a-dmss-bcdma-csirx"; 201 reg = <0x00 0x4e230000 0x00 0x100>, 202 <0x00 0x4e180000 0x00 0x8000>, 203 <0x00 0x4e100000 0x00 0x10000>; 204 reg-names = "gcfg", "rchanrt", "ringrt"; 205 #dma-cells = <3>; 206 msi-parent = <&inta_main_dmss_csi>; 207 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 208 ti,sci = <&dmsc>; 209 ti,sci-dev-id = <199>; 210 ti,sci-rm-range-rchan = <0x21>; 211 }; 212 }; 213 214 dmsc: system-controller@44043000 { 215 compatible = "ti,k2g-sci"; 216 ti,host-id = <12>; 217 mbox-names = "rx", "tx"; 218 mboxes = <&secure_proxy_main 12>, 219 <&secure_proxy_main 13>; 220 reg-names = "debug_messages"; 221 reg = <0x00 0x44043000 0x00 0xfe0>; 222 bootph-all; 223 224 k3_pds: power-controller { 225 compatible = "ti,sci-pm-domain"; 226 #power-domain-cells = <2>; 227 bootph-all; 228 }; 229 230 k3_clks: clock-controller { 231 compatible = "ti,k2g-sci-clk"; 232 #clock-cells = <2>; 233 bootph-all; 234 }; 235 236 k3_reset: reset-controller { 237 compatible = "ti,sci-reset"; 238 #reset-cells = <2>; 239 bootph-all; 240 }; 241 }; 242 243 crypto: crypto@40900000 { 244 compatible = "ti,am62-sa3ul"; 245 reg = <0x00 0x40900000 0x00 0x1200>; 246 #address-cells = <2>; 247 #size-cells = <2>; 248 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 249 250 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 251 <&main_pktdma 0x7507 0>; 252 dma-names = "tx", "rx1", "rx2"; 253 254 rng: rng@40910000 { 255 compatible = "inside-secure,safexcel-eip76"; 256 reg = <0x00 0x40910000 0x0 0x7d>; 257 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 258 status = "reserved"; 259 }; 260 }; 261 262 secure_proxy_sa3: mailbox@43600000 { 263 compatible = "ti,am654-secure-proxy"; 264 #mbox-cells = <1>; 265 reg-names = "target_data", "rt", "scfg"; 266 reg = <0x00 0x43600000 0x00 0x10000>, 267 <0x00 0x44880000 0x00 0x20000>, 268 <0x00 0x44860000 0x00 0x20000>; 269 /* 270 * Marked Disabled: 271 * Node is incomplete as it is meant for bootloaders and 272 * firmware on non-MPU processors 273 */ 274 status = "disabled"; 275 bootph-all; 276 }; 277 278 main_pmx0: pinctrl@f4000 { 279 compatible = "pinctrl-single"; 280 reg = <0x00 0xf4000 0x00 0x2b0>; 281 #pinctrl-cells = <1>; 282 pinctrl-single,register-width = <32>; 283 pinctrl-single,function-mask = <0xffffffff>; 284 bootph-all; 285 }; 286 287 main_esm: esm@420000 { 288 compatible = "ti,j721e-esm"; 289 reg = <0x00 0x420000 0x00 0x1000>; 290 bootph-pre-ram; 291 /* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */ 292 ti,esm-pins = <224>, <225>, <227>, <241>, <242>, <248>; 293 }; 294 295 main_timer0: timer@2400000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x2400000 0x00 0x400>; 298 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 36 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 36 2>; 302 assigned-clock-parents = <&k3_clks 36 3>; 303 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 bootph-all; 306 }; 307 308 main_timer1: timer@2410000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2410000 0x00 0x400>; 311 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 37 2>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 37 2>; 315 assigned-clock-parents = <&k3_clks 37 3>; 316 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer2: timer@2420000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2420000 0x00 0x400>; 323 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 38 2>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 38 2>; 327 assigned-clock-parents = <&k3_clks 38 3>; 328 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer3: timer@2430000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x2430000 0x00 0x400>; 335 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 39 2>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 39 2>; 339 assigned-clock-parents = <&k3_clks 39 3>; 340 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_timer4: timer@2440000 { 345 compatible = "ti,am654-timer"; 346 reg = <0x00 0x2440000 0x00 0x400>; 347 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&k3_clks 40 2>; 349 clock-names = "fck"; 350 assigned-clocks = <&k3_clks 40 2>; 351 assigned-clock-parents = <&k3_clks 40 3>; 352 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 353 ti,timer-pwm; 354 }; 355 356 main_timer5: timer@2450000 { 357 compatible = "ti,am654-timer"; 358 reg = <0x00 0x2450000 0x00 0x400>; 359 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&k3_clks 41 2>; 361 clock-names = "fck"; 362 assigned-clocks = <&k3_clks 41 2>; 363 assigned-clock-parents = <&k3_clks 41 3>; 364 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 365 ti,timer-pwm; 366 }; 367 368 main_timer6: timer@2460000 { 369 compatible = "ti,am654-timer"; 370 reg = <0x00 0x2460000 0x00 0x400>; 371 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&k3_clks 42 2>; 373 clock-names = "fck"; 374 assigned-clocks = <&k3_clks 42 2>; 375 assigned-clock-parents = <&k3_clks 42 3>; 376 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 377 ti,timer-pwm; 378 }; 379 380 main_timer7: timer@2470000 { 381 compatible = "ti,am654-timer"; 382 reg = <0x00 0x2470000 0x00 0x400>; 383 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&k3_clks 43 2>; 385 clock-names = "fck"; 386 assigned-clocks = <&k3_clks 43 2>; 387 assigned-clock-parents = <&k3_clks 43 3>; 388 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 389 ti,timer-pwm; 390 }; 391 392 main_uart0: serial@2800000 { 393 compatible = "ti,am64-uart", "ti,am654-uart"; 394 reg = <0x00 0x02800000 0x00 0x100>; 395 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 396 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 397 clocks = <&k3_clks 146 0>; 398 clock-names = "fclk"; 399 status = "disabled"; 400 }; 401 402 main_uart1: serial@2810000 { 403 compatible = "ti,am64-uart", "ti,am654-uart"; 404 reg = <0x00 0x02810000 0x00 0x100>; 405 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 406 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 152 0>; 408 clock-names = "fclk"; 409 status = "disabled"; 410 }; 411 412 main_uart2: serial@2820000 { 413 compatible = "ti,am64-uart", "ti,am654-uart"; 414 reg = <0x00 0x02820000 0x00 0x100>; 415 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 416 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 417 clocks = <&k3_clks 153 0>; 418 clock-names = "fclk"; 419 status = "disabled"; 420 }; 421 422 main_uart3: serial@2830000 { 423 compatible = "ti,am64-uart", "ti,am654-uart"; 424 reg = <0x00 0x02830000 0x00 0x100>; 425 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 426 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 154 0>; 428 clock-names = "fclk"; 429 status = "disabled"; 430 }; 431 432 main_uart4: serial@2840000 { 433 compatible = "ti,am64-uart", "ti,am654-uart"; 434 reg = <0x00 0x02840000 0x00 0x100>; 435 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 436 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 437 clocks = <&k3_clks 155 0>; 438 clock-names = "fclk"; 439 status = "disabled"; 440 }; 441 442 main_uart5: serial@2850000 { 443 compatible = "ti,am64-uart", "ti,am654-uart"; 444 reg = <0x00 0x02850000 0x00 0x100>; 445 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 446 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 447 clocks = <&k3_clks 156 0>; 448 clock-names = "fclk"; 449 status = "disabled"; 450 }; 451 452 main_uart6: serial@2860000 { 453 compatible = "ti,am64-uart", "ti,am654-uart"; 454 reg = <0x00 0x02860000 0x00 0x100>; 455 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 456 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 158 0>; 458 clock-names = "fclk"; 459 status = "disabled"; 460 }; 461 462 main_i2c0: i2c@20000000 { 463 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 464 reg = <0x00 0x20000000 0x00 0x100>; 465 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 469 clocks = <&k3_clks 102 2>; 470 clock-names = "fck"; 471 status = "disabled"; 472 }; 473 474 main_i2c1: i2c@20010000 { 475 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 476 reg = <0x00 0x20010000 0x00 0x100>; 477 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 481 clocks = <&k3_clks 103 2>; 482 clock-names = "fck"; 483 status = "disabled"; 484 }; 485 486 main_i2c2: i2c@20020000 { 487 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 488 reg = <0x00 0x20020000 0x00 0x100>; 489 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 493 clocks = <&k3_clks 104 2>; 494 clock-names = "fck"; 495 status = "disabled"; 496 }; 497 498 main_i2c3: i2c@20030000 { 499 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 500 reg = <0x00 0x20030000 0x00 0x100>; 501 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 105 2>; 506 clock-names = "fck"; 507 status = "disabled"; 508 }; 509 510 main_spi0: spi@20100000 { 511 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 512 reg = <0x00 0x20100000 0x00 0x400>; 513 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 517 clocks = <&k3_clks 141 0>; 518 status = "disabled"; 519 }; 520 521 main_spi1: spi@20110000 { 522 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 523 reg = <0x00 0x20110000 0x00 0x400>; 524 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 142 0>; 529 status = "disabled"; 530 }; 531 532 main_spi2: spi@20120000 { 533 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 534 reg = <0x00 0x20120000 0x00 0x400>; 535 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 539 clocks = <&k3_clks 143 0>; 540 status = "disabled"; 541 }; 542 543 main_gpio_intr: interrupt-controller@a00000 { 544 compatible = "ti,sci-intr"; 545 reg = <0x00 0x00a00000 0x00 0x800>; 546 ti,intr-trigger-type = <1>; 547 interrupt-controller; 548 interrupt-parent = <&gic500>; 549 #interrupt-cells = <1>; 550 ti,sci = <&dmsc>; 551 ti,sci-dev-id = <3>; 552 ti,interrupt-ranges = <0 32 16>; 553 }; 554 555 main_gpio0: gpio@600000 { 556 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 557 reg = <0x00 0x00600000 0x00 0x100>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 interrupt-parent = <&main_gpio_intr>; 561 interrupts = <190>, <191>, <192>, 562 <193>, <194>, <195>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 ti,davinci-gpio-unbanked = <0>; 566 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 567 clocks = <&k3_clks 77 0>; 568 clock-names = "gpio"; 569 }; 570 571 main_gpio1: gpio@601000 { 572 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 573 reg = <0x00 0x00601000 0x00 0x100>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-parent = <&main_gpio_intr>; 577 interrupts = <180>, <181>, <182>, 578 <183>, <184>, <185>; 579 interrupt-controller; 580 #interrupt-cells = <2>; 581 ti,davinci-gpio-unbanked = <0>; 582 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 583 clocks = <&k3_clks 78 0>; 584 clock-names = "gpio"; 585 }; 586 587 sdhci0: mmc@fa10000 { 588 compatible = "ti,am64-sdhci-8bit"; 589 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 590 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 591 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 592 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; 593 clock-names = "clk_ahb", "clk_xin"; 594 bus-width = <8>; 595 mmc-ddr-1_8v; 596 mmc-hs200-1_8v; 597 ti,clkbuf-sel = <0x7>; 598 ti,trm-icp = <0x8>; 599 ti,otap-del-sel-legacy = <0x1>; 600 ti,otap-del-sel-mmc-hs = <0x1>; 601 ti,otap-del-sel-ddr52 = <0x6>; 602 ti,otap-del-sel-hs200 = <0x8>; 603 ti,itap-del-sel-legacy = <0x10>; 604 ti,itap-del-sel-mmc-hs = <0xa>; 605 ti,itap-del-sel-ddr52 = <0x3>; 606 status = "disabled"; 607 }; 608 609 sdhci1: mmc@fa00000 { 610 compatible = "ti,am62-sdhci"; 611 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 612 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 613 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 614 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 615 clock-names = "clk_ahb", "clk_xin"; 616 bus-width = <4>; 617 ti,clkbuf-sel = <0x7>; 618 ti,otap-del-sel-legacy = <0x0>; 619 ti,otap-del-sel-sd-hs = <0x0>; 620 ti,otap-del-sel-sdr12 = <0xf>; 621 ti,otap-del-sel-sdr25 = <0xf>; 622 ti,otap-del-sel-sdr50 = <0xc>; 623 ti,otap-del-sel-ddr50 = <0x9>; 624 ti,otap-del-sel-sdr104 = <0x6>; 625 ti,itap-del-sel-legacy = <0x0>; 626 ti,itap-del-sel-sd-hs = <0x0>; 627 ti,itap-del-sel-sdr12 = <0x0>; 628 ti,itap-del-sel-sdr25 = <0x0>; 629 status = "disabled"; 630 }; 631 632 sdhci2: mmc@fa20000 { 633 compatible = "ti,am62-sdhci"; 634 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 635 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 636 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 637 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 638 clock-names = "clk_ahb", "clk_xin"; 639 bus-width = <4>; 640 ti,clkbuf-sel = <0x7>; 641 ti,otap-del-sel-legacy = <0x0>; 642 ti,otap-del-sel-sd-hs = <0x0>; 643 ti,otap-del-sel-sdr12 = <0xf>; 644 ti,otap-del-sel-sdr25 = <0xf>; 645 ti,otap-del-sel-sdr50 = <0xc>; 646 ti,otap-del-sel-ddr50 = <0x9>; 647 ti,otap-del-sel-sdr104 = <0x6>; 648 ti,itap-del-sel-legacy = <0x0>; 649 ti,itap-del-sel-sd-hs = <0x0>; 650 ti,itap-del-sel-sdr12 = <0x0>; 651 ti,itap-del-sel-sdr25 = <0x0>; 652 status = "disabled"; 653 }; 654 655 usbss0: usb@f900000 { 656 compatible = "ti,am62-usb"; 657 reg = <0x00 0x0f900000 0x00 0x800>, 658 <0x00 0x0f908000 0x00 0x400>; 659 clocks = <&k3_clks 161 3>; 660 clock-names = "ref"; 661 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 662 #address-cells = <2>; 663 #size-cells = <2>; 664 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 665 ranges; 666 status = "disabled"; 667 668 usb0: usb@31000000 { 669 compatible = "snps,dwc3"; 670 reg = <0x00 0x31000000 0x00 0x50000>; 671 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 672 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 673 interrupt-names = "host", "peripheral"; 674 maximum-speed = "high-speed"; 675 dr_mode = "otg"; 676 bootph-all; 677 snps,usb2-gadget-lpm-disable; 678 snps,usb2-lpm-disable; 679 }; 680 }; 681 682 fss: bus@fc00000 { 683 compatible = "simple-bus"; 684 reg = <0x00 0x0fc00000 0x00 0x70000>; 685 #address-cells = <2>; 686 #size-cells = <2>; 687 ranges; 688 689 ospi0: spi@fc40000 { 690 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 691 reg = <0x00 0x0fc40000 0x00 0x100>, 692 <0x05 0x00000000 0x01 0x00000000>; 693 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 694 cdns,fifo-depth = <256>; 695 cdns,fifo-width = <4>; 696 cdns,trigger-address = <0x0>; 697 clocks = <&k3_clks 75 7>; 698 assigned-clocks = <&k3_clks 75 7>; 699 assigned-clock-parents = <&k3_clks 75 8>; 700 assigned-clock-rates = <166666666>; 701 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 }; 707 708 cpsw3g: ethernet@8000000 { 709 compatible = "ti,am642-cpsw-nuss"; 710 #address-cells = <2>; 711 #size-cells = <2>; 712 reg = <0x00 0x08000000 0x00 0x200000>; 713 reg-names = "cpsw_nuss"; 714 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 715 clocks = <&k3_clks 13 0>; 716 assigned-clocks = <&k3_clks 13 3>; 717 assigned-clock-parents = <&k3_clks 13 11>; 718 clock-names = "fck"; 719 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 720 status = "disabled"; 721 722 dmas = <&main_pktdma 0xc600 15>, 723 <&main_pktdma 0xc601 15>, 724 <&main_pktdma 0xc602 15>, 725 <&main_pktdma 0xc603 15>, 726 <&main_pktdma 0xc604 15>, 727 <&main_pktdma 0xc605 15>, 728 <&main_pktdma 0xc606 15>, 729 <&main_pktdma 0xc607 15>, 730 <&main_pktdma 0x4600 15>; 731 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 732 "tx7", "rx"; 733 734 ethernet-ports { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 cpsw_port1: port@1 { 739 reg = <1>; 740 ti,mac-only; 741 label = "port1"; 742 phys = <&phy_gmii_sel 1>; 743 mac-address = [00 00 00 00 00 00]; 744 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 745 status = "disabled"; 746 }; 747 748 cpsw_port2: port@2 { 749 reg = <2>; 750 ti,mac-only; 751 label = "port2"; 752 phys = <&phy_gmii_sel 2>; 753 mac-address = [00 00 00 00 00 00]; 754 status = "disabled"; 755 }; 756 }; 757 758 cpsw3g_mdio: mdio@f00 { 759 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 760 reg = <0x00 0xf00 0x00 0x100>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 clocks = <&k3_clks 13 0>; 764 clock-names = "fck"; 765 bus_freq = <1000000>; 766 status = "disabled"; 767 }; 768 769 cpts@3d000 { 770 compatible = "ti,j721e-cpts"; 771 reg = <0x00 0x3d000 0x00 0x400>; 772 clocks = <&k3_clks 13 3>; 773 clock-names = "cpts"; 774 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 775 interrupt-names = "cpts"; 776 ti,cpts-ext-ts-inputs = <4>; 777 ti,cpts-periodic-outputs = <2>; 778 }; 779 }; 780 781 hwspinlock: spinlock@2a000000 { 782 compatible = "ti,am64-hwspinlock"; 783 reg = <0x00 0x2a000000 0x00 0x1000>; 784 #hwlock-cells = <1>; 785 }; 786 787 mailbox0_cluster0: mailbox@29000000 { 788 compatible = "ti,am64-mailbox"; 789 reg = <0x00 0x29000000 0x00 0x200>; 790 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 791 #mbox-cells = <1>; 792 ti,mbox-num-users = <4>; 793 ti,mbox-num-fifos = <16>; 794 status = "disabled"; 795 }; 796 797 mailbox0_cluster1: mailbox@29010000 { 798 compatible = "ti,am64-mailbox"; 799 reg = <0x00 0x29010000 0x00 0x200>; 800 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 801 #mbox-cells = <1>; 802 ti,mbox-num-users = <4>; 803 ti,mbox-num-fifos = <16>; 804 status = "disabled"; 805 }; 806 807 mailbox0_cluster2: mailbox@29020000 { 808 compatible = "ti,am64-mailbox"; 809 reg = <0x00 0x29020000 0x00 0x200>; 810 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 811 #mbox-cells = <1>; 812 ti,mbox-num-users = <4>; 813 ti,mbox-num-fifos = <16>; 814 status = "disabled"; 815 }; 816 817 mailbox0_cluster3: mailbox@29030000 { 818 compatible = "ti,am64-mailbox"; 819 reg = <0x00 0x29030000 0x00 0x200>; 820 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 821 #mbox-cells = <1>; 822 ti,mbox-num-users = <4>; 823 ti,mbox-num-fifos = <16>; 824 status = "disabled"; 825 }; 826 827 ecap0: pwm@23100000 { 828 compatible = "ti,am3352-ecap"; 829 #pwm-cells = <3>; 830 reg = <0x00 0x23100000 0x00 0x100>; 831 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 832 clocks = <&k3_clks 51 0>; 833 clock-names = "fck"; 834 status = "disabled"; 835 }; 836 837 ecap1: pwm@23110000 { 838 compatible = "ti,am3352-ecap"; 839 #pwm-cells = <3>; 840 reg = <0x00 0x23110000 0x00 0x100>; 841 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 842 clocks = <&k3_clks 52 0>; 843 clock-names = "fck"; 844 status = "disabled"; 845 }; 846 847 ecap2: pwm@23120000 { 848 compatible = "ti,am3352-ecap"; 849 #pwm-cells = <3>; 850 reg = <0x00 0x23120000 0x00 0x100>; 851 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 852 clocks = <&k3_clks 53 0>; 853 clock-names = "fck"; 854 status = "disabled"; 855 }; 856 857 eqep0: counter@23200000 { 858 compatible = "ti,am62-eqep"; 859 reg = <0x00 0x23200000 0x00 0x100>; 860 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 861 clocks = <&k3_clks 59 0>; 862 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 863 status = "disabled"; 864 }; 865 866 eqep1: counter@23210000 { 867 compatible = "ti,am62-eqep"; 868 reg = <0x00 0x23210000 0x00 0x100>; 869 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 870 clocks = <&k3_clks 60 0>; 871 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 872 status = "disabled"; 873 }; 874 875 eqep2: counter@23220000 { 876 compatible = "ti,am62-eqep"; 877 reg = <0x00 0x23220000 0x00 0x100>; 878 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 879 clocks = <&k3_clks 62 0>; 880 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 881 status = "disabled"; 882 }; 883 884 main_mcan0: can@20701000 { 885 compatible = "bosch,m_can"; 886 reg = <0x00 0x20701000 0x00 0x200>, 887 <0x00 0x20708000 0x00 0x8000>; 888 reg-names = "m_can", "message_ram"; 889 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 890 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 891 clock-names = "hclk", "cclk"; 892 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 894 interrupt-names = "int0", "int1"; 895 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 896 status = "disabled"; 897 }; 898 899 main_mcan1: can@20711000 { 900 compatible = "bosch,m_can"; 901 reg = <0x00 0x20711000 0x00 0x200>, 902 <0x00 0x20718000 0x00 0x8000>; 903 reg-names = "m_can", "message_ram"; 904 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 905 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; 906 clock-names = "hclk", "cclk"; 907 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "int0", "int1"; 910 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 911 status = "disabled"; 912 }; 913 914 main_rti0: watchdog@e000000 { 915 compatible = "ti,j7-rti-wdt"; 916 reg = <0x00 0x0e000000 0x00 0x100>; 917 clocks = <&k3_clks 125 0>; 918 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 919 assigned-clocks = <&k3_clks 125 0>; 920 assigned-clock-parents = <&k3_clks 125 2>; 921 }; 922 923 main_rti1: watchdog@e010000 { 924 compatible = "ti,j7-rti-wdt"; 925 reg = <0x00 0x0e010000 0x00 0x100>; 926 clocks = <&k3_clks 126 0>; 927 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 928 assigned-clocks = <&k3_clks 126 0>; 929 assigned-clock-parents = <&k3_clks 126 2>; 930 }; 931 932 main_rti2: watchdog@e020000 { 933 compatible = "ti,j7-rti-wdt"; 934 reg = <0x00 0x0e020000 0x00 0x100>; 935 clocks = <&k3_clks 127 0>; 936 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 937 assigned-clocks = <&k3_clks 127 0>; 938 assigned-clock-parents = <&k3_clks 127 2>; 939 }; 940 941 main_rti3: watchdog@e030000 { 942 compatible = "ti,j7-rti-wdt"; 943 reg = <0x00 0x0e030000 0x00 0x100>; 944 clocks = <&k3_clks 128 0>; 945 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 946 assigned-clocks = <&k3_clks 128 0>; 947 assigned-clock-parents = <&k3_clks 128 2>; 948 }; 949 950 main_rti15: watchdog@e0f0000 { 951 compatible = "ti,j7-rti-wdt"; 952 reg = <0x00 0x0e0f0000 0x00 0x100>; 953 clocks = <&k3_clks 130 0>; 954 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 955 assigned-clocks = <&k3_clks 130 0>; 956 assigned-clock-parents = <&k3_clks 130 2>; 957 }; 958 959 epwm0: pwm@23000000 { 960 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 961 #pwm-cells = <3>; 962 reg = <0x00 0x23000000 0x00 0x100>; 963 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 964 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 965 clock-names = "tbclk", "fck"; 966 status = "disabled"; 967 }; 968 969 epwm1: pwm@23010000 { 970 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 971 #pwm-cells = <3>; 972 reg = <0x00 0x23010000 0x00 0x100>; 973 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 974 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 975 clock-names = "tbclk", "fck"; 976 status = "disabled"; 977 }; 978 979 epwm2: pwm@23020000 { 980 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 981 #pwm-cells = <3>; 982 reg = <0x00 0x23020000 0x00 0x100>; 983 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 985 clock-names = "tbclk", "fck"; 986 status = "disabled"; 987 }; 988 989 mcasp0: audio-controller@2b00000 { 990 compatible = "ti,am33xx-mcasp-audio"; 991 reg = <0x00 0x02b00000 0x00 0x2000>, 992 <0x00 0x02b08000 0x00 0x400>; 993 reg-names = "mpu", "dat"; 994 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 996 interrupt-names = "tx", "rx"; 997 998 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 999 dma-names = "tx", "rx"; 1000 1001 clocks = <&k3_clks 190 0>; 1002 clock-names = "fck"; 1003 assigned-clocks = <&k3_clks 190 0>; 1004 assigned-clock-parents = <&k3_clks 190 2>; 1005 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1006 status = "disabled"; 1007 }; 1008 1009 mcasp1: audio-controller@2b10000 { 1010 compatible = "ti,am33xx-mcasp-audio"; 1011 reg = <0x00 0x02b10000 0x00 0x2000>, 1012 <0x00 0x02b18000 0x00 0x400>; 1013 reg-names = "mpu", "dat"; 1014 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1016 interrupt-names = "tx", "rx"; 1017 1018 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1019 dma-names = "tx", "rx"; 1020 1021 clocks = <&k3_clks 191 0>; 1022 clock-names = "fck"; 1023 assigned-clocks = <&k3_clks 191 0>; 1024 assigned-clock-parents = <&k3_clks 191 2>; 1025 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1026 status = "disabled"; 1027 }; 1028 1029 mcasp2: audio-controller@2b20000 { 1030 compatible = "ti,am33xx-mcasp-audio"; 1031 reg = <0x00 0x02b20000 0x00 0x2000>, 1032 <0x00 0x02b28000 0x00 0x400>; 1033 reg-names = "mpu", "dat"; 1034 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1036 interrupt-names = "tx", "rx"; 1037 1038 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1039 dma-names = "tx", "rx"; 1040 1041 clocks = <&k3_clks 192 0>; 1042 clock-names = "fck"; 1043 assigned-clocks = <&k3_clks 192 0>; 1044 assigned-clock-parents = <&k3_clks 192 2>; 1045 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1046 status = "disabled"; 1047 }; 1048 1049 ti_csi2rx0: ticsi2rx@30102000 { 1050 compatible = "ti,j721e-csi2rx-shim"; 1051 reg = <0x00 0x30102000 0x00 0x1000>; 1052 ranges; 1053 #address-cells = <2>; 1054 #size-cells = <2>; 1055 dmas = <&main_bcdma_csi 0 0x5000 0>; 1056 dma-names = "rx0"; 1057 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1058 status = "disabled"; 1059 1060 cdns_csi2rx0: csi-bridge@30101000 { 1061 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1062 reg = <0x00 0x30101000 0x00 0x1000>; 1063 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1065 interrupt-names = "error_irq", "irq"; 1066 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1067 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1068 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1069 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1070 phys = <&dphy0>; 1071 phy-names = "dphy"; 1072 1073 ports { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 1077 csi0_port0: port@0 { 1078 reg = <0>; 1079 status = "disabled"; 1080 }; 1081 1082 csi0_port1: port@1 { 1083 reg = <1>; 1084 status = "disabled"; 1085 }; 1086 1087 csi0_port2: port@2 { 1088 reg = <2>; 1089 status = "disabled"; 1090 }; 1091 1092 csi0_port3: port@3 { 1093 reg = <3>; 1094 status = "disabled"; 1095 }; 1096 1097 csi0_port4: port@4 { 1098 reg = <4>; 1099 status = "disabled"; 1100 }; 1101 }; 1102 }; 1103 }; 1104 1105 dphy0: phy@30110000 { 1106 compatible = "cdns,dphy-rx"; 1107 reg = <0x00 0x30110000 0x00 0x1100>; 1108 #phy-cells = <0>; 1109 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1110 status = "disabled"; 1111 }; 1112 1113 vpu: video-codec@30210000 { 1114 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1115 reg = <0x00 0x30210000 0x00 0x10000>; 1116 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&k3_clks 204 2>; 1118 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1119 }; 1120};
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