k3-am62a-wakeup.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
  4 *
  5 * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/bus/ti-sysc.h>
  9
 10&cbass_wakeup {
 11	wkup_conf: bus@43000000 {
 12		compatible = "simple-bus";
 13		#address-cells = <1>;
 14		#size-cells = <1>;
 15		ranges = <0x00 0x00 0x43000000 0x20000>;
 16
 17		chipid: chipid@14 {
 18			compatible = "ti,am654-chipid";
 19			reg = <0x14 0x4>;
 20			bootph-all;
 21		};
 22
 23		opp_efuse_table: syscon@18 {
 24			compatible = "ti,am62-opp-efuse-table", "syscon";
 25			reg = <0x18 0x4>;
 26		};
 27
 28		cpsw_mac_syscon: ethernet-mac-syscon@200 {
 29			compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
 30			reg = <0x200 0x8>;
 31		};
 32
 33		usb0_phy_ctrl: syscon@4008 {
 34			compatible = "ti,am62-usb-phy-ctrl", "syscon";
 35			reg = <0x4008 0x4>;
 36		};
 37
 38		usb1_phy_ctrl: syscon@4018 {
 39			compatible = "ti,am62-usb-phy-ctrl", "syscon";
 40			reg = <0x4018 0x4>;
 41		};
 42	};
 43
 44	target-module@2b300050 {
 45		compatible = "ti,sysc-omap2", "ti,sysc";
 46		reg = <0 0x2b300050 0 0x4>,
 47		      <0 0x2b300054 0 0x4>,
 48		      <0 0x2b300058 0 0x4>;
 49		reg-names = "rev", "sysc", "syss";
 50		ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 51				 SYSC_OMAP2_SOFTRESET |
 52				 SYSC_OMAP2_AUTOIDLE)>;
 53		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 54				<SYSC_IDLE_NO>,
 55				<SYSC_IDLE_SMART>,
 56				<SYSC_IDLE_SMART_WKUP>;
 57		ti,syss-mask = <1>;
 58		ti,no-reset-on-init;
 59		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 60		clocks = <&k3_clks 114 0>;
 61		clock-names = "fck";
 62		#address-cells = <1>;
 63		#size-cells = <1>;
 64		ranges = <0 0 0x2b300000 0x100000>;
 65
 66		wkup_uart0: serial@0 {
 67			compatible = "ti,am64-uart", "ti,am654-uart";
 68			reg = <0 0x100>;
 69			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 70			status = "disabled";
 71			bootph-pre-ram;
 72	       };
 73	};
 74
 75	wkup_i2c0: i2c@2b200000 {
 76		compatible = "ti,am64-i2c", "ti,omap4-i2c";
 77		reg = <0x00 0x2b200000 0x00 0x100>;
 78		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 79		#address-cells = <1>;
 80		#size-cells = <0>;
 81		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 82		clocks = <&k3_clks 107 4>;
 83		clock-names = "fck";
 84		status = "disabled";
 85	};
 86
 87	wkup_rtc0: rtc@2b1f0000 {
 88		compatible = "ti,am62-rtc";
 89		reg = <0x00 0x2b1f0000 0x00 0x100>;
 90		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 91		clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
 92		clock-names = "vbus", "osc32k";
 93		power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
 94		wakeup-source;
 95	};
 96
 97	wkup_rti0: watchdog@2b000000 {
 98		compatible = "ti,j7-rti-wdt";
 99		reg = <0x00 0x2b000000 0x00 0x100>;
100		clocks = <&k3_clks 132 0>;
101		power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
102		assigned-clocks = <&k3_clks 132 0>;
103		assigned-clock-parents = <&k3_clks 132 2>;
104		/* Used by DM firmware */
105		status = "reserved";
106	};
107
108	wkup_r5fss0: r5fss@78000000 {
109		compatible = "ti,am62-r5fss";
110		#address-cells = <1>;
111		#size-cells = <1>;
112		ranges = <0x78000000 0x00 0x78000000 0x8000>,
113			 <0x78100000 0x00 0x78100000 0x8000>;
114		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
115		status = "disabled";
116
117		wkup_r5fss0_core0: r5f@78000000 {
118			compatible = "ti,am62-r5f";
119			reg = <0x78000000 0x00008000>,
120			      <0x78100000 0x00008000>;
121			reg-names = "atcm", "btcm";
122			resets = <&k3_reset 121 1>;
123			firmware-name = "am62a-wkup-r5f0_0-fw";
124			ti,atcm-enable = <1>;
125			ti,btcm-enable = <1>;
126			ti,loczrama = <1>;
127			ti,sci = <&dmsc>;
128			ti,sci-dev-id = <121>;
129			ti,sci-proc-ids = <0x01 0xff>;
130			status = "disabled";
131		};
132	};
133
134	wkup_vtm0: temperature-sensor@b00000 {
135		compatible = "ti,j7200-vtm";
136		reg = <0x00 0xb00000 0x00 0x400>,
137		      <0x00 0xb01000 0x00 0x400>;
138		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
139		#thermal-sensor-cells = <1>;
140	};
141};