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k3-am62a-main.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 22 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 23 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 #interrupt-cells = <3>; 28 interrupt-controller; 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: bus@100000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x00 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 bootph-all; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 63 audio_refclk0: clock-controller@82e0 { 64 compatible = "ti,am62-audio-refclk"; 65 reg = <0x82e0 0x4>; 66 clocks = <&k3_clks 157 0>; 67 assigned-clocks = <&k3_clks 157 0>; 68 assigned-clock-parents = <&k3_clks 157 8>; 69 #clock-cells = <0>; 70 }; 71 72 audio_refclk1: clock-controller@82e4 { 73 compatible = "ti,am62-audio-refclk"; 74 reg = <0x82e4 0x4>; 75 clocks = <&k3_clks 157 10>; 76 assigned-clocks = <&k3_clks 157 10>; 77 assigned-clock-parents = <&k3_clks 157 18>; 78 #clock-cells = <0>; 79 }; 80 }; 81 82 dmss: bus@48000000 { 83 compatible = "simple-bus"; 84 #address-cells = <2>; 85 #size-cells = <2>; 86 dma-ranges; 87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 88 89 ti,sci-dev-id = <25>; 90 91 secure_proxy_main: mailbox@4d000000 { 92 compatible = "ti,am654-secure-proxy"; 93 reg = <0x00 0x4d000000 0x00 0x80000>, 94 <0x00 0x4a600000 0x00 0x80000>, 95 <0x00 0x4a400000 0x00 0x80000>; 96 reg-names = "target_data", "rt", "scfg"; 97 #mbox-cells = <1>; 98 interrupt-names = "rx_012"; 99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 100 bootph-all; 101 }; 102 103 inta_main_dmss: interrupt-controller@48000000 { 104 compatible = "ti,sci-inta"; 105 reg = <0x00 0x48000000 0x00 0x100000>; 106 #interrupt-cells = <0>; 107 interrupt-controller; 108 interrupt-parent = <&gic500>; 109 msi-controller; 110 ti,sci = <&dmsc>; 111 ti,sci-dev-id = <28>; 112 ti,interrupt-ranges = <6 70 34>; 113 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 114 }; 115 116 main_bcdma: dma-controller@485c0100 { 117 compatible = "ti,am64-dmss-bcdma"; 118 reg = <0x00 0x485c0100 0x00 0x100>, 119 <0x00 0x4c000000 0x00 0x20000>, 120 <0x00 0x4a820000 0x00 0x20000>, 121 <0x00 0x4aa40000 0x00 0x20000>, 122 <0x00 0x4bc00000 0x00 0x100000>, 123 <0x00 0x48600000 0x00 0x8000>, 124 <0x00 0x484a4000 0x00 0x2000>, 125 <0x00 0x484c2000 0x00 0x2000>, 126 <0x00 0x48420000 0x00 0x2000>; 127 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 128 "ring", "tchan", "rchan", "bchan"; 129 msi-parent = <&inta_main_dmss>; 130 #dma-cells = <3>; 131 ti,sci = <&dmsc>; 132 ti,sci-dev-id = <26>; 133 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 134 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 135 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 136 bootph-all; 137 }; 138 139 main_pktdma: dma-controller@485c0000 { 140 compatible = "ti,am64-dmss-pktdma"; 141 reg = <0x00 0x485c0000 0x00 0x100>, 142 <0x00 0x4a800000 0x00 0x20000>, 143 <0x00 0x4aa00000 0x00 0x20000>, 144 <0x00 0x4b800000 0x00 0x200000>, 145 <0x00 0x485e0000 0x00 0x10000>, 146 <0x00 0x484a0000 0x00 0x2000>, 147 <0x00 0x484c0000 0x00 0x2000>, 148 <0x00 0x48430000 0x00 0x1000>; 149 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 150 "ring", "tchan", "rchan", "rflow"; 151 msi-parent = <&inta_main_dmss>; 152 #dma-cells = <2>; 153 bootph-all; 154 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <30>; 157 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 158 <0x24>, /* CPSW_TX_CHAN */ 159 <0x25>, /* SAUL_TX_0_CHAN */ 160 <0x26>; /* SAUL_TX_1_CHAN */ 161 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 162 <0x11>, /* RING_CPSW_TX_CHAN */ 163 <0x12>, /* RING_SAUL_TX_0_CHAN */ 164 <0x13>; /* RING_SAUL_TX_1_CHAN */ 165 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 166 <0x2b>, /* CPSW_RX_CHAN */ 167 <0x2d>, /* SAUL_RX_0_CHAN */ 168 <0x2f>, /* SAUL_RX_1_CHAN */ 169 <0x31>, /* SAUL_RX_2_CHAN */ 170 <0x33>; /* SAUL_RX_3_CHAN */ 171 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 172 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 173 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 174 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 175 }; 176 }; 177 178 dmss_csi: bus@4e000000 { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 dma-ranges; 183 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; 184 185 ti,sci-dev-id = <198>; 186 187 inta_main_dmss_csi: interrupt-controller@4e0a0000 { 188 compatible = "ti,sci-inta"; 189 reg = <0x00 0x4e0a0000 0x00 0x8000>; 190 #interrupt-cells = <0>; 191 interrupt-controller; 192 interrupt-parent = <&gic500>; 193 msi-controller; 194 ti,sci = <&dmsc>; 195 ti,sci-dev-id = <200>; 196 ti,interrupt-ranges = <0 237 8>; 197 ti,unmapped-event-sources = <&main_bcdma_csi>; 198 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 199 }; 200 201 main_bcdma_csi: dma-controller@4e230000 { 202 compatible = "ti,am62a-dmss-bcdma-csirx"; 203 reg = <0x00 0x4e230000 0x00 0x100>, 204 <0x00 0x4e180000 0x00 0x8000>, 205 <0x00 0x4e100000 0x00 0x10000>; 206 reg-names = "gcfg", "rchanrt", "ringrt"; 207 msi-parent = <&inta_main_dmss_csi>; 208 #dma-cells = <3>; 209 ti,sci = <&dmsc>; 210 ti,sci-dev-id = <199>; 211 ti,sci-rm-range-rchan = <0x21>; 212 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 213 }; 214 }; 215 216 dmsc: system-controller@44043000 { 217 compatible = "ti,k2g-sci"; 218 reg = <0x00 0x44043000 0x00 0xfe0>; 219 reg-names = "debug_messages"; 220 ti,host-id = <12>; 221 mbox-names = "rx", "tx"; 222 mboxes = <&secure_proxy_main 12>, 223 <&secure_proxy_main 13>; 224 225 k3_pds: power-controller { 226 compatible = "ti,sci-pm-domain"; 227 #power-domain-cells = <2>; 228 bootph-all; 229 }; 230 231 k3_clks: clock-controller { 232 compatible = "ti,k2g-sci-clk"; 233 #clock-cells = <2>; 234 bootph-all; 235 }; 236 237 k3_reset: reset-controller { 238 compatible = "ti,sci-reset"; 239 #reset-cells = <2>; 240 bootph-all; 241 }; 242 }; 243 244 crypto: crypto@40900000 { 245 compatible = "ti,am62-sa3ul"; 246 reg = <0x00 0x40900000 0x00 0x1200>; 247 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 248 <&main_pktdma 0x7507 0>; 249 dma-names = "tx", "rx1", "rx2"; 250 #address-cells = <2>; 251 #size-cells = <2>; 252 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 253 254 rng: rng@40910000 { 255 compatible = "inside-secure,safexcel-eip76"; 256 reg = <0x00 0x40910000 0x00 0x7d>; 257 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 258 status = "reserved"; /* Reserved for OP-TEE */ 259 }; 260 }; 261 262 secure_proxy_sa3: mailbox@43600000 { 263 compatible = "ti,am654-secure-proxy"; 264 #mbox-cells = <1>; 265 reg-names = "target_data", "rt", "scfg"; 266 reg = <0x00 0x43600000 0x00 0x10000>, 267 <0x00 0x44880000 0x00 0x20000>, 268 <0x00 0x44860000 0x00 0x20000>; 269 /* 270 * Marked Disabled: 271 * Node is incomplete as it is meant for bootloaders and 272 * firmware on non-MPU processors 273 */ 274 status = "disabled"; 275 bootph-all; 276 }; 277 278 main_pmx0: pinctrl@f4000 { 279 compatible = "pinctrl-single"; 280 reg = <0x00 0xf4000 0x00 0x25c>; 281 #pinctrl-cells = <1>; 282 pinctrl-single,register-width = <32>; 283 pinctrl-single,function-mask = <0xffffffff>; 284 }; 285 286 main_esm: esm@420000 { 287 compatible = "ti,j721e-esm"; 288 reg = <0x0 0x420000 0x0 0x1000>; 289 bootph-pre-ram; 290 /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */ 291 ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>; 292 }; 293 294 main_timer0: timer@2400000 { 295 compatible = "ti,am654-timer"; 296 reg = <0x00 0x2400000 0x00 0x400>; 297 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&k3_clks 36 2>; 299 clock-names = "fck"; 300 assigned-clocks = <&k3_clks 36 2>; 301 assigned-clock-parents = <&k3_clks 36 3>; 302 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 303 ti,timer-pwm; 304 bootph-all; 305 }; 306 307 main_timer1: timer@2410000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x2410000 0x00 0x400>; 310 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 37 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 37 2>; 314 assigned-clock-parents = <&k3_clks 37 3>; 315 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer2: timer@2420000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x2420000 0x00 0x400>; 322 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 38 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 38 2>; 326 assigned-clock-parents = <&k3_clks 38 3>; 327 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer3: timer@2430000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x2430000 0x00 0x400>; 334 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 39 2>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 39 2>; 338 assigned-clock-parents = <&k3_clks 39 3>; 339 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer4: timer@2440000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x2440000 0x00 0x400>; 346 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 40 2>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 40 2>; 350 assigned-clock-parents = <&k3_clks 40 3>; 351 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer5: timer@2450000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x2450000 0x00 0x400>; 358 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 41 2>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 41 2>; 362 assigned-clock-parents = <&k3_clks 41 3>; 363 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer6: timer@2460000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x2460000 0x00 0x400>; 370 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 42 2>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 42 2>; 374 assigned-clock-parents = <&k3_clks 42 3>; 375 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer7: timer@2470000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x2470000 0x00 0x400>; 382 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 43 2>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 43 2>; 386 assigned-clock-parents = <&k3_clks 43 3>; 387 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_uart0: serial@2800000 { 392 compatible = "ti,am64-uart", "ti,am654-uart"; 393 reg = <0x00 0x02800000 0x00 0x100>; 394 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 395 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 396 clocks = <&k3_clks 146 0>; 397 clock-names = "fclk"; 398 status = "disabled"; 399 }; 400 401 main_uart1: serial@2810000 { 402 compatible = "ti,am64-uart", "ti,am654-uart"; 403 reg = <0x00 0x02810000 0x00 0x100>; 404 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 405 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 152 0>; 407 clock-names = "fclk"; 408 status = "disabled"; 409 }; 410 411 main_uart2: serial@2820000 { 412 compatible = "ti,am64-uart", "ti,am654-uart"; 413 reg = <0x00 0x02820000 0x00 0x100>; 414 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 415 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 153 0>; 417 clock-names = "fclk"; 418 status = "disabled"; 419 }; 420 421 main_uart3: serial@2830000 { 422 compatible = "ti,am64-uart", "ti,am654-uart"; 423 reg = <0x00 0x02830000 0x00 0x100>; 424 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 425 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 154 0>; 427 clock-names = "fclk"; 428 status = "disabled"; 429 }; 430 431 main_uart4: serial@2840000 { 432 compatible = "ti,am64-uart", "ti,am654-uart"; 433 reg = <0x00 0x02840000 0x00 0x100>; 434 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 435 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 155 0>; 437 clock-names = "fclk"; 438 status = "disabled"; 439 }; 440 441 main_uart5: serial@2850000 { 442 compatible = "ti,am64-uart", "ti,am654-uart"; 443 reg = <0x00 0x02850000 0x00 0x100>; 444 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 445 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 156 0>; 447 clock-names = "fclk"; 448 status = "disabled"; 449 }; 450 451 main_uart6: serial@2860000 { 452 compatible = "ti,am64-uart", "ti,am654-uart"; 453 reg = <0x00 0x02860000 0x00 0x100>; 454 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 455 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 158 0>; 457 clock-names = "fclk"; 458 status = "disabled"; 459 }; 460 461 main_i2c0: i2c@20000000 { 462 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 463 reg = <0x00 0x20000000 0x00 0x100>; 464 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 468 clocks = <&k3_clks 102 2>; 469 clock-names = "fck"; 470 status = "disabled"; 471 }; 472 473 main_i2c1: i2c@20010000 { 474 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 475 reg = <0x00 0x20010000 0x00 0x100>; 476 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 103 2>; 481 clock-names = "fck"; 482 status = "disabled"; 483 }; 484 485 main_i2c2: i2c@20020000 { 486 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 487 reg = <0x00 0x20020000 0x00 0x100>; 488 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 492 clocks = <&k3_clks 104 2>; 493 clock-names = "fck"; 494 status = "disabled"; 495 }; 496 497 main_i2c3: i2c@20030000 { 498 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 499 reg = <0x00 0x20030000 0x00 0x100>; 500 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 105 2>; 505 clock-names = "fck"; 506 status = "disabled"; 507 }; 508 509 main_spi0: spi@20100000 { 510 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 511 reg = <0x00 0x20100000 0x00 0x400>; 512 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 516 clocks = <&k3_clks 141 0>; 517 status = "disabled"; 518 }; 519 520 main_spi1: spi@20110000 { 521 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 522 reg = <0x00 0x20110000 0x00 0x400>; 523 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 527 clocks = <&k3_clks 142 0>; 528 status = "disabled"; 529 }; 530 531 main_spi2: spi@20120000 { 532 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 533 reg = <0x00 0x20120000 0x00 0x400>; 534 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 538 clocks = <&k3_clks 143 0>; 539 status = "disabled"; 540 }; 541 542 main_gpio_intr: interrupt-controller@a00000 { 543 compatible = "ti,sci-intr"; 544 reg = <0x00 0x00a00000 0x00 0x800>; 545 ti,intr-trigger-type = <1>; 546 interrupt-controller; 547 interrupt-parent = <&gic500>; 548 #interrupt-cells = <1>; 549 ti,sci = <&dmsc>; 550 ti,sci-dev-id = <3>; 551 ti,interrupt-ranges = <0 32 16>; 552 status = "disabled"; 553 }; 554 555 main_gpio0: gpio@600000 { 556 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 557 reg = <0x00 0x00600000 0x0 0x100>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 interrupt-parent = <&main_gpio_intr>; 561 interrupts = <190>, <191>, <192>, 562 <193>, <194>, <195>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 ti,ngpio = <92>; 566 ti,davinci-gpio-unbanked = <0>; 567 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 568 clocks = <&k3_clks 77 0>; 569 clock-names = "gpio"; 570 status = "disabled"; 571 }; 572 573 main_gpio1: gpio@601000 { 574 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 575 reg = <0x00 0x00601000 0x0 0x100>; 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-parent = <&main_gpio_intr>; 579 interrupts = <180>, <181>, <182>, 580 <183>, <184>, <185>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 ti,ngpio = <52>; 584 ti,davinci-gpio-unbanked = <0>; 585 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 586 clocks = <&k3_clks 78 0>; 587 clock-names = "gpio"; 588 status = "disabled"; 589 }; 590 591 sdhci0: mmc@fa10000 { 592 compatible = "ti,am62-sdhci"; 593 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 594 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 595 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 596 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 597 clock-names = "clk_ahb", "clk_xin"; 598 bus-width = <8>; 599 mmc-hs200-1_8v; 600 ti,clkbuf-sel = <0x7>; 601 ti,otap-del-sel-legacy = <0x0>; 602 ti,otap-del-sel-mmc-hs = <0x0>; 603 ti,otap-del-sel-hs200 = <0x6>; 604 status = "disabled"; 605 }; 606 607 sdhci1: mmc@fa00000 { 608 compatible = "ti,am62-sdhci"; 609 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 610 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 611 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 612 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 613 clock-names = "clk_ahb", "clk_xin"; 614 bus-width = <4>; 615 ti,clkbuf-sel = <0x7>; 616 ti,otap-del-sel-legacy = <0x0>; 617 ti,otap-del-sel-sd-hs = <0x0>; 618 ti,otap-del-sel-sdr12 = <0xf>; 619 ti,otap-del-sel-sdr25 = <0xf>; 620 ti,otap-del-sel-sdr50 = <0xc>; 621 ti,otap-del-sel-sdr104 = <0x6>; 622 ti,otap-del-sel-ddr50 = <0x9>; 623 ti,itap-del-sel-legacy = <0x0>; 624 ti,itap-del-sel-sd-hs = <0x0>; 625 ti,itap-del-sel-sdr12 = <0x0>; 626 ti,itap-del-sel-sdr25 = <0x0>; 627 status = "disabled"; 628 }; 629 630 sdhci2: mmc@fa20000 { 631 compatible = "ti,am62-sdhci"; 632 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; 633 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 634 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 635 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 636 clock-names = "clk_ahb", "clk_xin"; 637 bus-width = <4>; 638 ti,clkbuf-sel = <0x7>; 639 ti,otap-del-sel-legacy = <0x0>; 640 ti,otap-del-sel-sd-hs = <0x0>; 641 ti,otap-del-sel-sdr12 = <0xf>; 642 ti,otap-del-sel-sdr25 = <0xf>; 643 ti,otap-del-sel-sdr50 = <0xc>; 644 ti,otap-del-sel-sdr104 = <0x6>; 645 ti,otap-del-sel-ddr50 = <0x9>; 646 ti,itap-del-sel-legacy = <0x0>; 647 ti,itap-del-sel-sd-hs = <0x0>; 648 ti,itap-del-sel-sdr12 = <0x0>; 649 ti,itap-del-sel-sdr25 = <0x0>; 650 status = "disabled"; 651 }; 652 653 usbss0: dwc3-usb@f900000 { 654 compatible = "ti,am62-usb"; 655 reg = <0x00 0x0f900000 0x00 0x800>, 656 <0x00 0x0f908000 0x00 0x400>; 657 clocks = <&k3_clks 161 3>; 658 clock-names = "ref"; 659 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 660 #address-cells = <2>; 661 #size-cells = <2>; 662 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 663 ranges; 664 status = "disabled"; 665 666 usb0: usb@31000000 { 667 compatible = "snps,dwc3"; 668 reg = <0x00 0x31000000 0x00 0x50000>; 669 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 670 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 671 interrupt-names = "host", "peripheral"; 672 maximum-speed = "high-speed"; 673 dr_mode = "otg"; 674 bootph-all; 675 snps,usb2-gadget-lpm-disable; 676 snps,usb2-lpm-disable; 677 }; 678 }; 679 680 usbss1: dwc3-usb@f910000 { 681 compatible = "ti,am62-usb"; 682 reg = <0x00 0x0f910000 0x00 0x800>, 683 <0x00 0x0f918000 0x00 0x400>; 684 clocks = <&k3_clks 162 3>; 685 clock-names = "ref"; 686 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 690 ranges; 691 status = "disabled"; 692 693 usb1: usb@31100000 { 694 compatible = "snps,dwc3"; 695 reg = <0x00 0x31100000 0x00 0x50000>; 696 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 697 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 698 interrupt-names = "host", "peripheral"; 699 maximum-speed = "high-speed"; 700 dr_mode = "otg"; 701 snps,usb2-gadget-lpm-disable; 702 snps,usb2-lpm-disable; 703 }; 704 }; 705 706 fss: bus@fc00000 { 707 compatible = "simple-bus"; 708 reg = <0x00 0x0fc00000 0x00 0x70000>; 709 #address-cells = <2>; 710 #size-cells = <2>; 711 ranges; 712 status = "disabled"; 713 714 ospi0: spi@fc40000 { 715 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 716 reg = <0x00 0x0fc40000 0x00 0x100>, 717 <0x05 0x00000000 0x01 0x00000000>; 718 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 719 cdns,fifo-depth = <256>; 720 cdns,fifo-width = <4>; 721 cdns,trigger-address = <0x0>; 722 clocks = <&k3_clks 75 7>; 723 assigned-clocks = <&k3_clks 75 7>; 724 assigned-clock-parents = <&k3_clks 75 8>; 725 assigned-clock-rates = <166666666>; 726 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 }; 730 }; 731 732 cpsw3g: ethernet@8000000 { 733 compatible = "ti,am642-cpsw-nuss"; 734 #address-cells = <2>; 735 #size-cells = <2>; 736 reg = <0x0 0x8000000 0x0 0x200000>; 737 reg-names = "cpsw_nuss"; 738 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 739 clocks = <&k3_clks 13 0>; 740 assigned-clocks = <&k3_clks 13 3>; 741 assigned-clock-parents = <&k3_clks 13 11>; 742 clock-names = "fck"; 743 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 744 status = "disabled"; 745 746 dmas = <&main_pktdma 0xc600 15>, 747 <&main_pktdma 0xc601 15>, 748 <&main_pktdma 0xc602 15>, 749 <&main_pktdma 0xc603 15>, 750 <&main_pktdma 0xc604 15>, 751 <&main_pktdma 0xc605 15>, 752 <&main_pktdma 0xc606 15>, 753 <&main_pktdma 0xc607 15>, 754 <&main_pktdma 0x4600 15>; 755 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 756 "tx7", "rx"; 757 758 ethernet-ports { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 cpsw_port1: port@1 { 763 reg = <1>; 764 ti,mac-only; 765 label = "port1"; 766 phys = <&phy_gmii_sel 1>; 767 mac-address = [00 00 00 00 00 00]; 768 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 769 bootph-all; 770 }; 771 772 cpsw_port2: port@2 { 773 reg = <2>; 774 ti,mac-only; 775 label = "port2"; 776 phys = <&phy_gmii_sel 2>; 777 mac-address = [00 00 00 00 00 00]; 778 }; 779 }; 780 781 cpsw3g_mdio: mdio@f00 { 782 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 783 reg = <0x0 0xf00 0x0 0x100>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 clocks = <&k3_clks 13 0>; 787 clock-names = "fck"; 788 bus_freq = <1000000>; 789 bootph-all; 790 }; 791 792 cpts@3d000 { 793 compatible = "ti,j721e-cpts"; 794 reg = <0x0 0x3d000 0x0 0x400>; 795 clocks = <&k3_clks 13 3>; 796 clock-names = "cpts"; 797 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-names = "cpts"; 799 ti,cpts-ext-ts-inputs = <4>; 800 ti,cpts-periodic-outputs = <2>; 801 }; 802 }; 803 804 hwspinlock: spinlock@2a000000 { 805 compatible = "ti,am64-hwspinlock"; 806 reg = <0x00 0x2a000000 0x00 0x1000>; 807 #hwlock-cells = <1>; 808 }; 809 810 mailbox0_cluster0: mailbox@29000000 { 811 compatible = "ti,am64-mailbox"; 812 reg = <0x00 0x29000000 0x00 0x200>; 813 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 814 #mbox-cells = <1>; 815 ti,mbox-num-users = <4>; 816 ti,mbox-num-fifos = <16>; 817 status = "disabled"; 818 }; 819 820 mailbox0_cluster1: mailbox@29010000 { 821 compatible = "ti,am64-mailbox"; 822 reg = <0x00 0x29010000 0x00 0x200>; 823 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 824 #mbox-cells = <1>; 825 ti,mbox-num-users = <4>; 826 ti,mbox-num-fifos = <16>; 827 status = "disabled"; 828 }; 829 830 mailbox0_cluster2: mailbox@29020000 { 831 compatible = "ti,am64-mailbox"; 832 reg = <0x00 0x29020000 0x00 0x200>; 833 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 834 #mbox-cells = <1>; 835 ti,mbox-num-users = <4>; 836 ti,mbox-num-fifos = <16>; 837 status = "disabled"; 838 }; 839 840 mailbox0_cluster3: mailbox@29030000 { 841 compatible = "ti,am64-mailbox"; 842 reg = <0x00 0x29030000 0x00 0x200>; 843 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 844 #mbox-cells = <1>; 845 ti,mbox-num-users = <4>; 846 ti,mbox-num-fifos = <16>; 847 status = "disabled"; 848 }; 849 850 main_mcan0: can@20701000 { 851 compatible = "bosch,m_can"; 852 reg = <0x00 0x20701000 0x00 0x200>, 853 <0x00 0x20708000 0x00 0x8000>; 854 reg-names = "m_can", "message_ram"; 855 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 856 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 857 clock-names = "hclk", "cclk"; 858 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "int0", "int1"; 861 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 862 status = "disabled"; 863 }; 864 865 main_rti0: watchdog@e000000 { 866 compatible = "ti,j7-rti-wdt"; 867 reg = <0x00 0x0e000000 0x00 0x100>; 868 clocks = <&k3_clks 125 0>; 869 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 870 assigned-clocks = <&k3_clks 125 0>; 871 assigned-clock-parents = <&k3_clks 125 2>; 872 }; 873 874 main_rti1: watchdog@e010000 { 875 compatible = "ti,j7-rti-wdt"; 876 reg = <0x00 0x0e010000 0x00 0x100>; 877 clocks = <&k3_clks 126 0>; 878 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 879 assigned-clocks = <&k3_clks 126 0>; 880 assigned-clock-parents = <&k3_clks 126 2>; 881 }; 882 883 main_rti2: watchdog@e020000 { 884 compatible = "ti,j7-rti-wdt"; 885 reg = <0x00 0x0e020000 0x00 0x100>; 886 clocks = <&k3_clks 127 0>; 887 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 888 assigned-clocks = <&k3_clks 127 0>; 889 assigned-clock-parents = <&k3_clks 127 2>; 890 }; 891 892 main_rti3: watchdog@e030000 { 893 compatible = "ti,j7-rti-wdt"; 894 reg = <0x00 0x0e030000 0x00 0x100>; 895 clocks = <&k3_clks 128 0>; 896 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 897 assigned-clocks = <&k3_clks 128 0>; 898 assigned-clock-parents = <&k3_clks 128 2>; 899 }; 900 901 main_rti4: watchdog@e040000 { 902 compatible = "ti,j7-rti-wdt"; 903 reg = <0x00 0x0e040000 0x00 0x100>; 904 clocks = <&k3_clks 205 0>; 905 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 906 assigned-clocks = <&k3_clks 205 0>; 907 assigned-clock-parents = <&k3_clks 205 2>; 908 }; 909 910 epwm0: pwm@23000000 { 911 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 912 #pwm-cells = <3>; 913 reg = <0x00 0x23000000 0x00 0x100>; 914 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 916 clock-names = "tbclk", "fck"; 917 status = "disabled"; 918 }; 919 920 epwm1: pwm@23010000 { 921 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 922 #pwm-cells = <3>; 923 reg = <0x00 0x23010000 0x00 0x100>; 924 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 925 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 926 clock-names = "tbclk", "fck"; 927 status = "disabled"; 928 }; 929 930 epwm2: pwm@23020000 { 931 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 932 #pwm-cells = <3>; 933 reg = <0x00 0x23020000 0x00 0x100>; 934 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 935 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 936 clock-names = "tbclk", "fck"; 937 status = "disabled"; 938 }; 939 940 ecap0: pwm@23100000 { 941 compatible = "ti,am3352-ecap"; 942 #pwm-cells = <3>; 943 reg = <0x00 0x23100000 0x00 0x100>; 944 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 945 clocks = <&k3_clks 51 0>; 946 clock-names = "fck"; 947 status = "disabled"; 948 }; 949 950 ecap1: pwm@23110000 { 951 compatible = "ti,am3352-ecap"; 952 #pwm-cells = <3>; 953 reg = <0x00 0x23110000 0x00 0x100>; 954 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 955 clocks = <&k3_clks 52 0>; 956 clock-names = "fck"; 957 status = "disabled"; 958 }; 959 960 ecap2: pwm@23120000 { 961 compatible = "ti,am3352-ecap"; 962 #pwm-cells = <3>; 963 reg = <0x00 0x23120000 0x00 0x100>; 964 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 965 clocks = <&k3_clks 53 0>; 966 clock-names = "fck"; 967 status = "disabled"; 968 }; 969 970 eqep0: counter@23200000 { 971 compatible = "ti,am62-eqep"; 972 reg = <0x00 0x23200000 0x00 0x100>; 973 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 974 clocks = <&k3_clks 59 0>; 975 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 976 status = "disabled"; 977 }; 978 979 eqep1: counter@23210000 { 980 compatible = "ti,am62-eqep"; 981 reg = <0x00 0x23210000 0x00 0x100>; 982 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 983 clocks = <&k3_clks 60 0>; 984 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 985 status = "disabled"; 986 }; 987 988 eqep2: counter@23220000 { 989 compatible = "ti,am62-eqep"; 990 reg = <0x00 0x23220000 0x00 0x100>; 991 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 992 clocks = <&k3_clks 62 0>; 993 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 994 status = "disabled"; 995 }; 996 997 mcasp0: audio-controller@2b00000 { 998 compatible = "ti,am33xx-mcasp-audio"; 999 reg = <0x00 0x02b00000 0x00 0x2000>, 1000 <0x00 0x02b08000 0x00 0x400>; 1001 reg-names = "mpu", "dat"; 1002 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-names = "tx", "rx"; 1005 1006 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 1007 dma-names = "tx", "rx"; 1008 1009 clocks = <&k3_clks 190 0>; 1010 clock-names = "fck"; 1011 assigned-clocks = <&k3_clks 190 0>; 1012 assigned-clock-parents = <&k3_clks 190 2>; 1013 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1014 status = "disabled"; 1015 }; 1016 1017 mcasp1: audio-controller@2b10000 { 1018 compatible = "ti,am33xx-mcasp-audio"; 1019 reg = <0x00 0x02b10000 0x00 0x2000>, 1020 <0x00 0x02b18000 0x00 0x400>; 1021 reg-names = "mpu", "dat"; 1022 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "tx", "rx"; 1025 1026 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1027 dma-names = "tx", "rx"; 1028 1029 clocks = <&k3_clks 191 0>; 1030 clock-names = "fck"; 1031 assigned-clocks = <&k3_clks 191 0>; 1032 assigned-clock-parents = <&k3_clks 191 2>; 1033 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1034 status = "disabled"; 1035 }; 1036 1037 mcasp2: audio-controller@2b20000 { 1038 compatible = "ti,am33xx-mcasp-audio"; 1039 reg = <0x00 0x02b20000 0x00 0x2000>, 1040 <0x00 0x02b28000 0x00 0x400>; 1041 reg-names = "mpu", "dat"; 1042 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "tx", "rx"; 1045 1046 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1047 dma-names = "tx", "rx"; 1048 1049 clocks = <&k3_clks 192 0>; 1050 clock-names = "fck"; 1051 assigned-clocks = <&k3_clks 192 0>; 1052 assigned-clock-parents = <&k3_clks 192 2>; 1053 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1054 status = "disabled"; 1055 }; 1056 1057 ti_csi2rx0: ticsi2rx@30102000 { 1058 compatible = "ti,j721e-csi2rx-shim"; 1059 dmas = <&main_bcdma_csi 0 0x5000 0>; 1060 dma-names = "rx0"; 1061 reg = <0x00 0x30102000 0x00 0x1000>; 1062 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1063 #address-cells = <2>; 1064 #size-cells = <2>; 1065 ranges; 1066 status = "disabled"; 1067 1068 cdns_csi2rx0: csi-bridge@30101000 { 1069 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1070 reg = <0x00 0x30101000 0x00 0x1000>; 1071 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "error_irq", "irq"; 1074 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1075 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1076 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1077 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1078 phys = <&dphy0>; 1079 phy-names = "dphy"; 1080 1081 ports { 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 csi0_port0: port@0 { 1086 reg = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 csi0_port1: port@1 { 1091 reg = <1>; 1092 status = "disabled"; 1093 }; 1094 1095 csi0_port2: port@2 { 1096 reg = <2>; 1097 status = "disabled"; 1098 }; 1099 1100 csi0_port3: port@3 { 1101 reg = <3>; 1102 status = "disabled"; 1103 }; 1104 1105 csi0_port4: port@4 { 1106 reg = <4>; 1107 status = "disabled"; 1108 }; 1109 }; 1110 }; 1111 }; 1112 1113 dphy0: phy@30110000 { 1114 compatible = "cdns,dphy-rx"; 1115 reg = <0x00 0x30110000 0x00 0x1100>; 1116 #phy-cells = <0>; 1117 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1118 status = "disabled"; 1119 }; 1120 1121 dss: dss@30200000 { 1122 compatible = "ti,am62a7-dss"; 1123 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 1124 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 1125 <0x00 0x30206000 0x00 0x1000>, /* vid */ 1126 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 1127 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 1128 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ 1129 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 1130 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 1131 reg-names = "common", "vidl1", "vid", 1132 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1133 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1134 clocks = <&k3_clks 186 6>, 1135 <&k3_clks 186 0>, 1136 <&k3_clks 186 2>; 1137 clock-names = "fck", "vp1", "vp2"; 1138 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1139 status = "disabled"; 1140 1141 dss_ports: ports { 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 }; 1145 }; 1146 1147 vpu: video-codec@30210000 { 1148 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1149 reg = <0x00 0x30210000 0x00 0x10000>; 1150 clocks = <&k3_clks 204 2>; 1151 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1152 }; 1153 1154 c7x_0: dsp@7e000000 { 1155 compatible = "ti,am62a-c7xv-dsp"; 1156 reg = <0x00 0x7e000000 0x00 0x00100000>; 1157 reg-names = "l2sram"; 1158 resets = <&k3_reset 208 1>; 1159 firmware-name = "am62a-c71_0-fw"; 1160 ti,sci = <&dmsc>; 1161 ti,sci-dev-id = <208>; 1162 ti,sci-proc-ids = <0x04 0xff>; 1163 status = "disabled"; 1164 }; 1165 1166 e5010: jpeg-encoder@fd20000 { 1167 compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; 1168 reg = <0x00 0xfd20000 0x00 0x100>, 1169 <0x00 0xfd20200 0x00 0x200>; 1170 reg-names = "core", "mmu"; 1171 clocks = <&k3_clks 201 0>; 1172 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1173 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1174 }; 1175};
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