k3-am625.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for AM625 SoC family in Quad core configuration
  4 *
  5 * TRM: https://www.ti.com/lit/pdf/spruiv7
  6 *
  7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  8 */
  9
 10/dts-v1/;
 11
 12#include "k3-am62.dtsi"
 13
 14/ {
 15	cpus {
 16		#address-cells = <1>;
 17		#size-cells = <0>;
 18
 19		cpu-map {
 20			cluster0: cluster0 {
 21				core0 {
 22					cpu = <&cpu0>;
 23				};
 24
 25				core1 {
 26					cpu = <&cpu1>;
 27				};
 28
 29				core2 {
 30					cpu = <&cpu2>;
 31				};
 32
 33				core3 {
 34					cpu = <&cpu3>;
 35				};
 36			};
 37		};
 38
 39		cpu0: cpu@0 {
 40			compatible = "arm,cortex-a53";
 41			reg = <0x000>;
 42			device_type = "cpu";
 43			enable-method = "psci";
 44			i-cache-size = <0x8000>;
 45			i-cache-line-size = <64>;
 46			i-cache-sets = <256>;
 47			d-cache-size = <0x8000>;
 48			d-cache-line-size = <64>;
 49			d-cache-sets = <128>;
 50			next-level-cache = <&L2_0>;
 51			operating-points-v2 = <&a53_opp_table>;
 52			clocks = <&k3_clks 135 0>;
 53			#cooling-cells = <2>;
 54		};
 55
 56		cpu1: cpu@1 {
 57			compatible = "arm,cortex-a53";
 58			reg = <0x001>;
 59			device_type = "cpu";
 60			enable-method = "psci";
 61			i-cache-size = <0x8000>;
 62			i-cache-line-size = <64>;
 63			i-cache-sets = <256>;
 64			d-cache-size = <0x8000>;
 65			d-cache-line-size = <64>;
 66			d-cache-sets = <128>;
 67			next-level-cache = <&L2_0>;
 68			operating-points-v2 = <&a53_opp_table>;
 69			clocks = <&k3_clks 136 0>;
 70			#cooling-cells = <2>;
 71		};
 72
 73		cpu2: cpu@2 {
 74			compatible = "arm,cortex-a53";
 75			reg = <0x002>;
 76			device_type = "cpu";
 77			enable-method = "psci";
 78			i-cache-size = <0x8000>;
 79			i-cache-line-size = <64>;
 80			i-cache-sets = <256>;
 81			d-cache-size = <0x8000>;
 82			d-cache-line-size = <64>;
 83			d-cache-sets = <128>;
 84			next-level-cache = <&L2_0>;
 85			operating-points-v2 = <&a53_opp_table>;
 86			clocks = <&k3_clks 137 0>;
 87			#cooling-cells = <2>;
 88		};
 89
 90		cpu3: cpu@3 {
 91			compatible = "arm,cortex-a53";
 92			reg = <0x003>;
 93			device_type = "cpu";
 94			enable-method = "psci";
 95			i-cache-size = <0x8000>;
 96			i-cache-line-size = <64>;
 97			i-cache-sets = <256>;
 98			d-cache-size = <0x8000>;
 99			d-cache-line-size = <64>;
100			d-cache-sets = <128>;
101			next-level-cache = <&L2_0>;
102			operating-points-v2 = <&a53_opp_table>;
103			clocks = <&k3_clks 138 0>;
104			#cooling-cells = <2>;
105		};
106	};
107
108	a53_opp_table: opp-table {
109		compatible = "operating-points-v2-ti-cpu";
110		opp-shared;
111		syscon = <&opp_efuse_table>;
112
113		opp-200000000 {
114			opp-hz = /bits/ 64 <200000000>;
115			opp-supported-hw = <0x01 0x0007>;
116			clock-latency-ns = <6000000>;
117		};
118
119		opp-400000000 {
120			opp-hz = /bits/ 64 <400000000>;
121			opp-supported-hw = <0x01 0x0007>;
122			clock-latency-ns = <6000000>;
123		};
124
125		opp-600000000 {
126			opp-hz = /bits/ 64 <600000000>;
127			opp-supported-hw = <0x01 0x0007>;
128			clock-latency-ns = <6000000>;
129		};
130
131		opp-800000000 {
132			opp-hz = /bits/ 64 <800000000>;
133			opp-supported-hw = <0x01 0x0007>;
134			clock-latency-ns = <6000000>;
135		};
136
137		opp-1000000000 {
138			opp-hz = /bits/ 64 <1000000000>;
139			opp-supported-hw = <0x01 0x0006>;
140			clock-latency-ns = <6000000>;
141		};
142
143		opp-1250000000 {
144			opp-hz = /bits/ 64 <1250000000>;
145			opp-supported-hw = <0x01 0x0004>;
146			clock-latency-ns = <6000000>;
147			opp-suspend;
148		};
149	};
150
151	L2_0: l2-cache0 {
152		compatible = "cache";
153		cache-unified;
154		cache-level = <2>;
155		cache-size = <0x80000>;
156		cache-line-size = <64>;
157		cache-sets = <512>;
158	};
159};