k3-am62.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Device Tree Source for AM62 SoC Family
  4 *
  5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/interrupt-controller/irq.h>
 10#include <dt-bindings/interrupt-controller/arm-gic.h>
 11#include <dt-bindings/soc/ti,sci_pm_domain.h>
 12
 13#include "k3-pinctrl.h"
 14
 15/ {
 16	model = "Texas Instruments K3 AM625 SoC";
 17	compatible = "ti,am625";
 18	interrupt-parent = <&gic500>;
 19	#address-cells = <2>;
 20	#size-cells = <2>;
 21
 22	chosen { };
 23
 24	firmware {
 25		optee {
 26			compatible = "linaro,optee-tz";
 27			method = "smc";
 28		};
 29
 30		psci: psci {
 31			compatible = "arm,psci-1.0";
 32			method = "smc";
 33		};
 34	};
 35
 36	a53_timer0: timer-cl0-cpu0 {
 37		compatible = "arm,armv8-timer";
 38		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 39			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 40			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 41			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 42	};
 43
 44	pmu: pmu {
 45		compatible = "arm,cortex-a53-pmu";
 46		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 47	};
 48
 49	system-idle-states {
 50		system_partial_io: system-partial-io {
 51			compatible = "system-idle-state";
 52			idle-state-name = "off-wake";
 53		};
 54
 55		system_deep_sleep: system-deep-sleep {
 56			compatible = "system-idle-state";
 57			idle-state-name = "mem";
 58		};
 59
 60		system_mcu_only: system-mcu-only {
 61			compatible = "system-idle-state";
 62			idle-state-name = "mem-mcu-active";
 63		};
 64
 65		system_standby: system-standby {
 66			compatible = "system-idle-state";
 67			idle-state-name = "standby";
 68		};
 69	};
 70
 71	cbass_main: bus@f0000 {
 72		bootph-all;
 73		compatible = "simple-bus";
 74		#address-cells = <2>;
 75		#size-cells = <2>;
 76
 77		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
 78			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
 79			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
 80			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
 81			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
 82			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
 83			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
 84			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 85			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
 86			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
 87			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
 88			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
 89			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
 90			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
 91			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
 92			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
 93			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
 94			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
 95			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
 96			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
 97			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
 98			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
 99			 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
100			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
101			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
102			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
103			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
104
105			 /* MCU Domain Range */
106			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
107
108			 /* Wakeup Domain Range */
109			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
110			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
111			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
112			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
113			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
114
115		cbass_mcu: bus@4000000 {
116			bootph-all;
117			compatible = "simple-bus";
118			#address-cells = <2>;
119			#size-cells = <2>;
120			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
121		};
122
123		cbass_wakeup: bus@b00000 {
124			bootph-all;
125			compatible = "simple-bus";
126			#address-cells = <2>;
127			#size-cells = <2>;
128			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
129				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
130				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
131				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
132				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
133		};
134	};
135
136	dss_vp1_clk: clock-divider-oldi {
137		compatible = "fixed-factor-clock";
138		clocks = <&k3_clks 186 0>;
139		#clock-cells = <0>;
140		clock-div = <7>;
141		clock-mult = <1>;
142	};
143
144	#include "k3-am62-thermal.dtsi"
145};
146
147/* Now include the peripherals for each bus segments */
148#include "k3-am62-main.dtsi"
149#include "k3-am62-mcu.dtsi"
150#include "k3-am62-wakeup.dtsi"