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k3-am62-main.dtsi
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linux-6.19.14/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 27 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 28 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: bus@100000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x0 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 }; 55 56 epwm_tbclk: clock-controller@4130 { 57 compatible = "ti,am62-epwm-tbclk"; 58 reg = <0x4130 0x4>; 59 #clock-cells = <1>; 60 }; 61 62 audio_refclk0: clock-controller@82e0 { 63 compatible = "ti,am62-audio-refclk"; 64 reg = <0x82e0 0x4>; 65 clocks = <&k3_clks 157 0>; 66 assigned-clocks = <&k3_clks 157 0>; 67 assigned-clock-parents = <&k3_clks 157 8>; 68 #clock-cells = <0>; 69 }; 70 71 audio_refclk1: clock-controller@82e4 { 72 compatible = "ti,am62-audio-refclk"; 73 reg = <0x82e4 0x4>; 74 clocks = <&k3_clks 157 10>; 75 assigned-clocks = <&k3_clks 157 10>; 76 assigned-clock-parents = <&k3_clks 157 18>; 77 #clock-cells = <0>; 78 }; 79 80 dss_oldi_io_ctrl: oldi-io-controller@8600 { 81 compatible = "ti,am625-dss-oldi-io-ctrl", "syscon"; 82 reg = <0x8600 0x200>; 83 }; 84 }; 85 86 dmss: bus@48000000 { 87 bootph-all; 88 compatible = "simple-bus"; 89 #address-cells = <2>; 90 #size-cells = <2>; 91 dma-ranges; 92 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 93 94 ti,sci-dev-id = <25>; 95 96 secure_proxy_main: mailbox@4d000000 { 97 bootph-all; 98 compatible = "ti,am654-secure-proxy"; 99 #mbox-cells = <1>; 100 reg-names = "target_data", "rt", "scfg"; 101 reg = <0x00 0x4d000000 0x00 0x80000>, 102 <0x00 0x4a600000 0x00 0x80000>, 103 <0x00 0x4a400000 0x00 0x80000>; 104 interrupt-names = "rx_012"; 105 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 106 }; 107 108 inta_main_dmss: interrupt-controller@48000000 { 109 compatible = "ti,sci-inta"; 110 reg = <0x00 0x48000000 0x00 0x100000>; 111 #interrupt-cells = <0>; 112 interrupt-controller; 113 interrupt-parent = <&gic500>; 114 msi-controller; 115 ti,sci = <&dmsc>; 116 ti,sci-dev-id = <28>; 117 ti,interrupt-ranges = <4 68 36>; 118 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 119 }; 120 121 main_bcdma: dma-controller@485c0100 { 122 compatible = "ti,am64-dmss-bcdma"; 123 reg = <0x00 0x485c0100 0x00 0x100>, 124 <0x00 0x4c000000 0x00 0x20000>, 125 <0x00 0x4a820000 0x00 0x20000>, 126 <0x00 0x4aa40000 0x00 0x20000>, 127 <0x00 0x4bc00000 0x00 0x100000>, 128 <0x00 0x48600000 0x00 0x8000>, 129 <0x00 0x484a4000 0x00 0x2000>, 130 <0x00 0x484c2000 0x00 0x2000>, 131 <0x00 0x48420000 0x00 0x2000>; 132 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 133 "ring", "tchan", "rchan", "bchan"; 134 msi-parent = <&inta_main_dmss>; 135 #dma-cells = <3>; 136 137 ti,sci = <&dmsc>; 138 ti,sci-dev-id = <26>; 139 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 140 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 141 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 142 }; 143 144 main_pktdma: dma-controller@485c0000 { 145 compatible = "ti,am64-dmss-pktdma"; 146 reg = <0x00 0x485c0000 0x00 0x100>, 147 <0x00 0x4a800000 0x00 0x20000>, 148 <0x00 0x4aa00000 0x00 0x20000>, 149 <0x00 0x4b800000 0x00 0x200000>, 150 <0x00 0x485e0000 0x00 0x10000>, 151 <0x00 0x484a0000 0x00 0x2000>, 152 <0x00 0x484c0000 0x00 0x2000>, 153 <0x00 0x48430000 0x00 0x1000>; 154 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 155 "ring", "tchan", "rchan", "rflow"; 156 msi-parent = <&inta_main_dmss>; 157 #dma-cells = <2>; 158 159 ti,sci = <&dmsc>; 160 ti,sci-dev-id = <30>; 161 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 162 <0x24>, /* CPSW_TX_CHAN */ 163 <0x25>, /* SAUL_TX_0_CHAN */ 164 <0x26>; /* SAUL_TX_1_CHAN */ 165 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 166 <0x11>, /* RING_CPSW_TX_CHAN */ 167 <0x12>, /* RING_SAUL_TX_0_CHAN */ 168 <0x13>; /* RING_SAUL_TX_1_CHAN */ 169 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 170 <0x2b>, /* CPSW_RX_CHAN */ 171 <0x2d>, /* SAUL_RX_0_CHAN */ 172 <0x2f>, /* SAUL_RX_1_CHAN */ 173 <0x31>, /* SAUL_RX_2_CHAN */ 174 <0x33>; /* SAUL_RX_3_CHAN */ 175 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 176 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 177 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 178 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 179 }; 180 }; 181 182 dmsc: system-controller@44043000 { 183 bootph-all; 184 compatible = "ti,k2g-sci"; 185 ti,host-id = <12>; 186 mbox-names = "rx", "tx"; 187 mboxes = <&secure_proxy_main 12>, 188 <&secure_proxy_main 13>; 189 reg-names = "debug_messages"; 190 reg = <0x00 0x44043000 0x00 0xfe0>; 191 192 k3_pds: power-controller { 193 bootph-all; 194 compatible = "ti,sci-pm-domain"; 195 #power-domain-cells = <2>; 196 }; 197 198 k3_clks: clock-controller { 199 bootph-all; 200 compatible = "ti,k2g-sci-clk"; 201 #clock-cells = <2>; 202 }; 203 204 k3_reset: reset-controller { 205 bootph-all; 206 compatible = "ti,sci-reset"; 207 #reset-cells = <2>; 208 }; 209 }; 210 211 crypto: crypto@40900000 { 212 compatible = "ti,am62-sa3ul"; 213 reg = <0x00 0x40900000 0x00 0x1200>; 214 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 215 <&main_pktdma 0x7507 0>; 216 dma-names = "tx", "rx1", "rx2"; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 220 221 rng: rng@40910000 { 222 compatible = "inside-secure,safexcel-eip76"; 223 reg = <0x00 0x40910000 0x00 0x7d>; 224 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 225 status = "reserved"; /* Reserved for OP-TEE */ 226 }; 227 }; 228 229 secure_proxy_sa3: mailbox@43600000 { 230 bootph-pre-ram; 231 compatible = "ti,am654-secure-proxy"; 232 #mbox-cells = <1>; 233 reg-names = "target_data", "rt", "scfg"; 234 reg = <0x00 0x43600000 0x00 0x10000>, 235 <0x00 0x44880000 0x00 0x20000>, 236 <0x00 0x44860000 0x00 0x20000>; 237 /* 238 * Marked Disabled: 239 * Node is incomplete as it is meant for bootloaders and 240 * firmware on non-MPU processors 241 */ 242 status = "disabled"; 243 }; 244 245 main_pmx0: pinctrl@f4000 { 246 bootph-all; 247 compatible = "pinctrl-single"; 248 reg = <0x00 0xf4000 0x00 0x2ac>; 249 #pinctrl-cells = <1>; 250 pinctrl-single,register-width = <32>; 251 pinctrl-single,function-mask = <0xffffffff>; 252 }; 253 254 main_esm: esm@420000 { 255 bootph-pre-ram; 256 compatible = "ti,j721e-esm"; 257 reg = <0x00 0x420000 0x00 0x1000>; 258 /* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */ 259 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 260 }; 261 262 main_timer0: timer@2400000 { 263 bootph-all; 264 compatible = "ti,am654-timer"; 265 reg = <0x00 0x2400000 0x00 0x400>; 266 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&k3_clks 36 2>; 268 clock-names = "fck"; 269 assigned-clocks = <&k3_clks 36 2>; 270 assigned-clock-parents = <&k3_clks 36 3>; 271 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 272 ti,timer-pwm; 273 }; 274 275 main_timer1: timer@2410000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x2410000 0x00 0x400>; 278 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 37 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 37 2>; 282 assigned-clock-parents = <&k3_clks 37 3>; 283 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 }; 286 287 main_timer2: timer@2420000 { 288 compatible = "ti,am654-timer"; 289 reg = <0x00 0x2420000 0x00 0x400>; 290 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&k3_clks 38 2>; 292 clock-names = "fck"; 293 assigned-clocks = <&k3_clks 38 2>; 294 assigned-clock-parents = <&k3_clks 38 3>; 295 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 296 ti,timer-pwm; 297 }; 298 299 main_timer3: timer@2430000 { 300 compatible = "ti,am654-timer"; 301 reg = <0x00 0x2430000 0x00 0x400>; 302 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&k3_clks 39 2>; 304 clock-names = "fck"; 305 assigned-clocks = <&k3_clks 39 2>; 306 assigned-clock-parents = <&k3_clks 39 3>; 307 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 308 ti,timer-pwm; 309 }; 310 311 main_timer4: timer@2440000 { 312 compatible = "ti,am654-timer"; 313 reg = <0x00 0x2440000 0x00 0x400>; 314 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&k3_clks 40 2>; 316 clock-names = "fck"; 317 assigned-clocks = <&k3_clks 40 2>; 318 assigned-clock-parents = <&k3_clks 40 3>; 319 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 320 ti,timer-pwm; 321 }; 322 323 main_timer5: timer@2450000 { 324 compatible = "ti,am654-timer"; 325 reg = <0x00 0x2450000 0x00 0x400>; 326 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&k3_clks 41 2>; 328 clock-names = "fck"; 329 assigned-clocks = <&k3_clks 41 2>; 330 assigned-clock-parents = <&k3_clks 41 3>; 331 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 332 ti,timer-pwm; 333 }; 334 335 main_timer6: timer@2460000 { 336 compatible = "ti,am654-timer"; 337 reg = <0x00 0x2460000 0x00 0x400>; 338 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&k3_clks 42 2>; 340 clock-names = "fck"; 341 assigned-clocks = <&k3_clks 42 2>; 342 assigned-clock-parents = <&k3_clks 42 3>; 343 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 344 ti,timer-pwm; 345 }; 346 347 main_timer7: timer@2470000 { 348 compatible = "ti,am654-timer"; 349 reg = <0x00 0x2470000 0x00 0x400>; 350 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&k3_clks 43 2>; 352 clock-names = "fck"; 353 assigned-clocks = <&k3_clks 43 2>; 354 assigned-clock-parents = <&k3_clks 43 3>; 355 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 356 ti,timer-pwm; 357 }; 358 359 main_uart0: serial@2800000 { 360 compatible = "ti,am64-uart", "ti,am654-uart"; 361 reg = <0x00 0x02800000 0x00 0x100>; 362 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 363 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 146 0>; 365 clock-names = "fclk"; 366 status = "disabled"; 367 }; 368 369 main_uart1: serial@2810000 { 370 compatible = "ti,am64-uart", "ti,am654-uart"; 371 reg = <0x00 0x02810000 0x00 0x100>; 372 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 373 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 374 clocks = <&k3_clks 152 0>; 375 clock-names = "fclk"; 376 status = "disabled"; 377 }; 378 379 main_uart2: serial@2820000 { 380 compatible = "ti,am64-uart", "ti,am654-uart"; 381 reg = <0x00 0x02820000 0x00 0x100>; 382 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 383 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 384 clocks = <&k3_clks 153 0>; 385 clock-names = "fclk"; 386 status = "disabled"; 387 }; 388 389 main_uart3: serial@2830000 { 390 compatible = "ti,am64-uart", "ti,am654-uart"; 391 reg = <0x00 0x02830000 0x00 0x100>; 392 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 393 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 394 clocks = <&k3_clks 154 0>; 395 clock-names = "fclk"; 396 status = "disabled"; 397 }; 398 399 main_uart4: serial@2840000 { 400 compatible = "ti,am64-uart", "ti,am654-uart"; 401 reg = <0x00 0x02840000 0x00 0x100>; 402 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 403 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 155 0>; 405 clock-names = "fclk"; 406 status = "disabled"; 407 }; 408 409 main_uart5: serial@2850000 { 410 compatible = "ti,am64-uart", "ti,am654-uart"; 411 reg = <0x00 0x02850000 0x00 0x100>; 412 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 413 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 414 clocks = <&k3_clks 156 0>; 415 clock-names = "fclk"; 416 status = "disabled"; 417 }; 418 419 main_uart6: serial@2860000 { 420 compatible = "ti,am64-uart", "ti,am654-uart"; 421 reg = <0x00 0x02860000 0x00 0x100>; 422 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 423 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 424 clocks = <&k3_clks 158 0>; 425 clock-names = "fclk"; 426 status = "disabled"; 427 }; 428 429 main_i2c0: i2c@20000000 { 430 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 431 reg = <0x00 0x20000000 0x00 0x100>; 432 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 102 2>; 437 clock-names = "fck"; 438 status = "disabled"; 439 }; 440 441 main_i2c1: i2c@20010000 { 442 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 443 reg = <0x00 0x20010000 0x00 0x100>; 444 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 448 clocks = <&k3_clks 103 2>; 449 clock-names = "fck"; 450 status = "disabled"; 451 }; 452 453 main_i2c2: i2c@20020000 { 454 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 455 reg = <0x00 0x20020000 0x00 0x100>; 456 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 460 clocks = <&k3_clks 104 2>; 461 clock-names = "fck"; 462 status = "disabled"; 463 }; 464 465 main_i2c3: i2c@20030000 { 466 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 467 reg = <0x00 0x20030000 0x00 0x100>; 468 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 472 clocks = <&k3_clks 105 2>; 473 clock-names = "fck"; 474 status = "disabled"; 475 }; 476 477 main_spi0: spi@20100000 { 478 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 479 reg = <0x00 0x20100000 0x00 0x400>; 480 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 484 clocks = <&k3_clks 141 0>; 485 status = "disabled"; 486 }; 487 488 main_spi1: spi@20110000 { 489 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 490 reg = <0x00 0x20110000 0x00 0x400>; 491 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 495 clocks = <&k3_clks 142 0>; 496 status = "disabled"; 497 }; 498 499 main_spi2: spi@20120000 { 500 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 501 reg = <0x00 0x20120000 0x00 0x400>; 502 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 506 clocks = <&k3_clks 143 0>; 507 status = "disabled"; 508 }; 509 510 main_gpio_intr: interrupt-controller@a00000 { 511 compatible = "ti,sci-intr"; 512 reg = <0x00 0x00a00000 0x00 0x800>; 513 ti,intr-trigger-type = <1>; 514 interrupt-controller; 515 interrupt-parent = <&gic500>; 516 #interrupt-cells = <1>; 517 ti,sci = <&dmsc>; 518 ti,sci-dev-id = <3>; 519 ti,interrupt-ranges = <0 32 16>; 520 }; 521 522 main_gpio0: gpio@600000 { 523 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 524 reg = <0x0 0x00600000 0x0 0x100>; 525 gpio-ranges = <&main_pmx0 0 0 32>, 526 <&main_pmx0 32 33 38>, 527 <&main_pmx0 70 72 22>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-parent = <&main_gpio_intr>; 531 interrupts = <190>, <191>, <192>, 532 <193>, <194>, <195>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 ti,ngpio = <92>; 536 ti,davinci-gpio-unbanked = <0>; 537 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 538 clocks = <&k3_clks 77 0>; 539 clock-names = "gpio"; 540 }; 541 542 main_gpio1: gpio@601000 { 543 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 544 reg = <0x0 0x00601000 0x0 0x100>; 545 gpio-controller; 546 gpio-ranges = <&main_pmx0 0 94 41>, 547 <&main_pmx0 41 136 6>, 548 <&main_pmx0 47 143 3>, 549 <&main_pmx0 50 149 2>; 550 #gpio-cells = <2>; 551 interrupt-parent = <&main_gpio_intr>; 552 interrupts = <180>, <181>, <182>, 553 <183>, <184>, <185>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ti,ngpio = <52>; 557 ti,davinci-gpio-unbanked = <0>; 558 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 78 0>; 560 clock-names = "gpio"; 561 }; 562 563 sdhci0: mmc@fa10000 { 564 compatible = "ti,am62-sdhci"; 565 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 566 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 567 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 568 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 569 clock-names = "clk_ahb", "clk_xin"; 570 bus-width = <8>; 571 mmc-hs200-1_8v; 572 ti,clkbuf-sel = <0x7>; 573 ti,otap-del-sel-legacy = <0x0>; 574 ti,otap-del-sel-mmc-hs = <0x0>; 575 ti,otap-del-sel-hs200 = <0x6>; 576 ti,itap-del-sel-legacy = <0x0>; 577 ti,itap-del-sel-mmc-hs = <0x0>; 578 status = "disabled"; 579 }; 580 581 sdhci1: mmc@fa00000 { 582 compatible = "ti,am62-sdhci"; 583 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 584 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 585 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 586 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 587 clock-names = "clk_ahb", "clk_xin"; 588 bus-width = <4>; 589 ti,clkbuf-sel = <0x7>; 590 ti,otap-del-sel-legacy = <0x0>; 591 ti,otap-del-sel-sd-hs = <0x0>; 592 ti,otap-del-sel-sdr12 = <0xf>; 593 ti,otap-del-sel-sdr25 = <0xf>; 594 ti,otap-del-sel-sdr50 = <0xc>; 595 ti,otap-del-sel-sdr104 = <0x6>; 596 ti,otap-del-sel-ddr50 = <0x9>; 597 ti,itap-del-sel-legacy = <0x0>; 598 ti,itap-del-sel-sd-hs = <0x0>; 599 ti,itap-del-sel-sdr12 = <0x0>; 600 ti,itap-del-sel-sdr25 = <0x0>; 601 status = "disabled"; 602 }; 603 604 sdhci2: mmc@fa20000 { 605 compatible = "ti,am62-sdhci"; 606 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 607 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 608 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 609 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 610 clock-names = "clk_ahb", "clk_xin"; 611 bus-width = <4>; 612 ti,clkbuf-sel = <0x7>; 613 ti,otap-del-sel-legacy = <0x0>; 614 ti,otap-del-sel-sd-hs = <0x0>; 615 ti,otap-del-sel-sdr12 = <0xf>; 616 ti,otap-del-sel-sdr25 = <0xf>; 617 ti,otap-del-sel-sdr50 = <0xc>; 618 ti,otap-del-sel-sdr104 = <0x6>; 619 ti,otap-del-sel-ddr50 = <0x9>; 620 ti,itap-del-sel-legacy = <0x0>; 621 ti,itap-del-sel-sd-hs = <0x0>; 622 ti,itap-del-sel-sdr12 = <0x0>; 623 ti,itap-del-sel-sdr25 = <0x0>; 624 status = "disabled"; 625 }; 626 627 usbss0: dwc3-usb@f900000 { 628 compatible = "ti,am62-usb"; 629 reg = <0x00 0x0f900000 0x00 0x800>, 630 <0x00 0x0f908000 0x00 0x400>; 631 clocks = <&k3_clks 161 3>; 632 clock-names = "ref"; 633 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 634 #address-cells = <2>; 635 #size-cells = <2>; 636 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 637 ranges; 638 status = "disabled"; 639 640 usb0: usb@31000000 { 641 compatible = "snps,dwc3"; 642 reg = <0x00 0x31000000 0x00 0x50000>; 643 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 644 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 645 interrupt-names = "host", "peripheral"; 646 maximum-speed = "high-speed"; 647 dr_mode = "otg"; 648 snps,usb2-gadget-lpm-disable; 649 snps,usb2-lpm-disable; 650 }; 651 }; 652 653 usbss1: dwc3-usb@f910000 { 654 compatible = "ti,am62-usb"; 655 reg = <0x00 0x0f910000 0x00 0x800>, 656 <0x00 0x0f918000 0x00 0x400>; 657 clocks = <&k3_clks 162 3>; 658 clock-names = "ref"; 659 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 660 #address-cells = <2>; 661 #size-cells = <2>; 662 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 663 ranges; 664 status = "disabled"; 665 666 usb1: usb@31100000 { 667 compatible = "snps,dwc3"; 668 reg = <0x00 0x31100000 0x00 0x50000>; 669 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 670 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 671 interrupt-names = "host", "peripheral"; 672 maximum-speed = "high-speed"; 673 dr_mode = "otg"; 674 snps,usb2-gadget-lpm-disable; 675 snps,usb2-lpm-disable; 676 }; 677 }; 678 679 fss: bus@fc00000 { 680 compatible = "simple-bus"; 681 reg = <0x00 0x0fc00000 0x00 0x70000>; 682 #address-cells = <2>; 683 #size-cells = <2>; 684 ranges; 685 686 ospi0: spi@fc40000 { 687 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 688 reg = <0x00 0x0fc40000 0x00 0x100>, 689 <0x05 0x00000000 0x01 0x00000000>; 690 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 691 cdns,fifo-depth = <256>; 692 cdns,fifo-width = <4>; 693 cdns,trigger-address = <0x0>; 694 clocks = <&k3_clks 75 7>; 695 assigned-clocks = <&k3_clks 75 7>; 696 assigned-clock-parents = <&k3_clks 75 8>; 697 assigned-clock-rates = <166666666>; 698 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 status = "disabled"; 702 }; 703 }; 704 705 gpu: gpu@fd00000 { 706 compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", 707 "img,img-rogue"; 708 reg = <0x00 0x0fd00000 0x00 0x20000>; 709 clocks = <&k3_clks 187 0>; 710 clock-names = "core"; 711 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 712 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 713 power-domain-names = "a"; 714 }; 715 716 cpsw3g: ethernet@8000000 { 717 compatible = "ti,am642-cpsw-nuss"; 718 #address-cells = <2>; 719 #size-cells = <2>; 720 reg = <0x00 0x08000000 0x00 0x200000>; 721 reg-names = "cpsw_nuss"; 722 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 723 clocks = <&k3_clks 13 0>; 724 assigned-clocks = <&k3_clks 13 3>; 725 assigned-clock-parents = <&k3_clks 13 11>; 726 clock-names = "fck"; 727 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 728 729 dmas = <&main_pktdma 0xc600 15>, 730 <&main_pktdma 0xc601 15>, 731 <&main_pktdma 0xc602 15>, 732 <&main_pktdma 0xc603 15>, 733 <&main_pktdma 0xc604 15>, 734 <&main_pktdma 0xc605 15>, 735 <&main_pktdma 0xc606 15>, 736 <&main_pktdma 0xc607 15>, 737 <&main_pktdma 0x4600 15>; 738 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 739 "tx7", "rx"; 740 741 status = "disabled"; 742 743 ethernet-ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 cpsw_port1: port@1 { 748 reg = <1>; 749 ti,mac-only; 750 label = "port1"; 751 phys = <&phy_gmii_sel 1>; 752 mac-address = [00 00 00 00 00 00]; 753 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 754 }; 755 756 cpsw_port2: port@2 { 757 reg = <2>; 758 ti,mac-only; 759 label = "port2"; 760 phys = <&phy_gmii_sel 2>; 761 mac-address = [00 00 00 00 00 00]; 762 }; 763 }; 764 765 cpsw3g_mdio: mdio@f00 { 766 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 767 reg = <0x00 0xf00 0x00 0x100>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 clocks = <&k3_clks 13 0>; 771 clock-names = "fck"; 772 bus_freq = <1000000>; 773 status = "disabled"; 774 }; 775 776 cpts@3d000 { 777 compatible = "ti,j721e-cpts"; 778 reg = <0x00 0x3d000 0x00 0x400>; 779 clocks = <&k3_clks 13 3>; 780 clock-names = "cpts"; 781 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 782 interrupt-names = "cpts"; 783 ti,cpts-ext-ts-inputs = <4>; 784 ti,cpts-periodic-outputs = <2>; 785 }; 786 }; 787 788 dss: dss@30200000 { 789 compatible = "ti,am625-dss"; 790 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 791 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 792 <0x00 0x30206000 0x00 0x1000>, /* vid */ 793 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 794 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 795 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 796 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 797 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 798 reg-names = "common", "vidl1", "vid", 799 "ovr1", "ovr2", "vp1", "vp2", "common1"; 800 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 801 clocks = <&k3_clks 186 6>, 802 <&dss_vp1_clk>, 803 <&k3_clks 186 2>; 804 clock-names = "fck", "vp1", "vp2"; 805 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 806 status = "disabled"; 807 808 oldi-transmitters { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 812 oldi0: oldi@0 { 813 reg = <0>; 814 clocks = <&k3_clks 186 0>; 815 clock-names = "serial"; 816 ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; 817 status = "disabled"; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 oldi0_port0: port@0 { 824 reg = <0>; 825 }; 826 827 oldi0_port1: port@1 { 828 reg = <1>; 829 }; 830 }; 831 }; 832 833 oldi1: oldi@1 { 834 reg = <1>; 835 clocks = <&k3_clks 186 0>; 836 clock-names = "serial"; 837 ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; 838 status = "disabled"; 839 840 ports { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 844 oldi1_port0: port@0 { 845 reg = <0>; 846 }; 847 848 oldi1_port1: port@1 { 849 reg = <1>; 850 }; 851 }; 852 }; 853 }; 854 855 dss_ports: ports { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 }; 859 }; 860 861 hwspinlock: spinlock@2a000000 { 862 compatible = "ti,am64-hwspinlock"; 863 reg = <0x00 0x2a000000 0x00 0x1000>; 864 #hwlock-cells = <1>; 865 }; 866 867 mailbox0_cluster0: mailbox@29000000 { 868 compatible = "ti,am64-mailbox"; 869 reg = <0x00 0x29000000 0x00 0x200>; 870 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 872 #mbox-cells = <1>; 873 ti,mbox-num-users = <4>; 874 ti,mbox-num-fifos = <16>; 875 status = "disabled"; 876 }; 877 878 ecap0: pwm@23100000 { 879 compatible = "ti,am3352-ecap"; 880 #pwm-cells = <3>; 881 reg = <0x00 0x23100000 0x00 0x100>; 882 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 883 clocks = <&k3_clks 51 0>; 884 clock-names = "fck"; 885 status = "disabled"; 886 }; 887 888 ecap1: pwm@23110000 { 889 compatible = "ti,am3352-ecap"; 890 #pwm-cells = <3>; 891 reg = <0x00 0x23110000 0x00 0x100>; 892 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 893 clocks = <&k3_clks 52 0>; 894 clock-names = "fck"; 895 status = "disabled"; 896 }; 897 898 ecap2: pwm@23120000 { 899 compatible = "ti,am3352-ecap"; 900 #pwm-cells = <3>; 901 reg = <0x00 0x23120000 0x00 0x100>; 902 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 903 clocks = <&k3_clks 53 0>; 904 clock-names = "fck"; 905 status = "disabled"; 906 }; 907 908 eqep0: counter@23200000 { 909 compatible = "ti,am62-eqep"; 910 reg = <0x00 0x23200000 0x00 0x100>; 911 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 912 clocks = <&k3_clks 59 0>; 913 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 914 status = "disabled"; 915 }; 916 917 eqep1: counter@23210000 { 918 compatible = "ti,am62-eqep"; 919 reg = <0x00 0x23210000 0x00 0x100>; 920 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 921 clocks = <&k3_clks 60 0>; 922 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 923 status = "disabled"; 924 }; 925 926 eqep2: counter@23220000 { 927 compatible = "ti,am62-eqep"; 928 reg = <0x00 0x23220000 0x00 0x100>; 929 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&k3_clks 62 0>; 931 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 932 status = "disabled"; 933 }; 934 935 main_mcan0: can@20701000 { 936 compatible = "bosch,m_can"; 937 reg = <0x00 0x20701000 0x00 0x200>, 938 <0x00 0x20708000 0x00 0x8000>; 939 reg-names = "m_can", "message_ram"; 940 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 941 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 942 clock-names = "hclk", "cclk"; 943 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "int0", "int1"; 946 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 947 status = "disabled"; 948 }; 949 950 main_rti0: watchdog@e000000 { 951 compatible = "ti,j7-rti-wdt"; 952 reg = <0x00 0x0e000000 0x00 0x100>; 953 clocks = <&k3_clks 125 0>; 954 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 955 assigned-clocks = <&k3_clks 125 0>; 956 assigned-clock-parents = <&k3_clks 125 2>; 957 }; 958 959 main_rti1: watchdog@e010000 { 960 compatible = "ti,j7-rti-wdt"; 961 reg = <0x00 0x0e010000 0x00 0x100>; 962 clocks = <&k3_clks 126 0>; 963 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 964 assigned-clocks = <&k3_clks 126 0>; 965 assigned-clock-parents = <&k3_clks 126 2>; 966 }; 967 968 main_rti2: watchdog@e020000 { 969 compatible = "ti,j7-rti-wdt"; 970 reg = <0x00 0x0e020000 0x00 0x100>; 971 clocks = <&k3_clks 127 0>; 972 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 973 assigned-clocks = <&k3_clks 127 0>; 974 assigned-clock-parents = <&k3_clks 127 2>; 975 }; 976 977 main_rti3: watchdog@e030000 { 978 compatible = "ti,j7-rti-wdt"; 979 reg = <0x00 0x0e030000 0x00 0x100>; 980 clocks = <&k3_clks 128 0>; 981 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 982 assigned-clocks = <&k3_clks 128 0>; 983 assigned-clock-parents = <&k3_clks 128 2>; 984 }; 985 986 main_rti15: watchdog@e0f0000 { 987 compatible = "ti,j7-rti-wdt"; 988 reg = <0x00 0x0e0f0000 0x00 0x100>; 989 clocks = <&k3_clks 130 0>; 990 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 991 assigned-clocks = <&k3_clks 130 0>; 992 assigned-clock-parents = <&k3_clks 130 2>; 993 }; 994 995 epwm0: pwm@23000000 { 996 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 997 #pwm-cells = <3>; 998 reg = <0x00 0x23000000 0x00 0x100>; 999 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1000 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1001 clock-names = "tbclk", "fck"; 1002 status = "disabled"; 1003 }; 1004 1005 epwm1: pwm@23010000 { 1006 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1007 #pwm-cells = <3>; 1008 reg = <0x00 0x23010000 0x00 0x100>; 1009 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1010 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1011 clock-names = "tbclk", "fck"; 1012 status = "disabled"; 1013 }; 1014 1015 epwm2: pwm@23020000 { 1016 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1017 #pwm-cells = <3>; 1018 reg = <0x00 0x23020000 0x00 0x100>; 1019 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1020 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1021 clock-names = "tbclk", "fck"; 1022 status = "disabled"; 1023 }; 1024 1025 mcasp0: audio-controller@2b00000 { 1026 compatible = "ti,am33xx-mcasp-audio"; 1027 reg = <0x00 0x02b00000 0x00 0x2000>, 1028 <0x00 0x02b08000 0x00 0x400>; 1029 reg-names = "mpu", "dat"; 1030 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "tx", "rx"; 1033 1034 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 1035 dma-names = "tx", "rx"; 1036 1037 clocks = <&k3_clks 190 0>; 1038 clock-names = "fck"; 1039 assigned-clocks = <&k3_clks 190 0>; 1040 assigned-clock-parents = <&k3_clks 190 2>; 1041 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1042 status = "disabled"; 1043 }; 1044 1045 mcasp1: audio-controller@2b10000 { 1046 compatible = "ti,am33xx-mcasp-audio"; 1047 reg = <0x00 0x02b10000 0x00 0x2000>, 1048 <0x00 0x02b18000 0x00 0x400>; 1049 reg-names = "mpu", "dat"; 1050 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupt-names = "tx", "rx"; 1053 1054 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1055 dma-names = "tx", "rx"; 1056 1057 clocks = <&k3_clks 191 0>; 1058 clock-names = "fck"; 1059 assigned-clocks = <&k3_clks 191 0>; 1060 assigned-clock-parents = <&k3_clks 191 2>; 1061 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1062 status = "disabled"; 1063 }; 1064 1065 mcasp2: audio-controller@2b20000 { 1066 compatible = "ti,am33xx-mcasp-audio"; 1067 reg = <0x00 0x02b20000 0x00 0x2000>, 1068 <0x00 0x02b28000 0x00 0x400>; 1069 reg-names = "mpu", "dat"; 1070 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1072 interrupt-names = "tx", "rx"; 1073 1074 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1075 dma-names = "tx", "rx"; 1076 1077 clocks = <&k3_clks 192 0>; 1078 clock-names = "fck"; 1079 assigned-clocks = <&k3_clks 192 0>; 1080 assigned-clock-parents = <&k3_clks 192 2>; 1081 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1082 status = "disabled"; 1083 }; 1084 1085 ti_csi2rx0: ticsi2rx@30102000 { 1086 compatible = "ti,j721e-csi2rx-shim"; 1087 dmas = <&main_bcdma 0 0x4700 0>; 1088 dma-names = "rx0"; 1089 reg = <0x00 0x30102000 0x00 0x1000>; 1090 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1091 #address-cells = <2>; 1092 #size-cells = <2>; 1093 ranges; 1094 status = "disabled"; 1095 1096 cdns_csi2rx0: csi-bridge@30101000 { 1097 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1098 reg = <0x00 0x30101000 0x00 0x1000>; 1099 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "error_irq", "irq"; 1102 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1103 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1104 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1105 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1106 phys = <&dphy0>; 1107 phy-names = "dphy"; 1108 1109 ports { 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 csi0_port0: port@0 { 1114 reg = <0>; 1115 status = "disabled"; 1116 }; 1117 1118 csi0_port1: port@1 { 1119 reg = <1>; 1120 status = "disabled"; 1121 }; 1122 1123 csi0_port2: port@2 { 1124 reg = <2>; 1125 status = "disabled"; 1126 }; 1127 1128 csi0_port3: port@3 { 1129 reg = <3>; 1130 status = "disabled"; 1131 }; 1132 1133 csi0_port4: port@4 { 1134 reg = <4>; 1135 status = "disabled"; 1136 }; 1137 }; 1138 }; 1139 }; 1140 1141 dphy0: phy@30110000 { 1142 compatible = "cdns,dphy-rx"; 1143 reg = <0x00 0x30110000 0x00 0x1100>; 1144 #phy-cells = <0>; 1145 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1146 status = "disabled"; 1147 }; 1148 1149 pruss: pruss@30040000 { 1150 compatible = "ti,am625-pruss"; 1151 reg = <0x00 0x30040000 0x00 0x80000>; 1152 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1153 #address-cells = <1>; 1154 #size-cells = <1>; 1155 ranges = <0x0 0x00 0x30040000 0x80000>; 1156 1157 pruss_mem: memories@0 { 1158 reg = <0x0 0x2000>, 1159 <0x2000 0x2000>, 1160 <0x10000 0x10000>; 1161 reg-names = "dram0", "dram1", "shrdram2"; 1162 }; 1163 1164 pruss_cfg: cfg@26000 { 1165 compatible = "ti,pruss-cfg", "syscon"; 1166 reg = <0x26000 0x200>; 1167 #address-cells = <1>; 1168 #size-cells = <1>; 1169 ranges = <0x0 0x26000 0x2000>; 1170 1171 clocks { 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 pruss_coreclk_mux: coreclk-mux@3c { 1176 reg = <0x3c>; 1177 #clock-cells = <0>; 1178 clocks = <&k3_clks 81 0>, /* pruss_core_clk */ 1179 <&k3_clks 81 14>; /* pruss_iclk */ 1180 assigned-clocks = <&pruss_coreclk_mux>; 1181 assigned-clock-parents = <&k3_clks 81 14>; 1182 }; 1183 1184 pruss_iepclk_mux: iepclk-mux@30 { 1185 reg = <0x30>; 1186 #clock-cells = <0>; 1187 clocks = <&k3_clks 81 3>, /* pruss_iep_clk */ 1188 <&pruss_coreclk_mux>; /* pruss_coreclk_mux */ 1189 assigned-clocks = <&pruss_iepclk_mux>; 1190 assigned-clock-parents = <&pruss_coreclk_mux>; 1191 }; 1192 }; 1193 }; 1194 1195 pruss_intc: interrupt-controller@20000 { 1196 compatible = "ti,pruss-intc"; 1197 reg = <0x20000 0x2000>; 1198 interrupt-controller; 1199 #interrupt-cells = <3>; 1200 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1208 interrupt-names = "host_intr0", "host_intr1", 1209 "host_intr2", "host_intr3", 1210 "host_intr4", "host_intr5", 1211 "host_intr6", "host_intr7"; 1212 }; 1213 1214 pru0: pru@34000 { 1215 compatible = "ti,am625-pru"; 1216 reg = <0x34000 0x3000>, 1217 <0x22000 0x100>, 1218 <0x22400 0x100>; 1219 reg-names = "iram", "control", "debug"; 1220 firmware-name = "am62x-pru0-fw"; 1221 interrupt-parent = <&pruss_intc>; 1222 interrupts = <16 2 2>; 1223 interrupt-names = "vring"; 1224 }; 1225 1226 pru1: pru@38000 { 1227 compatible = "ti,am625-pru"; 1228 reg = <0x38000 0x3000>, 1229 <0x24000 0x100>, 1230 <0x24400 0x100>; 1231 reg-names = "iram", "control", "debug"; 1232 firmware-name = "am62x-pru1-fw"; 1233 interrupt-parent = <&pruss_intc>; 1234 interrupts = <18 3 3>; 1235 interrupt-names = "vring"; 1236 }; 1237 }; 1238 1239 gpmc0: memory-controller@3b000000 { 1240 compatible = "ti,am64-gpmc"; 1241 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1242 clocks = <&k3_clks 80 0>; 1243 clock-names = "fck"; 1244 reg = <0x00 0x03b000000 0x00 0x400>, 1245 <0x00 0x050000000 0x00 0x8000000>; 1246 reg-names = "cfg", "data"; 1247 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1248 gpmc,num-cs = <3>; 1249 gpmc,num-waitpins = <2>; 1250 #address-cells = <2>; 1251 #size-cells = <1>; 1252 interrupt-controller; 1253 #interrupt-cells = <2>; 1254 gpio-controller; 1255 #gpio-cells = <2>; 1256 status = "disabled"; 1257 }; 1258 1259 elm0: ecc@25010000 { 1260 compatible = "ti,am64-elm"; 1261 reg = <0x00 0x25010000 0x00 0x2000>; 1262 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1263 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1264 clocks = <&k3_clks 54 0>; 1265 clock-names = "fck"; 1266 status = "disabled"; 1267 }; 1268};
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