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fsd.dtsi
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linux-6.19.14/arch/arm64/boot/dts/tesla/fsd.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Tesla Full Self-Driving SoC device tree source 4 * 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2017-2022 Tesla, Inc. 8 * https://www.tesla.com 9 */ 10 11#include <dt-bindings/clock/fsd-clk.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "tesla,fsd"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &hsi2c_0; 22 i2c1 = &hsi2c_1; 23 i2c2 = &hsi2c_2; 24 i2c3 = &hsi2c_3; 25 i2c4 = &hsi2c_4; 26 i2c5 = &hsi2c_5; 27 i2c6 = &hsi2c_6; 28 i2c7 = &hsi2c_7; 29 pinctrl0 = &pinctrl_fsys0; 30 pinctrl1 = &pinctrl_peric; 31 pinctrl2 = &pinctrl_pmu; 32 spi0 = &spi_0; 33 spi1 = &spi_1; 34 spi2 = &spi_2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpucl0_0>; 45 }; 46 core1 { 47 cpu = <&cpucl0_1>; 48 }; 49 core2 { 50 cpu = <&cpucl0_2>; 51 }; 52 core3 { 53 cpu = <&cpucl0_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpucl1_0>; 60 }; 61 core1 { 62 cpu = <&cpucl1_1>; 63 }; 64 core2 { 65 cpu = <&cpucl1_2>; 66 }; 67 core3 { 68 cpu = <&cpucl1_3>; 69 }; 70 }; 71 72 cluster2 { 73 core0 { 74 cpu = <&cpucl2_0>; 75 }; 76 core1 { 77 cpu = <&cpucl2_1>; 78 }; 79 core2 { 80 cpu = <&cpucl2_2>; 81 }; 82 core3 { 83 cpu = <&cpucl2_3>; 84 }; 85 }; 86 }; 87 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x0 0x000>; 93 enable-method = "psci"; 94 clock-frequency = <2400000000>; 95 cpu-idle-states = <&cpu_sleep>; 96 i-cache-size = <0xc000>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <256>; 99 d-cache-size = <0x8000>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <256>; 102 next-level-cache = <&cpucl_l2>; 103 }; 104 105 cpucl0_1: cpu@1 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a72"; 108 reg = <0x0 0x001>; 109 enable-method = "psci"; 110 clock-frequency = <2400000000>; 111 cpu-idle-states = <&cpu_sleep>; 112 i-cache-size = <0xc000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <256>; 118 next-level-cache = <&cpucl_l2>; 119 }; 120 121 cpucl0_2: cpu@2 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a72"; 124 reg = <0x0 0x002>; 125 enable-method = "psci"; 126 clock-frequency = <2400000000>; 127 cpu-idle-states = <&cpu_sleep>; 128 i-cache-size = <0xc000>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <256>; 131 d-cache-size = <0x8000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; 134 next-level-cache = <&cpucl_l2>; 135 }; 136 137 cpucl0_3: cpu@3 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a72"; 140 reg = <0x0 0x003>; 141 enable-method = "psci"; 142 cpu-idle-states = <&cpu_sleep>; 143 i-cache-size = <0xc000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <256>; 149 next-level-cache = <&cpucl_l2>; 150 }; 151 152 /* Cluster 1 */ 153 cpucl1_0: cpu@100 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72"; 156 reg = <0x0 0x100>; 157 enable-method = "psci"; 158 clock-frequency = <2400000000>; 159 cpu-idle-states = <&cpu_sleep>; 160 i-cache-size = <0xc000>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <0x8000>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <256>; 166 next-level-cache = <&cpucl_l2>; 167 }; 168 169 cpucl1_1: cpu@101 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a72"; 172 reg = <0x0 0x101>; 173 enable-method = "psci"; 174 clock-frequency = <2400000000>; 175 cpu-idle-states = <&cpu_sleep>; 176 i-cache-size = <0xc000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x8000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&cpucl_l2>; 183 }; 184 185 cpucl1_2: cpu@102 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a72"; 188 reg = <0x0 0x102>; 189 enable-method = "psci"; 190 clock-frequency = <2400000000>; 191 cpu-idle-states = <&cpu_sleep>; 192 i-cache-size = <0xc000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&cpucl_l2>; 199 }; 200 201 cpucl1_3: cpu@103 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a72"; 204 reg = <0x0 0x103>; 205 enable-method = "psci"; 206 clock-frequency = <2400000000>; 207 cpu-idle-states = <&cpu_sleep>; 208 i-cache-size = <0xc000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <256>; 211 d-cache-size = <0x8000>; 212 d-cache-line-size = <64>; 213 d-cache-sets = <256>; 214 next-level-cache = <&cpucl_l2>; 215 }; 216 217 /* Cluster 2 */ 218 cpucl2_0: cpu@200 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-a72"; 221 reg = <0x0 0x200>; 222 enable-method = "psci"; 223 clock-frequency = <2400000000>; 224 cpu-idle-states = <&cpu_sleep>; 225 i-cache-size = <0xc000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <256>; 228 d-cache-size = <0x8000>; 229 d-cache-line-size = <64>; 230 d-cache-sets = <256>; 231 next-level-cache = <&cpucl_l2>; 232 }; 233 234 cpucl2_1: cpu@201 { 235 device_type = "cpu"; 236 compatible = "arm,cortex-a72"; 237 reg = <0x0 0x201>; 238 enable-method = "psci"; 239 clock-frequency = <2400000000>; 240 cpu-idle-states = <&cpu_sleep>; 241 i-cache-size = <0xc000>; 242 i-cache-line-size = <64>; 243 i-cache-sets = <256>; 244 d-cache-size = <0x8000>; 245 d-cache-line-size = <64>; 246 d-cache-sets = <256>; 247 next-level-cache = <&cpucl_l2>; 248 }; 249 250 cpucl2_2: cpu@202 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 reg = <0x0 0x202>; 254 enable-method = "psci"; 255 clock-frequency = <2400000000>; 256 cpu-idle-states = <&cpu_sleep>; 257 i-cache-size = <0xc000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <256>; 260 d-cache-size = <0x8000>; 261 d-cache-line-size = <64>; 262 d-cache-sets = <256>; 263 next-level-cache = <&cpucl_l2>; 264 }; 265 266 cpucl2_3: cpu@203 { 267 device_type = "cpu"; 268 compatible = "arm,cortex-a72"; 269 reg = <0x0 0x203>; 270 enable-method = "psci"; 271 clock-frequency = <2400000000>; 272 cpu-idle-states = <&cpu_sleep>; 273 i-cache-size = <0xc000>; 274 i-cache-line-size = <64>; 275 i-cache-sets = <256>; 276 d-cache-size = <0x8000>; 277 d-cache-line-size = <64>; 278 d-cache-sets = <256>; 279 next-level-cache = <&cpucl_l2>; 280 }; 281 282 cpucl_l2: l2-cache0 { 283 compatible = "cache"; 284 cache-level = <2>; 285 cache-unified; 286 cache-size = <0x400000>; 287 cache-line-size = <64>; 288 cache-sets = <4096>; 289 }; 290 291 idle-states { 292 entry-method = "psci"; 293 294 cpu_sleep: cpu-sleep { 295 idle-state-name = "c2"; 296 compatible = "arm,idle-state"; 297 local-timer-stop; 298 arm,psci-suspend-param = <0x0010000>; 299 entry-latency-us = <30>; 300 exit-latency-us = <75>; 301 min-residency-us = <300>; 302 }; 303 }; 304 }; 305 306 arm-pmu { 307 compatible = "arm,cortex-a72-pmu"; 308 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, 321 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, 322 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, 323 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; 324 }; 325 326 psci { 327 compatible = "arm,psci-1.0"; 328 method = "smc"; 329 }; 330 331 timer { 332 compatible = "arm,armv8-timer"; 333 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 334 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 335 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 336 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 337 }; 338 339 fin_pll: clock { 340 compatible = "fixed-clock"; 341 clock-output-names = "fin_pll"; 342 #clock-cells = <0>; 343 }; 344 345 reserved-memory { 346 #address-cells = <2>; 347 #size-cells = <2>; 348 ranges; 349 350 mfc_left: region@84000000 { 351 compatible = "shared-dma-pool"; 352 no-map; 353 reg = <0 0x84000000 0 0x8000000>; 354 }; 355 }; 356 357 soc: soc@0 { 358 compatible = "simple-bus"; 359 #address-cells = <2>; 360 #size-cells = <2>; 361 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; 362 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 363 364 gic: interrupt-controller@10400000 { 365 compatible = "arm,gic-v3"; 366 #address-cells = <0>; 367 #interrupt-cells = <3>; 368 interrupt-controller; 369 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ 370 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ 371 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 372 }; 373 374 smmu_imem: iommu@10200000 { 375 compatible = "arm,mmu-500"; 376 reg = <0x0 0x10200000 0x0 0x10000>; 377 #iommu-cells = <2>; 378 #global-interrupts = <7>; 379 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 380 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 381 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 382 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 383 /* Performance counter interrupts */ 384 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */ 385 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */ 386 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */ 387 /* Per context non-secure context interrupts, 0-3 interrupts */ 388 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 389 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 390 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 391 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */ 392 }; 393 394 smmu_isp: iommu@12100000 { 395 compatible = "arm,mmu-500"; 396 reg = <0x0 0x12100000 0x0 0x10000>; 397 #iommu-cells = <2>; 398 #global-interrupts = <11>; 399 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 400 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 401 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 402 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 403 /* Performance counter interrupts */ 404 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */ 405 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */ 406 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */ 407 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */ 408 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */ 409 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */ 410 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */ 411 /* Per context non-secure context interrupts, 0-7 interrupts */ 412 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 413 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 414 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 415 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */ 416 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */ 417 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */ 418 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */ 419 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */ 420 }; 421 422 smmu_peric: iommu@14900000 { 423 compatible = "arm,mmu-500"; 424 reg = <0x0 0x14900000 0x0 0x10000>; 425 #iommu-cells = <2>; 426 #global-interrupts = <5>; 427 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 428 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 429 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 430 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 431 /* Performance counter interrupts */ 432 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */ 433 /* Per context non-secure context interrupts, 0-1 interrupts */ 434 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 435 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 436 }; 437 438 smmu_fsys0: iommu@15450000 { 439 compatible = "arm,mmu-500"; 440 reg = <0x0 0x15450000 0x0 0x10000>; 441 #iommu-cells = <2>; 442 #global-interrupts = <5>; 443 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 444 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 445 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 446 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 447 /* Performance counter interrupts */ 448 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */ 449 /* Per context non-secure context interrupts, 0-1 interrupts */ 450 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 451 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 452 }; 453 454 clock_imem: clock-controller@10010000 { 455 compatible = "tesla,fsd-clock-imem"; 456 reg = <0x0 0x10010000 0x0 0x3000>; 457 #clock-cells = <1>; 458 clocks = <&fin_pll>, 459 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, 460 <&clock_cmu DOUT_CMU_IMEM_ACLK>, 461 <&clock_cmu DOUT_CMU_IMEM_DMACLK>; 462 clock-names = "fin_pll", 463 "dout_cmu_imem_tcuclk", 464 "dout_cmu_imem_aclk", 465 "dout_cmu_imem_dmaclk"; 466 }; 467 468 clock_cmu: clock-controller@11c10000 { 469 compatible = "tesla,fsd-clock-cmu"; 470 reg = <0x0 0x11c10000 0x0 0x3000>; 471 #clock-cells = <1>; 472 clocks = <&fin_pll>; 473 clock-names = "fin_pll"; 474 }; 475 476 clock_csi: clock-controller@12610000 { 477 compatible = "tesla,fsd-clock-cam_csi"; 478 reg = <0x0 0x12610000 0x0 0x3000>; 479 #clock-cells = <1>; 480 clocks = <&fin_pll>; 481 clock-names = "fin_pll"; 482 }; 483 484 sysreg_cam: system-controller@12630000 { 485 compatible = "tesla,fsd-cam-sysreg", "syscon"; 486 reg = <0x0 0x12630000 0x0 0x500>; 487 }; 488 489 clock_mfc: clock-controller@12810000 { 490 compatible = "tesla,fsd-clock-mfc"; 491 reg = <0x0 0x12810000 0x0 0x3000>; 492 #clock-cells = <1>; 493 clocks = <&fin_pll>; 494 clock-names = "fin_pll"; 495 }; 496 497 clock_peric: clock-controller@14010000 { 498 compatible = "tesla,fsd-clock-peric"; 499 reg = <0x0 0x14010000 0x0 0x3000>; 500 #clock-cells = <1>; 501 clocks = <&fin_pll>, 502 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, 503 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, 504 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, 505 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, 506 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; 507 clock-names = "fin_pll", 508 "dout_cmu_pll_shared0_div4", 509 "dout_cmu_peric_shared1div36", 510 "dout_cmu_peric_shared0div3_tbuclk", 511 "dout_cmu_peric_shared0div20", 512 "dout_cmu_peric_shared1div4_dmaclk"; 513 }; 514 515 sysreg_peric: system-controller@14030000 { 516 compatible = "tesla,fsd-peric-sysreg", "syscon"; 517 reg = <0x0 0x14030000 0x0 0x1000>; 518 }; 519 520 clock_fsys0: clock-controller@15010000 { 521 compatible = "tesla,fsd-clock-fsys0"; 522 reg = <0x0 0x15010000 0x0 0x3000>; 523 #clock-cells = <1>; 524 clocks = <&fin_pll>, 525 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, 526 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, 527 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; 528 clock-names = "fin_pll", 529 "dout_cmu_pll_shared0_div6", 530 "dout_cmu_fsys0_shared1div4", 531 "dout_cmu_fsys0_shared0div4"; 532 }; 533 534 sysreg_fsys0: system-controller@15030000 { 535 compatible = "tesla,fsd-fsys0-sysreg", "syscon"; 536 reg = <0x0 0x15030000 0x0 0x1000>; 537 }; 538 539 clock_fsys1: clock-controller@16810000 { 540 compatible = "tesla,fsd-clock-fsys1"; 541 reg = <0x0 0x16810000 0x0 0x3000>; 542 #clock-cells = <1>; 543 clocks = <&fin_pll>, 544 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, 545 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; 546 clock-names = "fin_pll", 547 "dout_cmu_fsys1_shared0div8", 548 "dout_cmu_fsys1_shared0div4"; 549 }; 550 551 sysreg_fsys1: system-controller@16830000 { 552 compatible = "tesla,fsd-fsys1-sysreg", "syscon"; 553 reg = <0x0 0x16830000 0x0 0x1000>; 554 }; 555 556 mdma0: dma-controller@10100000 { 557 compatible = "arm,pl330", "arm,primecell"; 558 reg = <0x0 0x10100000 0x0 0x1000>; 559 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 560 #dma-cells = <1>; 561 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; 562 clock-names = "apb_pclk"; 563 iommus = <&smmu_imem 0x800 0x0>; 564 }; 565 566 mdma1: dma-controller@10110000 { 567 compatible = "arm,pl330", "arm,primecell"; 568 reg = <0x0 0x10110000 0x0 0x1000>; 569 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 570 #dma-cells = <1>; 571 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; 572 clock-names = "apb_pclk"; 573 iommus = <&smmu_imem 0x801 0x0>; 574 }; 575 576 pdma0: dma-controller@14280000 { 577 compatible = "arm,pl330", "arm,primecell"; 578 reg = <0x0 0x14280000 0x0 0x1000>; 579 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 580 #dma-cells = <1>; 581 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; 582 clock-names = "apb_pclk"; 583 iommus = <&smmu_peric 0x2 0x0>; 584 }; 585 586 pdma1: dma-controller@14290000 { 587 compatible = "arm,pl330", "arm,primecell"; 588 reg = <0x0 0x14290000 0x0 0x1000>; 589 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 590 #dma-cells = <1>; 591 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; 592 clock-names = "apb_pclk"; 593 iommus = <&smmu_peric 0x1 0x0>; 594 }; 595 596 serial_0: serial@14180000 { 597 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart"; 598 reg = <0x0 0x14180000 0x0 0x100>; 599 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 600 dmas = <&pdma1 1>, <&pdma1 0>; 601 dma-names = "rx", "tx"; 602 clocks = <&clock_peric PERIC_PCLK_UART0>, 603 <&clock_peric PERIC_SCLK_UART0>; 604 clock-names = "uart", "clk_uart_baud0"; 605 samsung,uart-fifosize = <64>; 606 status = "disabled"; 607 }; 608 609 serial_1: serial@14190000 { 610 compatible = "tesla,fsd-uart", "samsung,exynos4210-uart"; 611 reg = <0x0 0x14190000 0x0 0x100>; 612 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 613 dmas = <&pdma1 3>, <&pdma1 2>; 614 dma-names = "rx", "tx"; 615 clocks = <&clock_peric PERIC_PCLK_UART1>, 616 <&clock_peric PERIC_SCLK_UART1>; 617 clock-names = "uart", "clk_uart_baud0"; 618 samsung,uart-fifosize = <64>; 619 status = "disabled"; 620 }; 621 622 pmu_system_controller: system-controller@11400000 { 623 compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon"; 624 reg = <0x0 0x11400000 0x0 0x5000>; 625 }; 626 627 watchdog_0: watchdog@100a0000 { 628 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 629 reg = <0x0 0x100a0000 0x0 0x100>; 630 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 631 samsung,syscon-phandle = <&pmu_system_controller>; 632 clocks = <&fin_pll>; 633 clock-names = "watchdog"; 634 }; 635 636 watchdog_1: watchdog@100b0000 { 637 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 638 reg = <0x0 0x100b0000 0x0 0x100>; 639 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 640 samsung,syscon-phandle = <&pmu_system_controller>; 641 clocks = <&fin_pll>; 642 clock-names = "watchdog"; 643 }; 644 645 watchdog_2: watchdog@100c0000 { 646 compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt"; 647 reg = <0x0 0x100c0000 0x0 0x100>; 648 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 649 samsung,syscon-phandle = <&pmu_system_controller>; 650 clocks = <&fin_pll>; 651 clock-names = "watchdog"; 652 }; 653 654 pwm_0: pwm@14100000 { 655 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm"; 656 reg = <0x0 0x14100000 0x0 0x100>; 657 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 658 #pwm-cells = <3>; 659 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; 660 clock-names = "timers"; 661 status = "disabled"; 662 }; 663 664 pwm_1: pwm@14110000 { 665 compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm"; 666 reg = <0x0 0x14110000 0x0 0x100>; 667 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 668 #pwm-cells = <3>; 669 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; 670 clock-names = "timers"; 671 status = "disabled"; 672 }; 673 674 hsi2c_0: i2c@14200000 { 675 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 676 reg = <0x0 0x14200000 0x0 0x1000>; 677 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&hs_i2c0_bus>; 682 clocks = <&clock_peric PERIC_PCLK_HSI2C0>; 683 clock-names = "hsi2c"; 684 status = "disabled"; 685 }; 686 687 hsi2c_1: i2c@14210000 { 688 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 689 reg = <0x0 0x14210000 0x0 0x1000>; 690 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&hs_i2c1_bus>; 695 clocks = <&clock_peric PERIC_PCLK_HSI2C1>; 696 clock-names = "hsi2c"; 697 status = "disabled"; 698 }; 699 700 hsi2c_2: i2c@14220000 { 701 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 702 reg = <0x0 0x14220000 0x0 0x1000>; 703 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&hs_i2c2_bus>; 708 clocks = <&clock_peric PERIC_PCLK_HSI2C2>; 709 clock-names = "hsi2c"; 710 status = "disabled"; 711 }; 712 713 hsi2c_3: i2c@14230000 { 714 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 715 reg = <0x0 0x14230000 0x0 0x1000>; 716 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&hs_i2c3_bus>; 721 clocks = <&clock_peric PERIC_PCLK_HSI2C3>; 722 clock-names = "hsi2c"; 723 status = "disabled"; 724 }; 725 726 hsi2c_4: i2c@14240000 { 727 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 728 reg = <0x0 0x14240000 0x0 0x1000>; 729 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&hs_i2c4_bus>; 734 clocks = <&clock_peric PERIC_PCLK_HSI2C4>; 735 clock-names = "hsi2c"; 736 status = "disabled"; 737 }; 738 739 hsi2c_5: i2c@14250000 { 740 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 741 reg = <0x0 0x14250000 0x0 0x1000>; 742 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&hs_i2c5_bus>; 747 clocks = <&clock_peric PERIC_PCLK_HSI2C5>; 748 clock-names = "hsi2c"; 749 status = "disabled"; 750 }; 751 752 hsi2c_6: i2c@14260000 { 753 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 754 reg = <0x0 0x14260000 0x0 0x1000>; 755 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&hs_i2c6_bus>; 760 clocks = <&clock_peric PERIC_PCLK_HSI2C6>; 761 clock-names = "hsi2c"; 762 status = "disabled"; 763 }; 764 765 hsi2c_7: i2c@14270000 { 766 compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c"; 767 reg = <0x0 0x14270000 0x0 0x1000>; 768 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&hs_i2c7_bus>; 773 clocks = <&clock_peric PERIC_PCLK_HSI2C7>; 774 clock-names = "hsi2c"; 775 status = "disabled"; 776 }; 777 778 i2s_0: i2s@140e0000 { 779 compatible = "tesla,fsd-i2s"; 780 reg = <0x0 0x140e0000 0x0 0x100>; 781 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 782 dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; 783 dma-names = "tx", "rx", "tx-sec"; 784 #clock-cells = <1>; 785 clocks = <&clock_peric PERIC_PCLK_TDM0>, 786 <&clock_peric PERIC_HCLK_TDM0>, 787 <&clock_peric PERIC_HCLK_TDM0>; 788 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&i2s0_bus>; 791 #sound-dai-cells = <1>; 792 status = "disabled"; 793 }; 794 795 i2s_1: i2s@140f0000 { 796 compatible = "tesla,fsd-i2s"; 797 reg = <0x0 0x140f0000 0x0 0x100>; 798 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 799 dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; 800 dma-names = "tx", "rx", "tx-sec"; 801 #clock-cells = <1>; 802 clocks = <&clock_peric PERIC_PCLK_TDM1>, 803 <&clock_peric PERIC_HCLK_TDM1>, 804 <&clock_peric PERIC_HCLK_TDM1>; 805 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&i2s1_bus>; 808 #sound-dai-cells = <1>; 809 status = "disabled"; 810 }; 811 812 pinctrl_pmu: pinctrl@114f0000 { 813 compatible = "tesla,fsd-pinctrl"; 814 reg = <0x0 0x114f0000 0x0 0x1000>; 815 }; 816 817 pinctrl_peric: pinctrl@141f0000 { 818 compatible = "tesla,fsd-pinctrl"; 819 reg = <0x0 0x141f0000 0x0 0x1000>; 820 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 821 }; 822 823 pinctrl_fsys0: pinctrl@15020000 { 824 compatible = "tesla,fsd-pinctrl"; 825 reg = <0x0 0x15020000 0x0 0x1000>; 826 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 827 }; 828 829 m_can0: can@14088000 { 830 compatible = "bosch,m_can"; 831 reg = <0x0 0x14088000 0x0 0x0200>, 832 <0x0 0x14080000 0x0 0x8000>; 833 reg-names = "m_can", "message_ram"; 834 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "int0", "int1"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&m_can0_bus>; 839 clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, 840 <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; 841 clock-names = "hclk", "cclk"; 842 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 843 status = "disabled"; 844 }; 845 846 m_can1: can@14098000 { 847 compatible = "bosch,m_can"; 848 reg = <0x0 0x14098000 0x0 0x0200>, 849 <0x0 0x14090000 0x0 0x8000>; 850 reg-names = "m_can", "message_ram"; 851 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "int0", "int1"; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&m_can1_bus>; 856 clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, 857 <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; 858 clock-names = "hclk", "cclk"; 859 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 860 status = "disabled"; 861 }; 862 863 m_can2: can@140a8000 { 864 compatible = "bosch,m_can"; 865 reg = <0x0 0x140a8000 0x0 0x0200>, 866 <0x0 0x140a0000 0x0 0x8000>; 867 reg-names = "m_can", "message_ram"; 868 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "int0", "int1"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&m_can2_bus>; 873 clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, 874 <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; 875 clock-names = "hclk", "cclk"; 876 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 877 status = "disabled"; 878 }; 879 880 m_can3: can@140b8000 { 881 compatible = "bosch,m_can"; 882 reg = <0x0 0x140b8000 0x0 0x0200>, 883 <0x0 0x140b0000 0x0 0x8000>; 884 reg-names = "m_can", "message_ram"; 885 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "int0", "int1"; 888 pinctrl-names = "default"; 889 pinctrl-0 = <&m_can3_bus>; 890 clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, 891 <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; 892 clock-names = "hclk", "cclk"; 893 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 894 status = "disabled"; 895 }; 896 897 spi_0: spi@14140000 { 898 compatible = "tesla,fsd-spi"; 899 reg = <0x0 0x14140000 0x0 0x100>; 900 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 901 dmas = <&pdma1 4>, <&pdma1 5>; 902 dma-names = "tx", "rx"; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&clock_peric PERIC_PCLK_SPI0>, 906 <&clock_peric PERIC_SCLK_SPI0>; 907 clock-names = "spi", "spi_busclk0"; 908 samsung,spi-src-clk = <0>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&spi0_bus>; 911 num-cs = <1>; 912 status = "disabled"; 913 }; 914 915 spi_1: spi@14150000 { 916 compatible = "tesla,fsd-spi"; 917 reg = <0x0 0x14150000 0x0 0x100>; 918 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&pdma1 6>, <&pdma1 7>; 920 dma-names = "tx", "rx"; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 clocks = <&clock_peric PERIC_PCLK_SPI1>, 924 <&clock_peric PERIC_SCLK_SPI1>; 925 clock-names = "spi", "spi_busclk0"; 926 samsung,spi-src-clk = <0>; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&spi1_bus>; 929 num-cs = <1>; 930 status = "disabled"; 931 }; 932 933 spi_2: spi@14160000 { 934 compatible = "tesla,fsd-spi"; 935 reg = <0x0 0x14160000 0x0 0x100>; 936 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 937 dmas = <&pdma1 8>, <&pdma1 9>; 938 dma-names = "tx", "rx"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 clocks = <&clock_peric PERIC_PCLK_SPI2>, 942 <&clock_peric PERIC_SCLK_SPI2>; 943 clock-names = "spi", "spi_busclk0"; 944 samsung,spi-src-clk = <0>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&spi2_bus>; 947 num-cs = <1>; 948 status = "disabled"; 949 }; 950 951 timer@10040000 { 952 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; 953 reg = <0x0 0x10040000 0x0 0x800>; 954 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; 971 clock-names = "fin_pll", "mct"; 972 }; 973 974 mfc: mfc@12880000 { 975 compatible = "tesla,fsd-mfc"; 976 reg = <0x0 0x12880000 0x0 0x10000>; 977 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 978 clock-names = "mfc"; 979 clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; 980 memory-region = <&mfc_left>; 981 }; 982 983 ethernet1: ethernet@14300000 { 984 compatible = "tesla,fsd-ethqos"; 985 reg = <0x0 0x14300000 0x0 0x10000>; 986 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-names = "macirq"; 988 clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>, 989 <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>, 990 <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>, 991 <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>, 992 <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>, 993 <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>, 994 <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>, 995 <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, 996 <&clock_peric PERIC_EQOS_PHYRXCLK>, 997 <&clock_peric PERIC_DOUT_RGMII_CLK>; 998 clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx", 999 "master2_bus", "slave2_bus", "eqos_rxclk_mux", 1000 "eqos_phyrxclk", "dout_peric_rgmii_clk"; 1001 assigned-clocks = <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, 1002 <&clock_peric PERIC_EQOS_PHYRXCLK>; 1003 assigned-clock-parents = <&clock_peric PERIC_EQOS_PHYRXCLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>, 1006 <ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>, 1007 <ð1_rx_ctrl>, <ð1_mdio>; 1008 local-mac-address = [00 00 00 00 00 00]; 1009 iommus = <&smmu_peric 0x0 0x1>; 1010 status = "disabled"; 1011 }; 1012 1013 ufs: ufs@15120000 { 1014 compatible = "tesla,fsd-ufs"; 1015 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ 1016 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ 1017 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ 1018 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ 1019 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1020 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, 1022 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; 1023 clock-names = "core_clk", "sclk_unipro_main"; 1024 freq-table-hz = <0 0>, <0 0>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1027 phys = <&ufs_phy>; 1028 phy-names = "ufs-phy"; 1029 status = "disabled"; 1030 }; 1031 1032 ufs_phy: ufs-phy@15124000 { 1033 compatible = "tesla,fsd-ufs-phy"; 1034 reg = <0x0 0x15124000 0x0 0x800>; 1035 reg-names = "phy-pma"; 1036 samsung,pmu-syscon = <&pmu_system_controller>; 1037 #phy-cells = <0>; 1038 clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; 1039 clock-names = "ref_clk"; 1040 }; 1041 1042 ethernet0: ethernet@15300000 { 1043 compatible = "tesla,fsd-ethqos"; 1044 reg = <0x0 0x15300000 0x0 0x10000>; 1045 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1046 interrupt-names = "macirq"; 1047 clocks = <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I>, 1048 <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I>, 1049 <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I>, 1050 <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>, 1051 <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>; 1052 clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx"; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <ð0_tx_clk>, <ð0_tx_data>, <ð0_tx_ctrl>, 1055 <ð0_phy_intr>, <ð0_rx_clk>, <ð0_rx_data>, 1056 <ð0_rx_ctrl>, <ð0_mdio>; 1057 local-mac-address = [00 00 00 00 00 00]; 1058 iommus = <&smmu_fsys0 0x0 0x1>; 1059 status = "disabled"; 1060 }; 1061 }; 1062}; 1063 1064#include "fsd-pinctrl.dtsi"
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