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stm32mp25-pinctrl.dtsi

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linux-6.19.14/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi DEVICETREE 
  1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
  2/*
  3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
  4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  5 */
  6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
  7
  8&pinctrl {
  9	eth1_mdio_pins_a: eth1-mdio-0 {
 10		pins1 {
 11			pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
 12			bias-disable;
 13			drive-push-pull;
 14			slew-rate = <2>;
 15		};
 16		pins2 {
 17			pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */
 18			bias-disable;
 19			drive-push-pull;
 20			slew-rate = <0>;
 21		};
 22	};
 23
 24	eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
 25		pins1 {
 26			pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
 27				 <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
 28		};
 29	};
 30
 31	eth1_rgmii_pins_a: eth1-rgmii-0 {
 32		pins1 {
 33			pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
 34				 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
 35				 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
 36				 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
 37				 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
 38			bias-disable;
 39			drive-push-pull;
 40			slew-rate = <3>;
 41			st,io-sync = "data on both edges";
 42		};
 43		pins2 {
 44			pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
 45				 <STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */
 46			bias-disable;
 47			drive-push-pull;
 48			slew-rate = <3>;
 49		};
 50		pins3 {
 51			pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
 52				 <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
 53				 <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
 54				 <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
 55				 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
 56			bias-disable;
 57			st,io-sync = "data on both edges";
 58		};
 59		pins4 {
 60			pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
 61			bias-disable;
 62		};
 63	};
 64
 65	eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
 66		pins {
 67			pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
 68				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
 69				 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
 70				 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
 71				 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
 72				 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
 73				 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
 74				 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
 75				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
 76				 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
 77				 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
 78				 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
 79				 <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
 80		};
 81	};
 82
 83	eth1_rgmii_pins_b: eth1-rgmii-1 {
 84		pins1 {
 85			pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
 86				 <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
 87				 <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
 88				 <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
 89				 <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
 90			bias-disable;
 91			drive-push-pull;
 92			slew-rate = <3>;
 93		};
 94		pins2 {
 95			pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
 96				 <STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */
 97				 <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */
 98				 <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */
 99			bias-disable;
100			drive-push-pull;
101			slew-rate = <3>;
102		};
103		pins3 {
104			pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
105				 <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
106				 <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
107				 <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
108				 <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
109			bias-disable;
110		};
111		pins4 {
112			pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
113			bias-disable;
114		};
115	};
116
117	eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {
118		pins {
119			pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
120				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
121				 <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
122				 <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
123				 <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
124				 <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
125				 <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
126				 <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */
127				 <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */
128				 <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
129				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
130				 <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
131				 <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
132				 <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
133				 <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
134		};
135	};
136
137	eth2_rgmii_pins_a: eth2-rgmii-0 {
138		pins1 {
139			pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
140				 <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
141				 <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
142				 <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
143				 <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
144			bias-disable;
145			drive-push-pull;
146			slew-rate = <3>;
147			st,io-sync = "data on both edges";
148		};
149		pins2 {
150			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
151				 <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
152				 <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */
153			bias-disable;
154			drive-push-pull;
155			slew-rate = <3>;
156		};
157		pins3 {
158			pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
159			bias-disable;
160			drive-push-pull;
161			slew-rate = <0>;
162		};
163		pins4 {
164			pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
165				 <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
166				 <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
167				 <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
168				 <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
169			bias-disable;
170			st,io-sync = "data on both edges";
171		};
172		pins5 {
173			pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
174			bias-disable;
175		};
176	};
177
178	eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
179		pins {
180			pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
181				 <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
182				 <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
183				 <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
184				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
185				 <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
186				 <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
187				 <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */
188				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
189				 <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
190				 <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
191				 <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
192				 <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
193				 <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
194				 <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
195		};
196	};
197
198	i2c2_pins_a: i2c2-0 {
199		pins {
200			pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
201				 <STM32_PINMUX('B', 4, AF9)>; /* I2C2_SDA */
202			bias-disable;
203			drive-open-drain;
204			slew-rate = <0>;
205		};
206	};
207
208	i2c2_sleep_pins_a: i2c2-sleep-0 {
209		pins {
210			pinmux = <STM32_PINMUX('B', 5, ANALOG)>, /* I2C2_SCL */
211				 <STM32_PINMUX('B', 4, ANALOG)>; /* I2C2_SDA */
212		};
213	};
214
215	ospi_port1_clk_pins_a: ospi-port1-clk-0 {
216		pins {
217			pinmux = <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */
218			bias-disable;
219			drive-push-pull;
220			slew-rate = <2>;
221		};
222	};
223
224	ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
225		pins {
226			pinmux = <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */
227		};
228	};
229
230	ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
231		pins {
232			pinmux = <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */
233			bias-pull-up;
234			drive-push-pull;
235			slew-rate = <0>;
236		};
237	};
238
239	ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
240		pins {
241			pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */
242		};
243	};
244
245	ospi_port1_io03_pins_a: ospi-port1-io03-0 {
246		pins {
247			pinmux = <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */
248				 <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */
249				 <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */
250				 <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */
251			bias-disable;
252			drive-push-pull;
253			slew-rate = <0>;
254		};
255	};
256
257	ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
258		pins {
259			pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */
260				 <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */
261				 <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */
262				 <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */
263		};
264	};
265
266	pcie_pins_a: pcie-0 {
267		pins {
268			pinmux = <STM32_PINMUX('J', 0, AF4)>;
269			bias-disable;
270		};
271	};
272
273	pcie_init_pins_a: pcie-init-0 {
274		pins {
275			pinmux = <STM32_PINMUX('J', 0, GPIO)>;
276			output-low;
277		};
278	};
279
280	pcie_sleep_pins_a: pcie-sleep-0 {
281		pins {
282			pinmux = <STM32_PINMUX('J', 0, ANALOG)>;
283		};
284	};
285
286	pwm3_pins_a: pwm3-0 {
287		pins {
288			pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */
289			bias-pull-down;
290			drive-push-pull;
291			slew-rate = <0>;
292		};
293	};
294
295	pwm3_sleep_pins_a: pwm3-sleep-0 {
296		pins {
297			pinmux = <STM32_PINMUX('B', 15, ANALOG)>; /* TIM3_CH2 */
298		};
299	};
300
301	pwm8_pins_a: pwm8-0 {
302		pins {
303			pinmux = <STM32_PINMUX('J', 5, AF8)>, /* TIM8_CH1 */
304				 <STM32_PINMUX('J', 4, AF8)>; /* TIM8_CH4 */
305			bias-pull-down;
306			drive-push-pull;
307			slew-rate = <0>;
308		};
309	};
310
311	pwm8_sleep_pins_a: pwm8-sleep-0 {
312		pins {
313			pinmux = <STM32_PINMUX('J', 5, ANALOG)>, /* TIM8_CH1 */
314				 <STM32_PINMUX('J', 4, ANALOG)>; /* TIM8_CH4 */
315		};
316	};
317
318	pwm12_pins_a: pwm12-0 {
319		pins {
320			pinmux = <STM32_PINMUX('B', 11, AF9)>; /* TIM12_CH2 */
321			bias-pull-down;
322			drive-push-pull;
323			slew-rate = <0>;
324		};
325	};
326
327	pwm12_sleep_pins_a: pwm12-sleep-0 {
328		pins {
329			pinmux = <STM32_PINMUX('B', 11, ANALOG)>; /* TIM12_CH2 */
330		};
331	};
332
333	sdmmc1_b4_pins_a: sdmmc1-b4-0 {
334		pins1 {
335			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
336				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
337				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
338				 <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */
339				 <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
340			slew-rate = <2>;
341			drive-push-pull;
342			bias-disable;
343		};
344		pins2 {
345			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
346			slew-rate = <3>;
347			drive-push-pull;
348			bias-disable;
349		};
350	};
351
352	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
353		pins1 {
354			pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
355				 <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */
356				 <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */
357				 <STM32_PINMUX('E', 1, AF10)>; /* SDMMC1_D3 */
358			slew-rate = <2>;
359			drive-push-pull;
360			bias-disable;
361		};
362		pins2 {
363			pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */
364			slew-rate = <3>;
365			drive-push-pull;
366			bias-disable;
367		};
368		pins3 {
369			pinmux = <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */
370			slew-rate = <2>;
371			drive-open-drain;
372			bias-disable;
373		};
374	};
375
376	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
377		pins {
378			pinmux = <STM32_PINMUX('E', 4, ANALOG)>, /* SDMMC1_D0 */
379				 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC1_D1 */
380				 <STM32_PINMUX('E', 0, ANALOG)>, /* SDMMC1_D2 */
381				 <STM32_PINMUX('E', 1, ANALOG)>, /* SDMMC1_D3 */
382				 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC1_CK */
383				 <STM32_PINMUX('E', 2, ANALOG)>; /* SDMMC1_CMD */
384		};
385	};
386
387	spi3_pins_a: spi3-0 {
388		pins1 {
389			pinmux = <STM32_PINMUX('B', 7, AF1)>, /* SPI3_SCK */
390				 <STM32_PINMUX('B', 8, AF1)>; /* SPI3_MOSI */
391			drive-push-pull;
392			bias-disable;
393			slew-rate = <1>;
394		};
395		pins2 {
396			pinmux = <STM32_PINMUX('B', 10, AF1)>; /* SPI3_MISO */
397			bias-disable;
398		};
399	};
400
401	spi3_sleep_pins_a: spi3-sleep-0 {
402		pins1 {
403			pinmux = <STM32_PINMUX('B', 7, ANALOG)>, /* SPI3_SCK */
404				 <STM32_PINMUX('B', 8, ANALOG)>, /* SPI3_MOSI */
405				 <STM32_PINMUX('B', 10, ANALOG)>; /* SPI3_MISO */
406		};
407	};
408
409	tim10_counter_pins_a: tim10-counter-0 {
410		pins {
411			pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */
412			bias-disable;
413		};
414	};
415
416	tim10_counter_sleep_pins_a: tim10-counter-sleep-0 {
417		pins {
418			pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */
419			bias-disable;
420		};
421	};
422
423	usart2_pins_a: usart2-0 {
424		pins1 {
425			pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
426			bias-disable;
427			drive-push-pull;
428			slew-rate = <0>;
429		};
430		pins2 {
431			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
432			bias-disable;
433		};
434	};
435
436	usart2_idle_pins_a: usart2-idle-0 {
437		pins1 {
438			pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
439		};
440		pins2 {
441			pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
442			bias-disable;
443		};
444	};
445
446	usart2_sleep_pins_a: usart2-sleep-0 {
447		pins {
448			pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
449				 <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
450		};
451	};
452
453	usart6_pins_a: usart6-0 {
454		pins1 {
455			pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
456				 <STM32_PINMUX('G', 5, AF3)>;  /* USART6_RTS */
457			bias-disable;
458			drive-push-pull;
459			slew-rate = <0>;
460		};
461		pins2 {
462			pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
463				 <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
464			bias-pull-up;
465		};
466	};
467
468	usart6_idle_pins_a: usart6-idle-0 {
469		pins1 {
470			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
471				 <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
472		};
473		pins2 {
474			pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
475			bias-disable;
476			drive-push-pull;
477			slew-rate = <0>;
478		};
479		pins3 {
480			pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
481			bias-pull-up;
482		};
483	};
484
485	usart6_sleep_pins_a: usart6-sleep-0 {
486		pins {
487			pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
488				 <STM32_PINMUX('G', 5, ANALOG)>,  /* USART6_RTS */
489				 <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
490				 <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
491		};
492	};
493};
494
495&pinctrl_z {
496	i2c8_pins_a: i2c8-0 {
497		pins {
498			pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C8_SCL */
499				 <STM32_PINMUX('Z', 3, AF8)>; /* I2C8_SDA */
500			bias-disable;
501			drive-open-drain;
502			slew-rate = <0>;
503		};
504	};
505
506	i2c8_sleep_pins_a: i2c8-sleep-0 {
507		pins {
508			pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C8_SCL */
509				 <STM32_PINMUX('Z', 3, ANALOG)>; /* I2C8_SDA */
510		};
511	};
512};
513
514&pinctrl_z {
515	spi8_pins_a: spi8-0 {
516		pins1 {
517			pinmux = <STM32_PINMUX('Z', 2, AF3)>, /* SPI8_SCK */
518				 <STM32_PINMUX('Z', 0, AF3)>; /* SPI8_MOSI */
519			drive-push-pull;
520			bias-disable;
521			slew-rate = <1>;
522		};
523		pins2 {
524			pinmux = <STM32_PINMUX('Z', 1, AF3)>; /* SPI8_MISO */
525			bias-disable;
526		};
527	};
528
529	spi8_sleep_pins_a: spi8-sleep-0 {
530		pins1 {
531			pinmux = <STM32_PINMUX('Z', 2, ANALOG)>, /* SPI8_SCK */
532				 <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI8_MOSI */
533				 <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */
534		};
535	};
536};
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