FILE
stm32mp231.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/st/stm32mp231.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 reg = <0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 power-domains = <&cpu0_pd>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clk_dsi_txbyte: clock-0 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 clk_rcbsec: clk-64000000 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <64000000>; 52 }; 53 54 firmware { 55 optee: optee { 56 compatible = "linaro,optee-tz"; 57 method = "smc"; 58 interrupt-parent = <&intc>; 59 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 60 }; 61 62 scmi { 63 compatible = "linaro,scmi-optee"; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 linaro,optee-channel-id = <0>; 67 68 scmi_clk: protocol@14 { 69 reg = <0x14>; 70 #clock-cells = <1>; 71 }; 72 73 scmi_reset: protocol@16 { 74 reg = <0x16>; 75 #reset-cells = <1>; 76 }; 77 78 scmi_voltd: protocol@17 { 79 reg = <0x17>; 80 81 scmi_regu: regulators { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 scmi_vddio1: regulator@0 { 86 reg = <VOLTD_SCMI_VDDIO1>; 87 regulator-name = "vddio1"; 88 }; 89 scmi_vddio2: regulator@1 { 90 reg = <VOLTD_SCMI_VDDIO2>; 91 regulator-name = "vddio2"; 92 }; 93 scmi_vddio3: regulator@2 { 94 reg = <VOLTD_SCMI_VDDIO3>; 95 regulator-name = "vddio3"; 96 }; 97 scmi_vddio4: regulator@3 { 98 reg = <VOLTD_SCMI_VDDIO4>; 99 regulator-name = "vddio4"; 100 }; 101 scmi_vdd33ucpd: regulator@5 { 102 reg = <VOLTD_SCMI_UCPD>; 103 regulator-name = "vdd33ucpd"; 104 }; 105 scmi_vdda18adc: regulator@7 { 106 reg = <VOLTD_SCMI_ADC>; 107 regulator-name = "vdda18adc"; 108 }; 109 }; 110 }; 111 }; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0"; 116 method = "smc"; 117 118 cpu0_pd: power-domain-cpu0 { 119 #power-domain-cells = <0>; 120 power-domains = <&cluster_pd>; 121 }; 122 123 cluster_pd: power-domain-cluster { 124 #power-domain-cells = <0>; 125 power-domains = <&ret_pd>; 126 }; 127 128 ret_pd: power-domain-retention { 129 #power-domain-cells = <0>; 130 }; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupt-parent = <&intc>; 136 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 138 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 139 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 140 always-on; 141 }; 142 143 soc@0 { 144 compatible = "simple-bus"; 145 ranges = <0x0 0x0 0x0 0x80000000>; 146 interrupt-parent = <&intc>; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 150 hpdma: dma-controller@40400000 { 151 compatible = "st,stm32mp25-dma3"; 152 reg = <0x40400000 0x1000>; 153 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 170 #dma-cells = <3>; 171 }; 172 173 hpdma2: dma-controller@40410000 { 174 compatible = "st,stm32mp25-dma3"; 175 reg = <0x40410000 0x1000>; 176 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 193 #dma-cells = <3>; 194 }; 195 196 hpdma3: dma-controller@40420000 { 197 compatible = "st,stm32mp25-dma3"; 198 reg = <0x40420000 0x1000>; 199 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 216 #dma-cells = <3>; 217 }; 218 219 rifsc: bus@42080000 { 220 compatible = "st,stm32mp25-rifsc", "simple-bus"; 221 reg = <0x42080000 0x1000>; 222 ranges; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 #access-controller-cells = <1>; 226 227 i2s2: audio-controller@400b0000 { 228 compatible = "st,stm32mp25-i2s"; 229 reg = <0x400b0000 0x400>; 230 #sound-dai-cells = <0>; 231 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 233 clock-names = "pclk", "i2sclk"; 234 resets = <&rcc SPI2_R>; 235 dmas = <&hpdma 51 0x43 0x12>, 236 <&hpdma 52 0x43 0x21>; 237 dma-names = "rx", "tx"; 238 access-controllers = <&rifsc 23>; 239 status = "disabled"; 240 }; 241 242 spi2: spi@400b0000 { 243 compatible = "st,stm32mp25-spi"; 244 reg = <0x400b0000 0x400>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&rcc CK_KER_SPI2>; 249 resets = <&rcc SPI2_R>; 250 dmas = <&hpdma 51 0x20 0x3012>, 251 <&hpdma 52 0x20 0x3021>; 252 dma-names = "rx", "tx"; 253 access-controllers = <&rifsc 23>; 254 status = "disabled"; 255 }; 256 257 i2s3: audio-controller@400c0000 { 258 compatible = "st,stm32mp25-i2s"; 259 reg = <0x400c0000 0x400>; 260 #sound-dai-cells = <0>; 261 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 263 clock-names = "pclk", "i2sclk"; 264 resets = <&rcc SPI3_R>; 265 dmas = <&hpdma 53 0x43 0x12>, 266 <&hpdma 54 0x43 0x21>; 267 dma-names = "rx", "tx"; 268 access-controllers = <&rifsc 24>; 269 status = "disabled"; 270 }; 271 272 spi3: spi@400c0000 { 273 compatible = "st,stm32mp25-spi"; 274 reg = <0x400c0000 0x400>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc CK_KER_SPI3>; 279 resets = <&rcc SPI3_R>; 280 dmas = <&hpdma 53 0x20 0x3012>, 281 <&hpdma 54 0x20 0x3021>; 282 dma-names = "rx", "tx"; 283 access-controllers = <&rifsc 24>; 284 status = "disabled"; 285 }; 286 287 spdifrx: audio-controller@400d0000 { 288 compatible = "st,stm32h7-spdifrx"; 289 reg = <0x400d0000 0x400>; 290 #sound-dai-cells = <0>; 291 clocks = <&rcc CK_KER_SPDIFRX>; 292 clock-names = "kclk"; 293 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 294 dmas = <&hpdma 71 0x43 0x212>, 295 <&hpdma 72 0x43 0x212>; 296 dma-names = "rx", "rx-ctrl"; 297 access-controllers = <&rifsc 30>; 298 status = "disabled"; 299 }; 300 301 usart2: serial@400e0000 { 302 compatible = "st,stm32h7-uart"; 303 reg = <0x400e0000 0x400>; 304 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&rcc CK_KER_USART2>; 306 dmas = <&hpdma 11 0x20 0x10012>, 307 <&hpdma 12 0x20 0x3021>; 308 dma-names = "rx", "tx"; 309 access-controllers = <&rifsc 32>; 310 status = "disabled"; 311 }; 312 313 usart3: serial@400f0000 { 314 compatible = "st,stm32h7-uart"; 315 reg = <0x400f0000 0x400>; 316 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&rcc CK_KER_USART3>; 318 dmas = <&hpdma 13 0x20 0x10012>, 319 <&hpdma 14 0x20 0x3021>; 320 dma-names = "rx", "tx"; 321 access-controllers = <&rifsc 33>; 322 status = "disabled"; 323 }; 324 325 uart4: serial@40100000 { 326 compatible = "st,stm32h7-uart"; 327 reg = <0x40100000 0x400>; 328 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&rcc CK_KER_UART4>; 330 dmas = <&hpdma 15 0x20 0x10012>, 331 <&hpdma 16 0x20 0x3021>; 332 dma-names = "rx", "tx"; 333 access-controllers = <&rifsc 34>; 334 status = "disabled"; 335 }; 336 337 uart5: serial@40110000 { 338 compatible = "st,stm32h7-uart"; 339 reg = <0x40110000 0x400>; 340 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&rcc CK_KER_UART5>; 342 dmas = <&hpdma 17 0x20 0x10012>, 343 <&hpdma 18 0x20 0x3021>; 344 dma-names = "rx", "tx"; 345 access-controllers = <&rifsc 35>; 346 status = "disabled"; 347 }; 348 349 i2c1: i2c@40120000 { 350 compatible = "st,stm32mp25-i2c"; 351 reg = <0x40120000 0x400>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 interrupt-names = "event"; 355 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&rcc CK_KER_I2C1>; 357 resets = <&rcc I2C1_R>; 358 dmas = <&hpdma 27 0x20 0x3012>, 359 <&hpdma 28 0x20 0x3021>; 360 dma-names = "rx", "tx"; 361 access-controllers = <&rifsc 41>; 362 status = "disabled"; 363 }; 364 365 i2c2: i2c@40130000 { 366 compatible = "st,stm32mp25-i2c"; 367 reg = <0x40130000 0x400>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 interrupt-names = "event"; 371 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&rcc CK_KER_I2C2>; 373 resets = <&rcc I2C2_R>; 374 dmas = <&hpdma 30 0x20 0x3012>, 375 <&hpdma 31 0x20 0x3021>; 376 dma-names = "rx", "tx"; 377 access-controllers = <&rifsc 42>; 378 status = "disabled"; 379 }; 380 381 i2c7: i2c@40180000 { 382 compatible = "st,stm32mp25-i2c"; 383 reg = <0x40180000 0x400>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 interrupt-names = "event"; 387 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&rcc CK_KER_I2C7>; 389 resets = <&rcc I2C7_R>; 390 dmas = <&hpdma 45 0x20 0x3012>, 391 <&hpdma 46 0x20 0x3021>; 392 dma-names = "rx", "tx"; 393 access-controllers = <&rifsc 47>; 394 status = "disabled"; 395 }; 396 397 usart6: serial@40220000 { 398 compatible = "st,stm32h7-uart"; 399 reg = <0x40220000 0x400>; 400 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&rcc CK_KER_USART6>; 402 dmas = <&hpdma 19 0x20 0x10012>, 403 <&hpdma 20 0x20 0x3021>; 404 dma-names = "rx", "tx"; 405 access-controllers = <&rifsc 36>; 406 status = "disabled"; 407 }; 408 409 i2s1: audio-controller@40230000 { 410 compatible = "st,stm32mp25-i2s"; 411 reg = <0x40230000 0x400>; 412 #sound-dai-cells = <0>; 413 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 415 clock-names = "pclk", "i2sclk"; 416 resets = <&rcc SPI1_R>; 417 dmas = <&hpdma 49 0x43 0x12>, 418 <&hpdma 50 0x43 0x21>; 419 dma-names = "rx", "tx"; 420 access-controllers = <&rifsc 22>; 421 status = "disabled"; 422 }; 423 424 spi1: spi@40230000 { 425 compatible = "st,stm32mp25-spi"; 426 reg = <0x40230000 0x400>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&rcc CK_KER_SPI1>; 431 resets = <&rcc SPI1_R>; 432 dmas = <&hpdma 49 0x20 0x3012>, 433 <&hpdma 50 0x20 0x3021>; 434 dma-names = "rx", "tx"; 435 access-controllers = <&rifsc 22>; 436 status = "disabled"; 437 }; 438 439 spi4: spi@40240000 { 440 compatible = "st,stm32mp25-spi"; 441 reg = <0x40240000 0x400>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&rcc CK_KER_SPI4>; 446 resets = <&rcc SPI4_R>; 447 dmas = <&hpdma 55 0x20 0x3012>, 448 <&hpdma 56 0x20 0x3021>; 449 dma-names = "rx", "tx"; 450 access-controllers = <&rifsc 25>; 451 status = "disabled"; 452 }; 453 454 spi5: spi@40280000 { 455 compatible = "st,stm32mp25-spi"; 456 reg = <0x40280000 0x400>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&rcc CK_KER_SPI5>; 461 resets = <&rcc SPI5_R>; 462 dmas = <&hpdma 57 0x20 0x3012>, 463 <&hpdma 58 0x20 0x3021>; 464 dma-names = "rx", "tx"; 465 access-controllers = <&rifsc 26>; 466 status = "disabled"; 467 }; 468 469 sai1: sai@40290000 { 470 compatible = "st,stm32mp25-sai"; 471 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 472 ranges = <0 0x40290000 0x400>; 473 #address-cells = <1>; 474 #size-cells = <1>; 475 clocks = <&rcc CK_BUS_SAI1>; 476 clock-names = "pclk"; 477 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 478 resets = <&rcc SAI1_R>; 479 access-controllers = <&rifsc 49>; 480 status = "disabled"; 481 482 sai1a: audio-controller@40290004 { 483 compatible = "st,stm32-sai-sub-a"; 484 reg = <0x4 0x20>; 485 #sound-dai-cells = <0>; 486 clocks = <&rcc CK_KER_SAI1>; 487 clock-names = "sai_ck"; 488 dmas = <&hpdma 73 0x43 0x21>; 489 status = "disabled"; 490 }; 491 492 sai1b: audio-controller@40290024 { 493 compatible = "st,stm32-sai-sub-b"; 494 reg = <0x24 0x20>; 495 #sound-dai-cells = <0>; 496 clocks = <&rcc CK_KER_SAI1>; 497 clock-names = "sai_ck"; 498 dmas = <&hpdma 74 0x43 0x12>; 499 status = "disabled"; 500 }; 501 }; 502 503 sai2: sai@402a0000 { 504 compatible = "st,stm32mp25-sai"; 505 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 506 ranges = <0 0x402a0000 0x400>; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 clocks = <&rcc CK_BUS_SAI2>; 510 clock-names = "pclk"; 511 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 512 resets = <&rcc SAI2_R>; 513 access-controllers = <&rifsc 50>; 514 status = "disabled"; 515 516 sai2a: audio-controller@402a0004 { 517 compatible = "st,stm32-sai-sub-a"; 518 reg = <0x4 0x20>; 519 #sound-dai-cells = <0>; 520 clocks = <&rcc CK_KER_SAI2>; 521 clock-names = "sai_ck"; 522 dmas = <&hpdma 75 0x43 0x21>; 523 status = "disabled"; 524 }; 525 526 sai2b: audio-controller@402a0024 { 527 compatible = "st,stm32-sai-sub-b"; 528 reg = <0x24 0x20>; 529 #sound-dai-cells = <0>; 530 clocks = <&rcc CK_KER_SAI2>; 531 clock-names = "sai_ck"; 532 dmas = <&hpdma 76 0x43 0x12>; 533 status = "disabled"; 534 }; 535 }; 536 537 sai3: sai@402b0000 { 538 compatible = "st,stm32mp25-sai"; 539 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 540 ranges = <0 0x402b0000 0x400>; 541 #address-cells = <1>; 542 #size-cells = <1>; 543 clocks = <&rcc CK_BUS_SAI3>; 544 clock-names = "pclk"; 545 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 546 resets = <&rcc SAI3_R>; 547 access-controllers = <&rifsc 51>; 548 status = "disabled"; 549 550 sai3a: audio-controller@402b0004 { 551 compatible = "st,stm32-sai-sub-a"; 552 reg = <0x4 0x20>; 553 #sound-dai-cells = <0>; 554 clocks = <&rcc CK_KER_SAI3>; 555 clock-names = "sai_ck"; 556 dmas = <&hpdma 77 0x43 0x21>; 557 status = "disabled"; 558 }; 559 560 sai3b: audio-controller@502b0024 { 561 compatible = "st,stm32-sai-sub-b"; 562 reg = <0x24 0x20>; 563 #sound-dai-cells = <0>; 564 clocks = <&rcc CK_KER_SAI3>; 565 clock-names = "sai_ck"; 566 dmas = <&hpdma 78 0x43 0x12>; 567 status = "disabled"; 568 }; 569 }; 570 571 usart1: serial@40330000 { 572 compatible = "st,stm32h7-uart"; 573 reg = <0x40330000 0x400>; 574 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&rcc CK_KER_USART1>; 576 dmas = <&hpdma 9 0x20 0x10012>, 577 <&hpdma 10 0x20 0x3021>; 578 dma-names = "rx", "tx"; 579 access-controllers = <&rifsc 31>; 580 status = "disabled"; 581 }; 582 583 sai4: sai@40340000 { 584 compatible = "st,stm32mp25-sai"; 585 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 586 ranges = <0 0x40340000 0x400>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 clocks = <&rcc CK_BUS_SAI4>; 590 clock-names = "pclk"; 591 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 592 resets = <&rcc SAI4_R>; 593 access-controllers = <&rifsc 52>; 594 status = "disabled"; 595 596 sai4a: audio-controller@40340004 { 597 compatible = "st,stm32-sai-sub-a"; 598 reg = <0x4 0x20>; 599 #sound-dai-cells = <0>; 600 clocks = <&rcc CK_KER_SAI4>; 601 clock-names = "sai_ck"; 602 dmas = <&hpdma 79 0x63 0x21>; 603 status = "disabled"; 604 }; 605 606 sai4b: audio-controller@40340024 { 607 compatible = "st,stm32-sai-sub-b"; 608 reg = <0x24 0x20>; 609 #sound-dai-cells = <0>; 610 clocks = <&rcc CK_KER_SAI4>; 611 clock-names = "sai_ck"; 612 dmas = <&hpdma 80 0x43 0x12>; 613 status = "disabled"; 614 }; 615 }; 616 617 uart7: serial@40370000 { 618 compatible = "st,stm32h7-uart"; 619 reg = <0x40370000 0x400>; 620 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&rcc CK_KER_UART7>; 622 dmas = <&hpdma 21 0x20 0x10012>, 623 <&hpdma 22 0x20 0x3021>; 624 dma-names = "rx", "tx"; 625 access-controllers = <&rifsc 37>; 626 status = "disabled"; 627 }; 628 629 rng: rng@42020000 { 630 compatible = "st,stm32mp25-rng"; 631 reg = <0x42020000 0x400>; 632 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 633 clock-names = "core", "bus"; 634 resets = <&rcc RNG_R>; 635 access-controllers = <&rifsc 92>; 636 status = "disabled"; 637 }; 638 639 spi8: spi@46020000 { 640 compatible = "st,stm32mp25-spi"; 641 reg = <0x46020000 0x400>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&rcc CK_KER_SPI8>; 646 resets = <&rcc SPI8_R>; 647 dmas = <&hpdma 171 0x20 0x3012>, 648 <&hpdma 172 0x20 0x3021>; 649 dma-names = "rx", "tx"; 650 access-controllers = <&rifsc 29>; 651 status = "disabled"; 652 }; 653 654 i2c8: i2c@46040000 { 655 compatible = "st,stm32mp25-i2c"; 656 reg = <0x46040000 0x400>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 interrupt-names = "event"; 660 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&rcc CK_KER_I2C8>; 662 resets = <&rcc I2C8_R>; 663 dmas = <&hpdma 168 0x20 0x3012>, 664 <&hpdma 169 0x20 0x3021>; 665 dma-names = "rx", "tx"; 666 access-controllers = <&rifsc 48>; 667 status = "disabled"; 668 }; 669 670 csi: csi@48020000 { 671 compatible = "st,stm32mp25-csi"; 672 reg = <0x48020000 0x2000>; 673 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 674 resets = <&rcc CSI_R>; 675 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 676 <&rcc CK_KER_CSIPHY>; 677 clock-names = "pclk", "txesc", "csi2phy"; 678 access-controllers = <&rifsc 86>; 679 status = "disabled"; 680 }; 681 682 dcmipp: dcmipp@48030000 { 683 compatible = "st,stm32mp25-dcmipp"; 684 reg = <0x48030000 0x1000>; 685 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 686 resets = <&rcc DCMIPP_R>; 687 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 688 clock-names = "kclk", "mclk"; 689 access-controllers = <&rifsc 87>; 690 status = "disabled"; 691 }; 692 693 sdmmc1: mmc@48220000 { 694 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 695 reg = <0x48220000 0x400>, <0x44230400 0x8>; 696 arm,primecell-periphid = <0x00353180>; 697 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&rcc CK_KER_SDMMC1 >; 699 clock-names = "apb_pclk"; 700 resets = <&rcc SDMMC1_R>; 701 cap-sd-highspeed; 702 cap-mmc-highspeed; 703 max-frequency = <120000000>; 704 access-controllers = <&rifsc 76>; 705 status = "disabled"; 706 }; 707 708 ethernet1: ethernet@482c0000 { 709 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 710 reg = <0x482c0000 0x4000>; 711 reg-names = "stmmaceth"; 712 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 713 interrupt-names = "macirq"; 714 clock-names = "stmmaceth", 715 "mac-clk-tx", 716 "mac-clk-rx", 717 "ptp_ref", 718 "ethstp", 719 "eth-ck"; 720 clocks = <&rcc CK_ETH1_MAC>, 721 <&rcc CK_ETH1_TX>, 722 <&rcc CK_ETH1_RX>, 723 <&rcc CK_KER_ETH1PTP>, 724 <&rcc CK_ETH1_STP>, 725 <&rcc CK_KER_ETH1>; 726 snps,axi-config = <&stmmac_axi_config_1>; 727 snps,mixed-burst; 728 snps,mtl-rx-config = <&mtl_rx_setup_1>; 729 snps,mtl-tx-config = <&mtl_tx_setup_1>; 730 snps,pbl = <2>; 731 snps,tso; 732 st,syscon = <&syscfg 0x3000>; 733 access-controllers = <&rifsc 60>; 734 status = "disabled"; 735 736 mtl_rx_setup_1: rx-queues-config { 737 snps,rx-queues-to-use = <2>; 738 queue0 {}; 739 queue1 {}; 740 }; 741 742 mtl_tx_setup_1: tx-queues-config { 743 snps,tx-queues-to-use = <4>; 744 queue0 {}; 745 queue1 {}; 746 queue2 {}; 747 queue3 {}; 748 }; 749 750 stmmac_axi_config_1: stmmac-axi-config { 751 snps,blen = <0 0 0 0 16 8 4>; 752 snps,rd_osr_lmt = <0x7>; 753 snps,wr_osr_lmt = <0x7>; 754 }; 755 }; 756 }; 757 758 bsec: efuse@44000000 { 759 compatible = "st,stm32mp25-bsec"; 760 reg = <0x44000000 0x1000>; 761 #address-cells = <1>; 762 #size-cells = <1>; 763 764 part_number_otp@24 { 765 reg = <0x24 0x4>; 766 }; 767 768 package_otp@1e8 { 769 reg = <0x1e8 0x1>; 770 bits = <0 3>; 771 }; 772 }; 773 774 rcc: clock-controller@44200000 { 775 compatible = "st,stm32mp25-rcc"; 776 reg = <0x44200000 0x10000>; 777 #clock-cells = <1>; 778 #reset-cells = <1>; 779 clocks = <&scmi_clk CK_SCMI_HSE>, 780 <&scmi_clk CK_SCMI_HSI>, 781 <&scmi_clk CK_SCMI_MSI>, 782 <&scmi_clk CK_SCMI_LSE>, 783 <&scmi_clk CK_SCMI_LSI>, 784 <&scmi_clk CK_SCMI_HSE_DIV2>, 785 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 786 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 787 <&scmi_clk CK_SCMI_ICN_SDMMC>, 788 <&scmi_clk CK_SCMI_ICN_DDR>, 789 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 790 <&scmi_clk CK_SCMI_ICN_HSL>, 791 <&scmi_clk CK_SCMI_ICN_NIC>, 792 <&scmi_clk CK_SCMI_ICN_VID>, 793 <&scmi_clk CK_SCMI_FLEXGEN_07>, 794 <&scmi_clk CK_SCMI_FLEXGEN_08>, 795 <&scmi_clk CK_SCMI_FLEXGEN_09>, 796 <&scmi_clk CK_SCMI_FLEXGEN_10>, 797 <&scmi_clk CK_SCMI_FLEXGEN_11>, 798 <&scmi_clk CK_SCMI_FLEXGEN_12>, 799 <&scmi_clk CK_SCMI_FLEXGEN_13>, 800 <&scmi_clk CK_SCMI_FLEXGEN_14>, 801 <&scmi_clk CK_SCMI_FLEXGEN_15>, 802 <&scmi_clk CK_SCMI_FLEXGEN_16>, 803 <&scmi_clk CK_SCMI_FLEXGEN_17>, 804 <&scmi_clk CK_SCMI_FLEXGEN_18>, 805 <&scmi_clk CK_SCMI_FLEXGEN_19>, 806 <&scmi_clk CK_SCMI_FLEXGEN_20>, 807 <&scmi_clk CK_SCMI_FLEXGEN_21>, 808 <&scmi_clk CK_SCMI_FLEXGEN_22>, 809 <&scmi_clk CK_SCMI_FLEXGEN_23>, 810 <&scmi_clk CK_SCMI_FLEXGEN_24>, 811 <&scmi_clk CK_SCMI_FLEXGEN_25>, 812 <&scmi_clk CK_SCMI_FLEXGEN_26>, 813 <&scmi_clk CK_SCMI_FLEXGEN_27>, 814 <&scmi_clk CK_SCMI_FLEXGEN_28>, 815 <&scmi_clk CK_SCMI_FLEXGEN_29>, 816 <&scmi_clk CK_SCMI_FLEXGEN_30>, 817 <&scmi_clk CK_SCMI_FLEXGEN_31>, 818 <&scmi_clk CK_SCMI_FLEXGEN_32>, 819 <&scmi_clk CK_SCMI_FLEXGEN_33>, 820 <&scmi_clk CK_SCMI_FLEXGEN_34>, 821 <&scmi_clk CK_SCMI_FLEXGEN_35>, 822 <&scmi_clk CK_SCMI_FLEXGEN_36>, 823 <&scmi_clk CK_SCMI_FLEXGEN_37>, 824 <&scmi_clk CK_SCMI_FLEXGEN_38>, 825 <&scmi_clk CK_SCMI_FLEXGEN_39>, 826 <&scmi_clk CK_SCMI_FLEXGEN_40>, 827 <&scmi_clk CK_SCMI_FLEXGEN_41>, 828 <&scmi_clk CK_SCMI_FLEXGEN_42>, 829 <&scmi_clk CK_SCMI_FLEXGEN_43>, 830 <&scmi_clk CK_SCMI_FLEXGEN_44>, 831 <&scmi_clk CK_SCMI_FLEXGEN_45>, 832 <&scmi_clk CK_SCMI_FLEXGEN_46>, 833 <&scmi_clk CK_SCMI_FLEXGEN_47>, 834 <&scmi_clk CK_SCMI_FLEXGEN_48>, 835 <&scmi_clk CK_SCMI_FLEXGEN_49>, 836 <&scmi_clk CK_SCMI_FLEXGEN_50>, 837 <&scmi_clk CK_SCMI_FLEXGEN_51>, 838 <&scmi_clk CK_SCMI_FLEXGEN_52>, 839 <&scmi_clk CK_SCMI_FLEXGEN_53>, 840 <&scmi_clk CK_SCMI_FLEXGEN_54>, 841 <&scmi_clk CK_SCMI_FLEXGEN_55>, 842 <&scmi_clk CK_SCMI_FLEXGEN_56>, 843 <&scmi_clk CK_SCMI_FLEXGEN_57>, 844 <&scmi_clk CK_SCMI_FLEXGEN_58>, 845 <&scmi_clk CK_SCMI_FLEXGEN_59>, 846 <&scmi_clk CK_SCMI_FLEXGEN_60>, 847 <&scmi_clk CK_SCMI_FLEXGEN_61>, 848 <&scmi_clk CK_SCMI_FLEXGEN_62>, 849 <&scmi_clk CK_SCMI_FLEXGEN_63>, 850 <&scmi_clk CK_SCMI_ICN_APB1>, 851 <&scmi_clk CK_SCMI_ICN_APB2>, 852 <&scmi_clk CK_SCMI_ICN_APB3>, 853 <&scmi_clk CK_SCMI_ICN_APB4>, 854 <&scmi_clk CK_SCMI_ICN_APBDBG>, 855 <&scmi_clk CK_SCMI_TIMG1>, 856 <&scmi_clk CK_SCMI_TIMG2>, 857 <&scmi_clk CK_SCMI_PLL3>, 858 <&clk_dsi_txbyte>; 859 access-controllers = <&rifsc 156>; 860 }; 861 862 exti1: interrupt-controller@44220000 { 863 compatible = "st,stm32mp1-exti", "syscon"; 864 reg = <0x44220000 0x400>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 interrupts-extended = 868 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 869 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 870 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 871 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 872 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 873 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 874 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 875 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 876 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 877 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 878 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 879 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 880 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 881 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 882 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 883 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 884 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 885 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 886 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 887 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 888 <0>, /* EXTI_20 */ 889 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 890 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 891 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 892 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 893 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 894 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 895 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 896 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 897 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 898 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 899 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 900 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 901 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 902 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 903 <0>, 904 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 905 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 906 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 907 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 908 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 909 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 910 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 911 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 912 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 913 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 914 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 915 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 916 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 917 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 918 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 919 <0>, 920 <0>, 921 <0>, 922 <0>, 923 <0>, 924 <0>, 925 <0>, 926 <0>, 927 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 928 <0>, /* EXTI_60 */ 929 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 930 <0>, 931 <0>, 932 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 933 <0>, 934 <0>, 935 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 936 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 937 <0>, 938 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 939 <0>, 940 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 941 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 942 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 943 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 944 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 945 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 946 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 947 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 948 <0>, /* EXTI_80 */ 949 <0>, 950 <0>, 951 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 952 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 953 }; 954 955 syscfg: syscon@44230000 { 956 compatible = "st,stm32mp23-syscfg", "syscon"; 957 reg = <0x44230000 0x10000>; 958 }; 959 960 pinctrl: pinctrl@44240000 { 961 compatible = "st,stm32mp257-pinctrl"; 962 ranges = <0 0x44240000 0xa0400>; 963 #address-cells = <1>; 964 #size-cells = <1>; 965 interrupt-parent = <&exti1>; 966 st,syscfg = <&exti1 0x60 0xff>; 967 pins-are-numbered; 968 969 gpioa: gpio@44240000 { 970 reg = <0x0 0x400>; 971 gpio-controller; 972 #gpio-cells = <2>; 973 interrupt-controller; 974 #interrupt-cells = <2>; 975 clocks = <&scmi_clk CK_SCMI_GPIOA>; 976 st,bank-name = "GPIOA"; 977 status = "disabled"; 978 }; 979 980 gpiob: gpio@44250000 { 981 reg = <0x10000 0x400>; 982 gpio-controller; 983 #gpio-cells = <2>; 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 clocks = <&scmi_clk CK_SCMI_GPIOB>; 987 st,bank-name = "GPIOB"; 988 status = "disabled"; 989 }; 990 991 gpioc: gpio@44260000 { 992 reg = <0x20000 0x400>; 993 gpio-controller; 994 #gpio-cells = <2>; 995 interrupt-controller; 996 #interrupt-cells = <2>; 997 clocks = <&scmi_clk CK_SCMI_GPIOC>; 998 st,bank-name = "GPIOC"; 999 status = "disabled"; 1000 }; 1001 1002 gpiod: gpio@44270000 { 1003 reg = <0x30000 0x400>; 1004 gpio-controller; 1005 #gpio-cells = <2>; 1006 interrupt-controller; 1007 #interrupt-cells = <2>; 1008 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1009 st,bank-name = "GPIOD"; 1010 status = "disabled"; 1011 }; 1012 1013 gpioe: gpio@44280000 { 1014 reg = <0x40000 0x400>; 1015 gpio-controller; 1016 #gpio-cells = <2>; 1017 interrupt-controller; 1018 #interrupt-cells = <2>; 1019 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1020 st,bank-name = "GPIOE"; 1021 status = "disabled"; 1022 }; 1023 1024 gpiof: gpio@44290000 { 1025 reg = <0x50000 0x400>; 1026 gpio-controller; 1027 #gpio-cells = <2>; 1028 interrupt-controller; 1029 #interrupt-cells = <2>; 1030 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1031 st,bank-name = "GPIOF"; 1032 status = "disabled"; 1033 }; 1034 1035 gpiog: gpio@442a0000 { 1036 reg = <0x60000 0x400>; 1037 gpio-controller; 1038 #gpio-cells = <2>; 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1042 st,bank-name = "GPIOG"; 1043 status = "disabled"; 1044 }; 1045 1046 gpioh: gpio@442b0000 { 1047 reg = <0x70000 0x400>; 1048 gpio-controller; 1049 #gpio-cells = <2>; 1050 interrupt-controller; 1051 #interrupt-cells = <2>; 1052 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1053 st,bank-name = "GPIOH"; 1054 status = "disabled"; 1055 }; 1056 1057 gpioi: gpio@442c0000 { 1058 reg = <0x80000 0x400>; 1059 gpio-controller; 1060 #gpio-cells = <2>; 1061 interrupt-controller; 1062 #interrupt-cells = <2>; 1063 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1064 st,bank-name = "GPIOI"; 1065 status = "disabled"; 1066 }; 1067 }; 1068 1069 rtc: rtc@46000000 { 1070 compatible = "st,stm32mp25-rtc"; 1071 reg = <0x46000000 0x400>; 1072 clocks = <&scmi_clk CK_SCMI_RTC>, 1073 <&scmi_clk CK_SCMI_RTCCK>; 1074 clock-names = "pclk", "rtc_ck"; 1075 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1076 status = "disabled"; 1077 }; 1078 1079 pinctrl_z: pinctrl@46200000 { 1080 compatible = "st,stm32mp257-z-pinctrl"; 1081 ranges = <0 0x46200000 0x400>; 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 interrupt-parent = <&exti1>; 1085 st,syscfg = <&exti1 0x60 0xff>; 1086 pins-are-numbered; 1087 1088 gpioz: gpio@46200000 { 1089 reg = <0 0x400>; 1090 gpio-controller; 1091 #gpio-cells = <2>; 1092 interrupt-controller; 1093 #interrupt-cells = <2>; 1094 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1095 st,bank-name = "GPIOZ"; 1096 st,bank-ioport = <11>; 1097 status = "disabled"; 1098 }; 1099 1100 }; 1101 1102 exti2: interrupt-controller@46230000 { 1103 compatible = "st,stm32mp1-exti", "syscon"; 1104 reg = <0x46230000 0x400>; 1105 interrupt-controller; 1106 #interrupt-cells = <2>; 1107 interrupts-extended = 1108 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1109 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1110 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1111 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1112 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1113 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1114 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1115 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1116 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1117 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1118 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1119 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1120 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1121 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1122 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1123 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1124 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1125 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1126 <0>, 1127 <0>, 1128 <0>, /* EXTI_20 */ 1129 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1130 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1131 <0>, 1132 <0>, 1133 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1134 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1135 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1136 <0>, 1137 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1138 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1139 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1140 <0>, 1141 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1142 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1143 <0>, 1144 <0>, 1145 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1146 <0>, 1147 <0>, 1148 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1149 <0>, 1150 <0>, 1151 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1152 <0>, 1153 <0>, 1154 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1155 <0>, 1156 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1157 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1158 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1159 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1160 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1161 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1162 <0>, 1163 <0>, 1164 <0>, 1165 <0>, 1166 <0>, 1167 <0>, 1168 <0>, /* EXTI_60 */ 1169 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1170 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1171 <0>, 1172 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1173 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1174 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1175 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1176 <0>, 1177 <0>, 1178 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1179 }; 1180 1181 intc: interrupt-controller@4ac10000 { 1182 compatible = "arm,gic-400"; 1183 reg = <0x4ac10000 0x1000>, 1184 <0x4ac20000 0x20000>, 1185 <0x4ac40000 0x20000>, 1186 <0x4ac60000 0x20000>; 1187 #interrupt-cells = <3>; 1188 interrupt-controller; 1189 }; 1190 }; 1191};
~/
Read-only file preview.