rk3588-tiger.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
  4 */
  5
  6#include <dt-bindings/gpio/gpio.h>
  7#include <dt-bindings/leds/common.h>
  8#include <dt-bindings/pinctrl/rockchip.h>
  9#include "rk8xx.h"
 10#include "rk3588.dtsi"
 11
 12/ {
 13	compatible = "tsd,rk3588-tiger", "rockchip,rk3588";
 14
 15	aliases {
 16		i2c10 = &i2c10;
 17		mmc0 = &sdhci;
 18		rtc0 = &rtc_twi;
 19	};
 20
 21	emmc_pwrseq: emmc-pwrseq {
 22		compatible = "mmc-pwrseq-emmc";
 23		pinctrl-0 = <&emmc_reset>;
 24		pinctrl-names = "default";
 25		reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
 26	};
 27
 28	extcon_usb3: extcon-usb3 {
 29		compatible = "linux,extcon-usb-gpio";
 30		id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
 31		pinctrl-names = "default";
 32		pinctrl-0 = <&usb3_id>;
 33		status = "disabled";
 34	};
 35
 36	leds {
 37		compatible = "gpio-leds";
 38		pinctrl-names = "default";
 39		pinctrl-0 = <&module_led_pin>;
 40
 41		/* Named LED1 on the board */
 42		led-1 {
 43			gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
 44			function = LED_FUNCTION_HEARTBEAT;
 45			linux,default-trigger = "heartbeat";
 46			color = <LED_COLOR_ID_AMBER>;
 47		};
 48	};
 49
 50	/*
 51	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
 52	 * clock generator.
 53	 * The clock output is gated via the OE pin on the clock generator.
 54	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
 55	 */
 56	pcie_refclk_gen: pcie-refclk-gen-clock {
 57		compatible = "fixed-clock";
 58		#clock-cells = <0>;
 59		clock-frequency = <100000000>;
 60	};
 61
 62	pcie_refclk: pcie-refclk-clock {
 63		compatible = "gpio-gate-clock";
 64		clocks = <&pcie_refclk_gen>;
 65		#clock-cells = <0>;
 66		enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */
 67	};
 68
 69	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
 70		compatible = "regulator-fixed";
 71		regulator-name = "vcc_1v1_nldo_s3";
 72		regulator-always-on;
 73		regulator-boot-on;
 74		regulator-min-microvolt = <1100000>;
 75		regulator-max-microvolt = <1100000>;
 76		vin-supply = <&vcc5v0_sys>;
 77	};
 78
 79	vcc_1v2_s3: regulator-vcc-1v2-s3 {
 80		compatible = "regulator-fixed";
 81		regulator-name = "vcc_1v2_s3";
 82		regulator-always-on;
 83		regulator-boot-on;
 84		regulator-min-microvolt = <1200000>;
 85		regulator-max-microvolt = <1200000>;
 86		vin-supply = <&vcc5v0_sys>;
 87	};
 88
 89	vcc5v0_sys: regulator-vcc5v0-sys {
 90		compatible = "regulator-fixed";
 91		regulator-name = "vcc5v0_sys";
 92		regulator-always-on;
 93		regulator-boot-on;
 94		regulator-min-microvolt = <5000000>;
 95		regulator-max-microvolt = <5000000>;
 96		vin-supply = <&vcc5v0_baseboard>;
 97	};
 98};
 99
100&cpu_b0 {
101	cpu-supply = <&vdd_cpu_big0_s0>;
102};
103
104&cpu_b1 {
105	cpu-supply = <&vdd_cpu_big0_s0>;
106};
107
108&cpu_b2 {
109	cpu-supply = <&vdd_cpu_big1_s0>;
110};
111
112&cpu_b3 {
113	cpu-supply = <&vdd_cpu_big1_s0>;
114};
115
116&cpu_l0 {
117	cpu-supply = <&vdd_cpu_lit_s0>;
118};
119
120&cpu_l1 {
121	cpu-supply = <&vdd_cpu_lit_s0>;
122};
123
124&cpu_l2 {
125	cpu-supply = <&vdd_cpu_lit_s0>;
126};
127
128&cpu_l3 {
129	cpu-supply = <&vdd_cpu_lit_s0>;
130};
131
132&gmac0 {
133	clock_in_out = "output";
134	phy-handle = <&rgmii_phy>;
135	phy-mode = "rgmii";
136	phy-supply = <&vcc_1v2_s3>;
137	pinctrl-names = "default";
138	pinctrl-0 = <&gmac0_miim
139		     &gmac0_rx_bus2
140		     &gmac0_tx_bus2
141		     &gmac0_rgmii_clk
142		     &gmac0_rgmii_bus
143		     &eth0_pins
144		     &eth_reset>;
145	tx_delay = <0x10>;
146	rx_delay = <0x10>;
147	snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
148	snps,reset-active-low;
149	snps,reset-delays-us = <0 10000 100000>;
150};
151
152&gpu {
153	mali-supply = <&vdd_gpu_s0>;
154	status = "okay";
155};
156
157&hdmi0 {
158	pinctrl-names = "default";
159	pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl
160		     &hdmim1_tx0_sda>;
161};
162
163&i2c1 {
164	pinctrl-0 = <&i2c1m0_xfer>;
165};
166
167&i2c1m0_xfer {
168	rockchip,pins =
169		/* i2c1_scl_m0 */
170		<0 RK_PB5 9 &pcfg_pull_none_drv_level_0>,
171		/* i2c1_sda_m0 */
172		<0 RK_PB6 9 &pcfg_pull_none_drv_level_0>;
173};
174
175&i2c2 {
176	pinctrl-0 = <&i2c2m3_xfer>;
177};
178
179&i2c2m3_xfer {
180	rockchip,pins =
181		/* i2c2_scl_m3 */
182		<1 RK_PC5 9 &pcfg_pull_none_drv_level_0>,
183		/* i2c2_sda_m3 */
184		<1 RK_PC4 9 &pcfg_pull_none_drv_level_0>;
185};
186
187&i2c3 {
188	pinctrl-0 = <&i2c3m0_xfer>;
189};
190
191&i2c4 {
192	pinctrl-0 = <&i2c4m4_xfer>;
193	status = "okay";
194
195	vdd_npu_s0: regulator@42 {
196		compatible = "rockchip,rk8602";
197		reg = <0x42>;
198		fcs,suspend-voltage-selector = <1>;
199		regulator-name = "vdd_npu_s0";
200		regulator-always-on;
201		regulator-boot-on;
202		regulator-min-microvolt = <550000>;
203		regulator-max-microvolt = <950000>;
204		regulator-ramp-delay = <2300>;
205		vin-supply = <&vcc5v0_sys>;
206
207		regulator-state-mem {
208			regulator-off-in-suspend;
209		};
210	};
211};
212
213&i2c5 {
214	pinctrl-0 = <&i2c5m1_xfer>;
215};
216
217&i2c5m1_xfer {
218	rockchip,pins =
219		/* i2c5_scl_m1 */
220		<4 RK_PB6 9 &pcfg_pull_none_drv_level_0>,
221		/* i2c5_sda_m1 */
222		<4 RK_PB7 9 &pcfg_pull_none_drv_level_0>;
223};
224
225&i2c6 {
226	/*
227	 * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus,
228	 * but SOC can handle only up to (400kHz).
229	 */
230	clock-frequency = <400000>;
231	status = "okay";
232
233	fan@18 {
234		compatible = "tsd,mule", "ti,amc6821";
235		reg = <0x18>;
236
237		i2c-mux {
238			compatible = "tsd,mule-i2c-mux";
239			#address-cells = <1>;
240			#size-cells = <0>;
241
242			i2c10: i2c@0 {
243				reg = <0x0>;
244				#address-cells = <1>;
245				#size-cells = <0>;
246
247				rtc_twi: rtc@6f {
248					compatible = "isil,isl1208";
249					reg = <0x6f>;
250				};
251			};
252		};
253	};
254};
255
256&i2c6m0_xfer {
257	rockchip,pins =
258		/* i2c6_scl_m0 */
259		<0 RK_PD0 9 &pcfg_pull_none_drv_level_0>,
260		/* i2c6_sda_m0 */
261		<0 RK_PC7 9 &pcfg_pull_none_drv_level_0>;
262};
263
264&i2c7 {
265	status = "okay";
266
267	vdd_cpu_big0_s0: regulator@42 {
268		compatible = "rockchip,rk8602";
269		reg = <0x42>;
270		fcs,suspend-voltage-selector = <1>;
271		regulator-name = "vdd_cpu_big0_s0";
272		regulator-always-on;
273		regulator-boot-on;
274		regulator-min-microvolt = <550000>;
275		regulator-max-microvolt = <1050000>;
276		regulator-ramp-delay = <2300>;
277		vin-supply = <&vcc5v0_sys>;
278
279		regulator-state-mem {
280			regulator-off-in-suspend;
281		};
282	};
283
284	vdd_cpu_big1_s0: regulator@43 {
285		compatible = "rockchip,rk8603", "rockchip,rk8602";
286		reg = <0x43>;
287		fcs,suspend-voltage-selector = <1>;
288		regulator-name = "vdd_cpu_big1_s0";
289		regulator-always-on;
290		regulator-boot-on;
291		regulator-min-microvolt = <550000>;
292		regulator-max-microvolt = <1050000>;
293		regulator-ramp-delay = <2300>;
294		vin-supply = <&vcc5v0_sys>;
295
296		regulator-state-mem {
297			regulator-off-in-suspend;
298		};
299	};
300};
301
302&i2c7m0_xfer {
303	rockchip,pins =
304		/* i2c7_scl_m0 */
305		<1 RK_PD0 9 &pcfg_pull_none_drv_level_0>,
306		/* i2c7_sda_m0 */
307		<1 RK_PD1 9 &pcfg_pull_none_drv_level_0>;
308};
309
310&i2c8 {
311	pinctrl-0 = <&i2c8m2_xfer>;
312};
313
314&mdio0 {
315	rgmii_phy: ethernet-phy@6 {
316		/* KSZ9031 or KSZ9131 */
317		compatible = "ethernet-phy-ieee802.3-c22";
318		reg = <0x6>;
319		clocks = <&cru REFCLKO25M_ETH0_OUT>;
320	};
321};
322
323&pcie3x4 {
324	/*
325	 * The board has a gpio-controlled "pcie_refclk" generator,
326	 * so add it to the list of clocks.
327	 */
328	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
329		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
330		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
331		 <&pcie_refclk>;
332	clock-names = "aclk_mst", "aclk_slv",
333		      "aclk_dbi", "pclk",
334		      "aux", "pipe",
335		      "ref";
336	reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
337};
338
339&pd_gpu {
340	domain-supply = <&vdd_gpu_s0>;
341};
342
343&pinctrl {
344	emmc {
345		emmc_reset: emmc-reset {
346			rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
347		};
348	};
349
350	ethernet {
351		eth_reset: eth-reset {
352			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
353		};
354	};
355
356	leds {
357		module_led_pin: module-led-pin {
358			rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
359		};
360	};
361
362	usb3 {
363		usb3_id: usb3-id {
364			rockchip,pins =
365			  <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
366		};
367	};
368};
369
370&pwm0 {
371	pinctrl-0 = <&pwm0m1_pins>;
372	pinctrl-names = "default";
373};
374
375&saradc {
376	vref-supply = <&vcc_1v8_s0>;
377	status = "okay";
378};
379
380&sdhci {
381	bus-width = <8>;
382	cap-mmc-highspeed;
383	mmc-ddr-1_8v;
384	mmc-hs200-1_8v;
385	mmc-pwrseq = <&emmc_pwrseq>;
386	no-sdio;
387	no-sd;
388	non-removable;
389	pinctrl-names = "default";
390	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
391	vmmc-supply = <&vcc_3v3_s3>;
392	vqmmc-supply = <&vcc_1v8_s3>;
393	status = "okay";
394};
395
396&sdmmc {
397	bus-width = <4>;
398	cap-sd-highspeed;
399	max-frequency = <150000000>;
400	vqmmc-supply = <&vccio_sd_s0>;
401};
402
403&spi0 {
404	pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>;
405};
406
407&spi2 {
408	assigned-clocks = <&cru CLK_SPI2>;
409	assigned-clock-rates = <200000000>;
410	num-cs = <1>;
411	pinctrl-names = "default";
412	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
413	status = "okay";
414
415	pmic@0 {
416		compatible = "rockchip,rk806";
417		reg = <0x0>;
418		interrupt-parent = <&gpio0>;
419		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
420		gpio-controller;
421		#gpio-cells = <2>;
422		pinctrl-names = "default";
423		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
424			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
425		spi-max-frequency = <1000000>;
426		system-power-controller;
427		vcc1-supply = <&vcc5v0_sys>;
428		vcc2-supply = <&vcc5v0_sys>;
429		vcc3-supply = <&vcc5v0_sys>;
430		vcc4-supply = <&vcc5v0_sys>;
431		vcc5-supply = <&vcc5v0_sys>;
432		vcc6-supply = <&vcc5v0_sys>;
433		vcc7-supply = <&vcc5v0_sys>;
434		vcc8-supply = <&vcc5v0_sys>;
435		vcc9-supply = <&vcc5v0_sys>;
436		vcc10-supply = <&vcc5v0_sys>;
437		vcc11-supply = <&vcc_2v0_pldo_s3>;
438		vcc12-supply = <&vcc5v0_sys>;
439		vcc13-supply = <&vcc_1v1_nldo_s3>;
440		vcc14-supply = <&vcc_1v1_nldo_s3>;
441		vcca-supply = <&vcc5v0_sys>;
442		rockchip,reset-mode = <RK806_RESTART>;
443
444		rk806_dvs1_null: dvs1-null-pins {
445			pins = "gpio_pwrctrl1";
446			function = "pin_fun0";
447		};
448
449		rk806_dvs2_null: dvs2-null-pins {
450			pins = "gpio_pwrctrl2";
451			function = "pin_fun0";
452		};
453
454		rk806_dvs3_null: dvs3-null-pins {
455			pins = "gpio_pwrctrl3";
456			function = "pin_fun0";
457		};
458
459		regulators {
460			vdd_gpu_s0: dcdc-reg1 {
461				regulator-boot-on;
462				regulator-min-microvolt = <550000>;
463				regulator-max-microvolt = <950000>;
464				regulator-ramp-delay = <12500>;
465				regulator-name = "vdd_gpu_s0";
466				regulator-enable-ramp-delay = <400>;
467
468				regulator-state-mem {
469					regulator-off-in-suspend;
470				};
471			};
472
473			vdd_cpu_lit_s0: dcdc-reg2 {
474				regulator-name = "vdd_cpu_lit_s0";
475				regulator-always-on;
476				regulator-boot-on;
477				regulator-min-microvolt = <550000>;
478				regulator-max-microvolt = <950000>;
479				regulator-ramp-delay = <12500>;
480
481				regulator-state-mem {
482					regulator-off-in-suspend;
483				};
484			};
485
486			vdd_log_s0: dcdc-reg3 {
487				regulator-name = "vdd_log_s0";
488				regulator-always-on;
489				regulator-boot-on;
490				regulator-min-microvolt = <675000>;
491				regulator-max-microvolt = <750000>;
492				regulator-ramp-delay = <12500>;
493
494				regulator-state-mem {
495					regulator-off-in-suspend;
496					regulator-suspend-microvolt = <750000>;
497				};
498			};
499
500			vdd_vdenc_s0: dcdc-reg4 {
501				regulator-name = "vdd_vdenc_s0";
502				regulator-always-on;
503				regulator-boot-on;
504				regulator-min-microvolt = <550000>;
505				regulator-max-microvolt = <950000>;
506				regulator-ramp-delay = <12500>;
507
508				regulator-state-mem {
509					regulator-off-in-suspend;
510				};
511			};
512
513			vdd_ddr_s0: dcdc-reg5 {
514				regulator-name = "vdd_ddr_s0";
515				regulator-always-on;
516				regulator-boot-on;
517				regulator-min-microvolt = <675000>;
518				regulator-max-microvolt = <900000>;
519				regulator-ramp-delay = <12500>;
520
521				regulator-state-mem {
522					regulator-off-in-suspend;
523					regulator-suspend-microvolt = <850000>;
524				};
525			};
526
527			vdd2_ddr_s3: dcdc-reg6 {
528				regulator-name = "vdd2_ddr_s3";
529				regulator-always-on;
530				regulator-boot-on;
531
532				regulator-state-mem {
533					regulator-on-in-suspend;
534				};
535			};
536
537			vcc_2v0_pldo_s3: dcdc-reg7 {
538				regulator-name = "vcc_2v0_pldo_s3";
539				regulator-always-on;
540				regulator-boot-on;
541				regulator-min-microvolt = <2000000>;
542				regulator-max-microvolt = <2000000>;
543				regulator-ramp-delay = <12500>;
544
545				regulator-state-mem {
546					regulator-on-in-suspend;
547					regulator-suspend-microvolt = <2000000>;
548				};
549			};
550
551			vcc_3v3_s3: dcdc-reg8 {
552				regulator-name = "vcc_3v3_s3";
553				regulator-always-on;
554				regulator-boot-on;
555				regulator-min-microvolt = <3300000>;
556				regulator-max-microvolt = <3300000>;
557
558				regulator-state-mem {
559					regulator-on-in-suspend;
560					regulator-suspend-microvolt = <3300000>;
561				};
562			};
563
564			vddq_ddr_s0: dcdc-reg9 {
565				regulator-name = "vddq_ddr_s0";
566				regulator-always-on;
567				regulator-boot-on;
568
569				regulator-state-mem {
570					regulator-off-in-suspend;
571				};
572			};
573
574			vcc_1v8_s3: dcdc-reg10 {
575				regulator-name = "vcc_1v8_s3";
576				regulator-always-on;
577				regulator-boot-on;
578				regulator-min-microvolt = <1800000>;
579				regulator-max-microvolt = <1800000>;
580
581				regulator-state-mem {
582					regulator-on-in-suspend;
583					regulator-suspend-microvolt = <1800000>;
584				};
585			};
586
587			vcca_1v8_s0: pldo-reg1 {
588				regulator-name = "vcca_1v8_s0";
589				regulator-always-on;
590				regulator-boot-on;
591				regulator-min-microvolt = <1800000>;
592				regulator-max-microvolt = <1800000>;
593
594				regulator-state-mem {
595					regulator-off-in-suspend;
596				};
597			};
598
599			vcc_1v8_s0: pldo-reg2 {
600				regulator-name = "vcc_1v8_s0";
601				regulator-always-on;
602				regulator-boot-on;
603				regulator-min-microvolt = <1800000>;
604				regulator-max-microvolt = <1800000>;
605
606				regulator-state-mem {
607					regulator-off-in-suspend;
608					regulator-suspend-microvolt = <1800000>;
609				};
610			};
611
612			vdda_1v2_s0: pldo-reg3 {
613				regulator-name = "vdda_1v2_s0";
614				regulator-always-on;
615				regulator-boot-on;
616				regulator-min-microvolt = <1200000>;
617				regulator-max-microvolt = <1200000>;
618
619				regulator-state-mem {
620					regulator-off-in-suspend;
621				};
622			};
623
624			vcca_3v3_s0: pldo-reg4 {
625				regulator-name = "vcca_3v3_s0";
626				regulator-always-on;
627				regulator-boot-on;
628				regulator-min-microvolt = <3300000>;
629				regulator-max-microvolt = <3300000>;
630				regulator-ramp-delay = <12500>;
631
632				regulator-state-mem {
633					regulator-off-in-suspend;
634				};
635			};
636
637			vccio_sd_s0: pldo-reg5 {
638				regulator-name = "vccio_sd_s0";
639				regulator-always-on;
640				regulator-boot-on;
641				regulator-min-microvolt = <1800000>;
642				regulator-max-microvolt = <3300000>;
643				regulator-ramp-delay = <12500>;
644
645				regulator-state-mem {
646					regulator-off-in-suspend;
647				};
648			};
649
650			pldo6_s3: pldo-reg6 {
651				regulator-name = "pldo6_s3";
652				regulator-always-on;
653				regulator-boot-on;
654				regulator-min-microvolt = <1800000>;
655				regulator-max-microvolt = <1800000>;
656
657				regulator-state-mem {
658					regulator-on-in-suspend;
659					regulator-suspend-microvolt = <1800000>;
660				};
661			};
662
663			vdd_0v75_s3: nldo-reg1 {
664				regulator-name = "vdd_0v75_s3";
665				regulator-always-on;
666				regulator-boot-on;
667				regulator-min-microvolt = <750000>;
668				regulator-max-microvolt = <750000>;
669
670				regulator-state-mem {
671					regulator-on-in-suspend;
672					regulator-suspend-microvolt = <750000>;
673				};
674			};
675
676			vdda_ddr_pll_s0: nldo-reg2 {
677				regulator-name = "vdda_ddr_pll_s0";
678				regulator-always-on;
679				regulator-boot-on;
680				regulator-min-microvolt = <850000>;
681				regulator-max-microvolt = <850000>;
682
683				regulator-state-mem {
684					regulator-off-in-suspend;
685					regulator-suspend-microvolt = <850000>;
686				};
687			};
688
689			vdda_0v75_s0: nldo-reg3 {
690				regulator-name = "vdda_0v75_s0";
691				regulator-always-on;
692				regulator-boot-on;
693				regulator-min-microvolt = <750000>;
694				regulator-max-microvolt = <750000>;
695
696				regulator-state-mem {
697					regulator-off-in-suspend;
698				};
699			};
700
701			vdda_0v85_s0: nldo-reg4 {
702				regulator-name = "vdda_0v85_s0";
703				regulator-always-on;
704				regulator-boot-on;
705				regulator-min-microvolt = <850000>;
706				regulator-max-microvolt = <850000>;
707
708				regulator-state-mem {
709					regulator-off-in-suspend;
710				};
711			};
712
713			vdd_0v75_s0: nldo-reg5 {
714				regulator-name = "vdd_0v75_s0";
715				regulator-always-on;
716				regulator-boot-on;
717				regulator-min-microvolt = <750000>;
718				regulator-max-microvolt = <750000>;
719
720				regulator-state-mem {
721					regulator-off-in-suspend;
722				};
723			};
724		};
725	};
726};
727
728&tsadc {
729	status = "okay";
730};
731
732/* Routed to UART0 on the Q7 connector */
733&uart2 {
734	pinctrl-0 = <&uart2m2_xfer>;
735};
736
737/* Mule-ATtiny UPDI */
738&uart4 {
739	pinctrl-0 = <&uart4m2_xfer>;
740	status = "okay";
741};