rk3588-jaguar-pre-ict-tester.dtso

  1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
  2/*
  3 * Copyright (c) 2024 Cherry Embedded Solutions GmbH
  4 *
  5 * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine
  6 * connector on RK3588 Jaguar.
  7 *
  8 * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary
  9 * camera connectors (each their own I2C bus, clock, reset and PWM lines as well
 10 * as 2-lane CSI).
 11 *
 12 * This adapter routes some GPIOs to power rails and loops together some other
 13 * GPIOs.
 14 *
 15 * This adapter is used during manufacturing for validating proper soldering of
 16 * the mezzanine connector.
 17 */
 18
 19/dts-v1/;
 20/plugin/;
 21
 22#include <dt-bindings/gpio/gpio.h>
 23#include <dt-bindings/pinctrl/rockchip.h>
 24
 25&{/} {
 26	pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
 27		compatible = "regulator-fixed";
 28		regulator-name = "pre_ict_tester_vcc_1v2";
 29		regulator-always-on;
 30		regulator-boot-on;
 31		regulator-min-microvolt = <1200000>;
 32		regulator-max-microvolt = <1200000>;
 33		vin-supply = <&vcc_3v3_s3>;
 34	};
 35
 36	pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 {
 37		compatible = "regulator-fixed";
 38		regulator-name = "pre_ict_tester_vcc_2v8";
 39		regulator-always-on;
 40		regulator-boot-on;
 41		regulator-min-microvolt = <2800000>;
 42		regulator-max-microvolt = <2800000>;
 43		vin-supply = <&vcc_3v3_s3>;
 44	};
 45};
 46
 47&combphy0_ps {
 48	status = "okay";
 49};
 50
 51&gpio3 {
 52	pinctrl-0 = <&pre_ict_pwr2gpio>;
 53	pinctrl-names = "default";
 54};
 55
 56&pcie2x1l2 {
 57	pinctrl-names = "default";
 58	pinctrl-0 = <&pcie2x1l2_perstn_m0>;
 59	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */
 60	vpcie3v3-supply = <&vcc_3v3_s3>;
 61	status = "okay";
 62};
 63
 64&pinctrl {
 65	pcie2x1l2 {
 66		pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 {
 67			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
 68		};
 69	};
 70
 71	pre-ict-tester {
 72		pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins {
 73			rockchip,pins =
 74			/*
 75			 * GPIO3_A3 requires two power rails to be properly
 76			 * routed to the mezzanine connector to report a proper
 77			 * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an
 78			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
 79			 * but GPIO3_C6 would catch this HW soldering issue.
 80			 * If VCC_IN_2 is properly routed, GPIO3_A3 should be
 81			 * LOW. The signal shall not read HIGH in the event
 82			 * GPIO3_A3 isn't properly routed due to soldering
 83			 * issue. Therefore, let's enforce a pull-up (which is
 84			 * the SoC default for this pin).
 85			 */
 86				<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
 87			/*
 88			 * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power
 89			 * rail. It should be HIGH if all is properly soldered.
 90			 * To guarantee that, a pull-down is enforced (which is
 91			 * the SoC default for this pin) so that LOW is read if
 92			 * the loop doesn't exist on HW (soldering issue on
 93			 * either signals).
 94			 */
 95				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>,
 96			/*
 97			 * GPIO3_B2 requires two power rails to be properly
 98			 * routed to the mezzanine connector to report a proper
 99			 * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an
100			 * incorrect value if VCC_1V8_S0_1 isn't properly routed,
101			 * but GPIO3_C6 would catch this HW soldering issue.
102			 * If VCC_IN_1 is properly routed, GPIO3_B2 should be
103			 * LOW. This is an issue if GPIO3_B2 isn't properly
104			 * routed due to soldering issue, because GPIO3_B2
105			 * default bias is pull-down therefore being LOW. So
106			 * the worst case scenario and the pass scenario expect
107			 * the same value. Make GPIO3_B2 a pull-up so that a
108			 * soldering issue on GPIO3_B2 reports HIGH but proper
109			 * soldering reports LOW.
110			 */
111				<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
112			/*
113			 * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power
114			 * rail. It should be HIGH if all is properly soldered.
115			 * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't
116			 * properly routed due to soldering issue, because
117			 * GPIO3_C6 default bias is pull-up therefore being HIGH
118			 * in all cases:
119			 *  - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not
120			 *    routed properly,
121			 *  - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is
122			 *    not routed properly,
123			 *  - GPIO3_C6 is HIGH if everything is proper,
124			 * Make GPIO3_C6 a pull-down so that a soldering issue
125			 * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper
126			 * soldering reports HIGH.
127			 */
128				<3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>,
129			/*
130			 * GPIO3_D2 is routed to VCC_5V0_1 power rail through a
131			 * voltage divider on the adapter.
132			 * It should be HIGH if all is properly soldered.
133			 * To guarantee that, a pull-down is enforced (which is
134			 * the SoC default for this pin) so that LOW is read if
135			 * the loop doesn't exist on HW (soldering issue on
136			 * either signals).
137			 */
138				<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>,
139			/*
140			 * GPIO3_D3 is routed to VCC_5V0_2 power rail through a
141			 * voltage divider on the adapter.
142			 * It should be HIGH if all is properly soldered.
143			 * To guarantee that, a pull-down is enforced (which is
144			 * the SoC default for this pin) so that LOW is read if
145			 * the loop doesn't exist on HW (soldering issue on
146			 * either signals).
147			 */
148				<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>,
149			/*
150			 * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through
151			 * a voltage divider on the adapter.
152			 * It should be HIGH if all is properly soldered.
153			 * To guarantee that, a pull-down is enforced (which is
154			 * the SoC default for this pin) so that LOW is read if
155			 * the loop doesn't exist on HW (soldering issue on
156			 * either signals).
157			 */
158				<3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>,
159			/*
160			 * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through
161			 * a voltage divider on the adapter.
162			 * It should be HIGH if all is properly soldered.
163			 * To guarantee that, a pull-down is enforced (which is
164			 * the SoC default for this pin) so that LOW is read if
165			 * the loop doesn't exist on HW (soldering issue on
166			 * either signals).
167			 */
168				<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
169		};
170	};
171};