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rk3588-extra.dtsi
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linux-6.19.14/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588-base.dtsi" 7#include "rk3588-extra-pinctrl.dtsi" 8 9/ { 10 hdmi1_sound: hdmi1-sound { 11 compatible = "simple-audio-card"; 12 simple-audio-card,format = "i2s"; 13 simple-audio-card,mclk-fs = <128>; 14 simple-audio-card,name = "hdmi1"; 15 status = "disabled"; 16 17 simple-audio-card,codec { 18 sound-dai = <&hdmi1>; 19 }; 20 21 simple-audio-card,cpu { 22 sound-dai = <&i2s6_8ch>; 23 }; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 /* 32 * The 4k HDMI capture controller works only with 32bit 33 * phys addresses and doesn't support IOMMU. HDMI RX CMA 34 * must be reserved below 4GB. 35 * The size of 160MB was determined as follows: 36 * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB 37 * To ensure sufficient support for practical use-cases, 38 * we doubled the 66MB value. 39 */ 40 hdmi_receiver_cma: hdmi-receiver-cma { 41 compatible = "shared-dma-pool"; 42 alloc-ranges = <0x0 0x0 0x0 0xffffffff>; 43 size = <0x0 (160 * 0x100000)>; /* 160MiB */ 44 alignment = <0x0 0x40000>; /* 64K */ 45 no-map; 46 status = "disabled"; 47 }; 48 }; 49 50 usb_host1_xhci: usb@fc400000 { 51 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 52 reg = <0x0 0xfc400000 0x0 0x400000>; 53 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 54 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 55 <&cru ACLK_USB3OTG1>; 56 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 57 dr_mode = "otg"; 58 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; 59 phy-names = "usb2-phy", "usb3-phy"; 60 phy_type = "utmi_wide"; 61 power-domains = <&power RK3588_PD_USB>; 62 resets = <&cru SRST_A_USB3OTG1>; 63 snps,dis_enblslpm_quirk; 64 snps,dis-u2-freeclk-exists-quirk; 65 snps,dis-del-phy-power-chg-quirk; 66 snps,dis-tx-ipgap-linecheck-quirk; 67 status = "disabled"; 68 }; 69 70 pcie30_phy_grf: syscon@fd5b8000 { 71 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 72 reg = <0x0 0xfd5b8000 0x0 0x10000>; 73 }; 74 75 pipe_phy1_grf: syscon@fd5c0000 { 76 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 77 reg = <0x0 0xfd5c0000 0x0 0x100>; 78 }; 79 80 usbdpphy1_grf: syscon@fd5cc000 { 81 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 82 reg = <0x0 0xfd5cc000 0x0 0x4000>; 83 }; 84 85 usb2phy1_grf: syscon@fd5d4000 { 86 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 87 reg = <0x0 0xfd5d4000 0x0 0x4000>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 91 u2phy1: usb2phy@4000 { 92 compatible = "rockchip,rk3588-usb2phy"; 93 reg = <0x4000 0x10>; 94 #clock-cells = <0>; 95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 96 clock-names = "phyclk"; 97 clock-output-names = "usb480m_phy1"; 98 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 99 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 100 reset-names = "phy", "apb"; 101 status = "disabled"; 102 103 u2phy1_otg: otg-port { 104 #phy-cells = <0>; 105 status = "disabled"; 106 }; 107 }; 108 }; 109 110 hdptxphy1_grf: syscon@fd5e4000 { 111 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 112 reg = <0x0 0xfd5e4000 0x0 0x100>; 113 }; 114 115 spdif_tx5: spdif-tx@fddb8000 { 116 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 117 reg = <0x0 0xfddb8000 0x0 0x1000>; 118 assigned-clock-parents = <&cru PLL_AUPLL>; 119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; 120 clock-names = "mclk", "hclk"; 121 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; 122 dma-names = "tx"; 123 dmas = <&dmac1 22>; 124 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 125 power-domains = <&power RK3588_PD_VO0>; 126 #sound-dai-cells = <0>; 127 status = "disabled"; 128 }; 129 130 i2s8_8ch: i2s@fddc8000 { 131 compatible = "rockchip,rk3588-i2s-tdm"; 132 reg = <0x0 0xfddc8000 0x0 0x1000>; 133 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 134 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 135 clock-names = "mclk_tx", "mclk_rx", "hclk"; 136 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 137 assigned-clock-parents = <&cru PLL_AUPLL>; 138 dmas = <&dmac2 22>; 139 dma-names = "tx"; 140 power-domains = <&power RK3588_PD_VO0>; 141 resets = <&cru SRST_M_I2S8_8CH_TX>; 142 reset-names = "tx-m"; 143 #sound-dai-cells = <0>; 144 status = "disabled"; 145 }; 146 147 spdif_tx4: spdif-tx@fdde8000 { 148 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 149 reg = <0x0 0xfdde8000 0x0 0x1000>; 150 assigned-clock-parents = <&cru PLL_AUPLL>; 151 assigned-clocks = <&cru CLK_SPDIF4_SRC>; 152 clock-names = "mclk", "hclk"; 153 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 154 dma-names = "tx"; 155 dmas = <&dmac1 8>; 156 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 157 power-domains = <&power RK3588_PD_VO1>; 158 #sound-dai-cells = <0>; 159 status = "disabled"; 160 }; 161 162 i2s6_8ch: i2s@fddf4000 { 163 compatible = "rockchip,rk3588-i2s-tdm"; 164 reg = <0x0 0xfddf4000 0x0 0x1000>; 165 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 166 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 167 clock-names = "mclk_tx", "mclk_rx", "hclk"; 168 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 169 assigned-clock-parents = <&cru PLL_AUPLL>; 170 dmas = <&dmac2 4>; 171 dma-names = "tx"; 172 power-domains = <&power RK3588_PD_VO1>; 173 resets = <&cru SRST_M_I2S6_8CH_TX>; 174 reset-names = "tx-m"; 175 #sound-dai-cells = <0>; 176 status = "disabled"; 177 }; 178 179 i2s7_8ch: i2s@fddf8000 { 180 compatible = "rockchip,rk3588-i2s-tdm"; 181 reg = <0x0 0xfddf8000 0x0 0x1000>; 182 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 183 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 184 clock-names = "mclk_tx", "mclk_rx", "hclk"; 185 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 186 assigned-clock-parents = <&cru PLL_AUPLL>; 187 dmas = <&dmac2 21>; 188 dma-names = "rx"; 189 power-domains = <&power RK3588_PD_VO1>; 190 resets = <&cru SRST_M_I2S7_8CH_RX>; 191 reset-names = "rx-m"; 192 #sound-dai-cells = <0>; 193 status = "disabled"; 194 }; 195 196 i2s10_8ch: i2s@fde00000 { 197 compatible = "rockchip,rk3588-i2s-tdm"; 198 reg = <0x0 0xfde00000 0x0 0x1000>; 199 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 201 clock-names = "mclk_tx", "mclk_rx", "hclk"; 202 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 203 assigned-clock-parents = <&cru PLL_AUPLL>; 204 dmas = <&dmac2 24>; 205 dma-names = "rx"; 206 power-domains = <&power RK3588_PD_VO1>; 207 resets = <&cru SRST_M_I2S10_8CH_RX>; 208 reset-names = "rx-m"; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 dp1: dp@fde60000 { 214 compatible = "rockchip,rk3588-dp"; 215 reg = <0x0 0xfde60000 0x0 0x4000>; 216 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 217 assigned-clocks = <&cru CLK_AUX16M_1>; 218 assigned-clock-rates = <16000000>; 219 clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, 220 <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>, 221 <&cru MCLK_SPDIF5_DP1>; 222 clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; 223 phys = <&usbdp_phy1 PHY_TYPE_DP>; 224 power-domains = <&power RK3588_PD_VO0>; 225 resets = <&cru SRST_DP1>; 226 #sound-dai-cells = <0>; 227 status = "disabled"; 228 229 ports { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 233 dp1_in: port@0 { 234 reg = <0>; 235 }; 236 237 dp1_out: port@1 { 238 reg = <1>; 239 }; 240 }; 241 }; 242 243 hdmi1: hdmi@fdea0000 { 244 compatible = "rockchip,rk3588-dw-hdmi-qp"; 245 reg = <0x0 0xfdea0000 0x0 0x20000>; 246 clocks = <&cru PCLK_HDMITX1>, 247 <&cru CLK_HDMITX1_EARC>, 248 <&cru CLK_HDMITX1_REF>, 249 <&cru MCLK_I2S6_8CH_TX>, 250 <&cru CLK_HDMIHDP1>, 251 <&cru HCLK_VO1>; 252 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 253 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, 254 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, 255 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, 256 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, 257 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 258 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 259 phys = <&hdptxphy1>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd 262 &hdmim1_tx1_scl &hdmim1_tx1_sda>; 263 power-domains = <&power RK3588_PD_VO1>; 264 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; 265 reset-names = "ref", "hdp"; 266 rockchip,grf = <&sys_grf>; 267 rockchip,vo-grf = <&vo1_grf>; 268 #sound-dai-cells = <0>; 269 status = "disabled"; 270 271 ports { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 hdmi1_in: port@0 { 276 reg = <0>; 277 }; 278 279 hdmi1_out: port@1 { 280 reg = <1>; 281 }; 282 }; 283 }; 284 285 edp1: edp@fded0000 { 286 compatible = "rockchip,rk3588-edp"; 287 reg = <0x0 0xfded0000 0x0 0x1000>; 288 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>; 289 clock-names = "dp", "pclk"; 290 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 291 phys = <&hdptxphy1>; 292 phy-names = "dp"; 293 power-domains = <&power RK3588_PD_VO1>; 294 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; 295 reset-names = "dp", "apb"; 296 rockchip,grf = <&vo1_grf>; 297 status = "disabled"; 298 299 ports { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 edp1_in: port@0 { 304 reg = <0>; 305 }; 306 307 edp1_out: port@1 { 308 reg = <1>; 309 }; 310 }; 311 }; 312 313 hdmi_receiver: hdmi_receiver@fdee0000 { 314 compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; 315 reg = <0x0 0xfdee0000 0x0 0x6000>; 316 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, 317 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, 318 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; 319 interrupt-names = "cec", "hdmi", "dma"; 320 clocks = <&cru ACLK_HDMIRX>, 321 <&cru CLK_HDMIRX_AUD>, 322 <&cru CLK_CR_PARA>, 323 <&cru PCLK_HDMIRX>, 324 <&cru CLK_HDMIRX_REF>, 325 <&cru PCLK_S_HDMIRX>, 326 <&cru HCLK_VO1>; 327 clock-names = "aclk", 328 "audio", 329 "cr_para", 330 "pclk", 331 "ref", 332 "hclk_s_hdmirx", 333 "hclk_vo1"; 334 memory-region = <&hdmi_receiver_cma>; 335 power-domains = <&power RK3588_PD_VO1>; 336 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, 337 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; 338 reset-names = "axi", "apb", "ref", "biu"; 339 rockchip,grf = <&sys_grf>; 340 rockchip,vo1-grf = <&vo1_grf>; 341 status = "disabled"; 342 }; 343 344 pcie3x4: pcie@fe150000 { 345 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 346 #address-cells = <3>; 347 #size-cells = <2>; 348 bus-range = <0x00 0x0f>; 349 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 350 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 351 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 352 clock-names = "aclk_mst", "aclk_slv", 353 "aclk_dbi", "pclk", 354 "aux", "pipe"; 355 device_type = "pci"; 356 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 361 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 362 #interrupt-cells = <1>; 363 interrupt-map-mask = <0 0 0 7>; 364 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 365 <0 0 0 2 &pcie3x4_intc 1>, 366 <0 0 0 3 &pcie3x4_intc 2>, 367 <0 0 0 4 &pcie3x4_intc 3>; 368 linux,pci-domain = <0>; 369 max-link-speed = <3>; 370 msi-map = <0x0000 &its1 0x0000 0x1000>; 371 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>; 372 num-lanes = <4>; 373 phys = <&pcie30phy>; 374 phy-names = "pcie-phy"; 375 power-domains = <&power RK3588_PD_PCIE>; 376 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 377 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 378 <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; 379 reg = <0xa 0x40000000 0x0 0x00400000>, 380 <0x0 0xfe150000 0x0 0x00010000>, 381 <0x0 0xf0000000 0x0 0x00100000>; 382 reg-names = "dbi", "apb", "config"; 383 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 384 reset-names = "pwr", "pipe"; 385 status = "disabled"; 386 387 pcie3x4_intc: legacy-interrupt-controller { 388 interrupt-controller; 389 #address-cells = <0>; 390 #interrupt-cells = <1>; 391 interrupt-parent = <&gic>; 392 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 393 }; 394 }; 395 396 pcie3x4_ep: pcie-ep@fe150000 { 397 compatible = "rockchip,rk3588-pcie-ep"; 398 reg = <0xa 0x40000000 0x0 0x00100000>, 399 <0xa 0x40100000 0x0 0x00100000>, 400 <0x0 0xfe150000 0x0 0x00010000>, 401 <0x9 0x00000000 0x0 0x40000000>, 402 <0xa 0x40300000 0x0 0x00100000>; 403 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; 404 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 405 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 406 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 407 clock-names = "aclk_mst", "aclk_slv", 408 "aclk_dbi", "pclk", 409 "aux", "pipe"; 410 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 411 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 412 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 413 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 414 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, 415 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, 416 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, 417 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, 418 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 419 interrupt-names = "sys", "pmc", "msg", "legacy", "err", 420 "dma0", "dma1", "dma2", "dma3"; 421 max-link-speed = <3>; 422 num-lanes = <4>; 423 phys = <&pcie30phy>; 424 phy-names = "pcie-phy"; 425 power-domains = <&power RK3588_PD_PCIE>; 426 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 427 reset-names = "pwr", "pipe"; 428 status = "disabled"; 429 }; 430 431 pcie3x2: pcie@fe160000 { 432 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 433 #address-cells = <3>; 434 #size-cells = <2>; 435 bus-range = <0x10 0x1f>; 436 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 437 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 438 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 439 clock-names = "aclk_mst", "aclk_slv", 440 "aclk_dbi", "pclk", 441 "aux", "pipe"; 442 device_type = "pci"; 443 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 444 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 445 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 446 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 447 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 448 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 449 #interrupt-cells = <1>; 450 interrupt-map-mask = <0 0 0 7>; 451 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 452 <0 0 0 2 &pcie3x2_intc 1>, 453 <0 0 0 3 &pcie3x2_intc 2>, 454 <0 0 0 4 &pcie3x2_intc 3>; 455 linux,pci-domain = <1>; 456 max-link-speed = <3>; 457 msi-map = <0x1000 &its1 0x1000 0x1000>; 458 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>; 459 num-lanes = <2>; 460 phys = <&pcie30phy>; 461 phy-names = "pcie-phy"; 462 power-domains = <&power RK3588_PD_PCIE>; 463 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 464 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 465 <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; 466 reg = <0xa 0x40400000 0x0 0x00400000>, 467 <0x0 0xfe160000 0x0 0x00010000>, 468 <0x0 0xf1000000 0x0 0x00100000>; 469 reg-names = "dbi", "apb", "config"; 470 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 471 reset-names = "pwr", "pipe"; 472 status = "disabled"; 473 474 pcie3x2_intc: legacy-interrupt-controller { 475 interrupt-controller; 476 #address-cells = <0>; 477 #interrupt-cells = <1>; 478 interrupt-parent = <&gic>; 479 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 480 }; 481 }; 482 483 pcie2x1l0: pcie@fe170000 { 484 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 485 bus-range = <0x20 0x2f>; 486 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 487 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 488 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 489 clock-names = "aclk_mst", "aclk_slv", 490 "aclk_dbi", "pclk", 491 "aux", "pipe"; 492 device_type = "pci"; 493 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 494 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 495 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 496 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 497 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 498 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 499 #interrupt-cells = <1>; 500 interrupt-map-mask = <0 0 0 7>; 501 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 502 <0 0 0 2 &pcie2x1l0_intc 1>, 503 <0 0 0 3 &pcie2x1l0_intc 2>, 504 <0 0 0 4 &pcie2x1l0_intc 3>; 505 linux,pci-domain = <2>; 506 max-link-speed = <2>; 507 msi-map = <0x2000 &its0 0x2000 0x1000>; 508 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>; 509 num-lanes = <1>; 510 phys = <&combphy1_ps PHY_TYPE_PCIE>; 511 phy-names = "pcie-phy"; 512 power-domains = <&power RK3588_PD_PCIE>; 513 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 514 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 515 <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; 516 reg = <0xa 0x40800000 0x0 0x00400000>, 517 <0x0 0xfe170000 0x0 0x00010000>, 518 <0x0 0xf2000000 0x0 0x00100000>; 519 reg-names = "dbi", "apb", "config"; 520 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 521 reset-names = "pwr", "pipe"; 522 #address-cells = <3>; 523 #size-cells = <2>; 524 status = "disabled"; 525 526 pcie2x1l0_intc: legacy-interrupt-controller { 527 interrupt-controller; 528 #address-cells = <0>; 529 #interrupt-cells = <1>; 530 interrupt-parent = <&gic>; 531 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 532 }; 533 }; 534 535 gmac0: ethernet@fe1b0000 { 536 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 537 reg = <0x0 0xfe1b0000 0x0 0x10000>; 538 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 539 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 540 interrupt-names = "macirq", "eth_wake_irq"; 541 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 542 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 543 <&cru CLK_GMAC0_PTP_REF>; 544 clock-names = "stmmaceth", "clk_mac_ref", 545 "pclk_mac", "aclk_mac", 546 "ptp_ref"; 547 power-domains = <&power RK3588_PD_GMAC>; 548 resets = <&cru SRST_A_GMAC0>; 549 reset-names = "stmmaceth"; 550 rockchip,grf = <&sys_grf>; 551 rockchip,php-grf = <&php_grf>; 552 snps,axi-config = <&gmac0_stmmac_axi_setup>; 553 snps,mixed-burst; 554 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 555 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 556 snps,tso; 557 status = "disabled"; 558 559 mdio0: mdio { 560 compatible = "snps,dwmac-mdio"; 561 #address-cells = <0x1>; 562 #size-cells = <0x0>; 563 }; 564 565 gmac0_stmmac_axi_setup: stmmac-axi-config { 566 snps,blen = <0 0 0 0 16 8 4>; 567 snps,wr_osr_lmt = <4>; 568 snps,rd_osr_lmt = <8>; 569 }; 570 571 gmac0_mtl_rx_setup: rx-queues-config { 572 snps,rx-queues-to-use = <2>; 573 queue0 {}; 574 queue1 {}; 575 }; 576 577 gmac0_mtl_tx_setup: tx-queues-config { 578 snps,tx-queues-to-use = <2>; 579 queue0 {}; 580 queue1 {}; 581 }; 582 }; 583 584 sata1: sata@fe220000 { 585 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 586 reg = <0 0xfe220000 0 0x1000>; 587 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 588 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 589 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 590 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 591 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 592 ports-implemented = <0x1>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 597 sata-port@0 { 598 reg = <0>; 599 hba-port-cap = <HBA_PORT_FBSCP>; 600 phys = <&combphy1_ps PHY_TYPE_SATA>; 601 phy-names = "sata-phy"; 602 snps,rx-ts-max = <32>; 603 snps,tx-ts-max = <32>; 604 }; 605 }; 606 607 hdptxphy1: phy@fed70000 { 608 compatible = "rockchip,rk3588-hdptx-phy"; 609 reg = <0x0 0xfed70000 0x0 0x2000>; 610 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 611 clock-names = "ref", "apb"; 612 #clock-cells = <0>; 613 #phy-cells = <0>; 614 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 615 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 616 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 617 <&cru SRST_HDPTX1_LCPLL>; 618 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 619 "lcpll"; 620 rockchip,grf = <&hdptxphy1_grf>; 621 status = "disabled"; 622 }; 623 624 usbdp_phy1: phy@fed90000 { 625 compatible = "rockchip,rk3588-usbdp-phy"; 626 reg = <0x0 0xfed90000 0x0 0x10000>; 627 #phy-cells = <1>; 628 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 629 <&cru CLK_USBDP_PHY1_IMMORTAL>, 630 <&cru PCLK_USBDPPHY1>, 631 <&u2phy1>; 632 clock-names = "refclk", "immortal", "pclk", "utmi"; 633 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 634 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 635 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 636 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 637 <&cru SRST_P_USBDPPHY1>; 638 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 639 rockchip,u2phy-grf = <&usb2phy1_grf>; 640 rockchip,usb-grf = <&usb_grf>; 641 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 642 rockchip,vo-grf = <&vo0_grf>; 643 status = "disabled"; 644 }; 645 646 combphy1_ps: phy@fee10000 { 647 compatible = "rockchip,rk3588-naneng-combphy"; 648 reg = <0x0 0xfee10000 0x0 0x100>; 649 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 650 <&cru PCLK_PHP_ROOT>; 651 clock-names = "ref", "apb", "pipe"; 652 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 653 assigned-clock-rates = <100000000>; 654 #phy-cells = <1>; 655 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 656 reset-names = "phy", "apb"; 657 rockchip,pipe-grf = <&php_grf>; 658 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 659 status = "disabled"; 660 }; 661 662 pcie30phy: phy@fee80000 { 663 compatible = "rockchip,rk3588-pcie3-phy"; 664 reg = <0x0 0xfee80000 0x0 0x20000>; 665 #phy-cells = <0>; 666 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 667 clock-names = "pclk"; 668 resets = <&cru SRST_PCIE30_PHY>; 669 reset-names = "phy"; 670 rockchip,pipe-grf = <&php_grf>; 671 rockchip,phy-grf = <&pcie30_phy_grf>; 672 status = "disabled"; 673 }; 674}; 675 676&vop { 677 clocks = <&cru ACLK_VOP>, 678 <&cru HCLK_VOP>, 679 <&cru DCLK_VOP0>, 680 <&cru DCLK_VOP1>, 681 <&cru DCLK_VOP2>, 682 <&cru DCLK_VOP3>, 683 <&cru PCLK_VOP_ROOT>, 684 <&hdptxphy0>, 685 <&hdptxphy1>; 686 clock-names = "aclk", 687 "hclk", 688 "dclk_vp0", 689 "dclk_vp1", 690 "dclk_vp2", 691 "dclk_vp3", 692 "pclk_vop", 693 "pll_hdmiphy0", 694 "pll_hdmiphy1"; 695};
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