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rk3588-base.dtsi
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linux-6.19.14/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/reset/rockchip,rk3588-cru.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/ata/ahci.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3588"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 i2c6 = &i2c6; 36 i2c7 = &i2c7; 37 i2c8 = &i2c8; 38 serial0 = &uart0; 39 serial1 = &uart1; 40 serial2 = &uart2; 41 serial3 = &uart3; 42 serial4 = &uart4; 43 serial5 = &uart5; 44 serial6 = &uart6; 45 serial7 = &uart7; 46 serial8 = &uart8; 47 serial9 = &uart9; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 spi3 = &spi3; 52 spi4 = &spi4; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu_l0>; 63 }; 64 core1 { 65 cpu = <&cpu_l1>; 66 }; 67 core2 { 68 cpu = <&cpu_l2>; 69 }; 70 core3 { 71 cpu = <&cpu_l3>; 72 }; 73 }; 74 cluster1 { 75 core0 { 76 cpu = <&cpu_b0>; 77 }; 78 core1 { 79 cpu = <&cpu_b1>; 80 }; 81 }; 82 cluster2 { 83 core0 { 84 cpu = <&cpu_b2>; 85 }; 86 core1 { 87 cpu = <&cpu_b3>; 88 }; 89 }; 90 }; 91 92 cpu_l0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a55"; 95 reg = <0x0>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <530>; 98 clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 cpu-idle-states = <&CPU_SLEEP>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l0>; 107 dynamic-power-coefficient = <228>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu_l1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <530>; 117 clocks = <&scmi_clk SCMI_CLK_CPUL>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_cache_l1>; 126 dynamic-power-coefficient = <228>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu_l2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x200>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <530>; 136 clocks = <&scmi_clk SCMI_CLK_CPUL>; 137 cpu-idle-states = <&CPU_SLEEP>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l2>; 145 dynamic-power-coefficient = <228>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu_l3: cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <530>; 155 clocks = <&scmi_clk SCMI_CLK_CPUL>; 156 cpu-idle-states = <&CPU_SLEEP>; 157 i-cache-size = <32768>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <128>; 160 d-cache-size = <32768>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <128>; 163 next-level-cache = <&l2_cache_l3>; 164 dynamic-power-coefficient = <228>; 165 #cooling-cells = <2>; 166 }; 167 168 cpu_b0: cpu@400 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a76"; 171 reg = <0x400>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_b0>; 183 dynamic-power-coefficient = <416>; 184 #cooling-cells = <2>; 185 }; 186 187 cpu_b1: cpu@500 { 188 device_type = "cpu"; 189 compatible = "arm,cortex-a76"; 190 reg = <0x500>; 191 enable-method = "psci"; 192 capacity-dmips-mhz = <1024>; 193 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 194 cpu-idle-states = <&CPU_SLEEP>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_cache_b1>; 202 dynamic-power-coefficient = <416>; 203 #cooling-cells = <2>; 204 }; 205 206 cpu_b2: cpu@600 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a76"; 209 reg = <0x600>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 213 cpu-idle-states = <&CPU_SLEEP>; 214 i-cache-size = <65536>; 215 i-cache-line-size = <64>; 216 i-cache-sets = <256>; 217 d-cache-size = <65536>; 218 d-cache-line-size = <64>; 219 d-cache-sets = <256>; 220 next-level-cache = <&l2_cache_b2>; 221 dynamic-power-coefficient = <416>; 222 #cooling-cells = <2>; 223 }; 224 225 cpu_b3: cpu@700 { 226 device_type = "cpu"; 227 compatible = "arm,cortex-a76"; 228 reg = <0x700>; 229 enable-method = "psci"; 230 capacity-dmips-mhz = <1024>; 231 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 232 cpu-idle-states = <&CPU_SLEEP>; 233 i-cache-size = <65536>; 234 i-cache-line-size = <64>; 235 i-cache-sets = <256>; 236 d-cache-size = <65536>; 237 d-cache-line-size = <64>; 238 d-cache-sets = <256>; 239 next-level-cache = <&l2_cache_b3>; 240 dynamic-power-coefficient = <416>; 241 #cooling-cells = <2>; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 CPU_SLEEP: cpu-sleep { 247 compatible = "arm,idle-state"; 248 local-timer-stop; 249 arm,psci-suspend-param = <0x0010000>; 250 entry-latency-us = <100>; 251 exit-latency-us = <120>; 252 min-residency-us = <1000>; 253 }; 254 }; 255 256 l2_cache_l0: l2-cache-l0 { 257 compatible = "cache"; 258 cache-size = <131072>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 cache-level = <2>; 262 cache-unified; 263 next-level-cache = <&l3_cache>; 264 }; 265 266 l2_cache_l1: l2-cache-l1 { 267 compatible = "cache"; 268 cache-size = <131072>; 269 cache-line-size = <64>; 270 cache-sets = <512>; 271 cache-level = <2>; 272 cache-unified; 273 next-level-cache = <&l3_cache>; 274 }; 275 276 l2_cache_l2: l2-cache-l2 { 277 compatible = "cache"; 278 cache-size = <131072>; 279 cache-line-size = <64>; 280 cache-sets = <512>; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&l3_cache>; 284 }; 285 286 l2_cache_l3: l2-cache-l3 { 287 compatible = "cache"; 288 cache-size = <131072>; 289 cache-line-size = <64>; 290 cache-sets = <512>; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&l3_cache>; 294 }; 295 296 l2_cache_b0: l2-cache-b0 { 297 compatible = "cache"; 298 cache-size = <524288>; 299 cache-line-size = <64>; 300 cache-sets = <1024>; 301 cache-level = <2>; 302 cache-unified; 303 next-level-cache = <&l3_cache>; 304 }; 305 306 l2_cache_b1: l2-cache-b1 { 307 compatible = "cache"; 308 cache-size = <524288>; 309 cache-line-size = <64>; 310 cache-sets = <1024>; 311 cache-level = <2>; 312 cache-unified; 313 next-level-cache = <&l3_cache>; 314 }; 315 316 l2_cache_b2: l2-cache-b2 { 317 compatible = "cache"; 318 cache-size = <524288>; 319 cache-line-size = <64>; 320 cache-sets = <1024>; 321 cache-level = <2>; 322 cache-unified; 323 next-level-cache = <&l3_cache>; 324 }; 325 326 l2_cache_b3: l2-cache-b3 { 327 compatible = "cache"; 328 cache-size = <524288>; 329 cache-line-size = <64>; 330 cache-sets = <1024>; 331 cache-level = <2>; 332 cache-unified; 333 next-level-cache = <&l3_cache>; 334 }; 335 }; 336 337 /* 338 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 339 * so it's represented here, outside the "cpus" node 340 */ 341 l3_cache: l3-cache { 342 compatible = "cache"; 343 cache-size = <3145728>; 344 cache-line-size = <64>; 345 cache-sets = <4096>; 346 cache-level = <3>; 347 cache-unified; 348 }; 349 350 display_subsystem: display-subsystem { 351 compatible = "rockchip,display-subsystem"; 352 ports = <&vop_out>; 353 }; 354 355 firmware { 356 scmi: scmi { 357 compatible = "arm,scmi-smc"; 358 arm,smc-id = <0x82000010>; 359 shmem = <&scmi_shmem>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 scmi_clk: protocol@14 { 364 reg = <0x14>; 365 #clock-cells = <1>; 366 }; 367 368 scmi_reset: protocol@16 { 369 reg = <0x16>; 370 #reset-cells = <1>; 371 }; 372 }; 373 }; 374 375 hdmi0_sound: hdmi0-sound { 376 compatible = "simple-audio-card"; 377 simple-audio-card,format = "i2s"; 378 simple-audio-card,mclk-fs = <128>; 379 simple-audio-card,name = "hdmi0"; 380 status = "disabled"; 381 382 simple-audio-card,codec { 383 sound-dai = <&hdmi0>; 384 }; 385 386 simple-audio-card,cpu { 387 sound-dai = <&i2s5_8ch>; 388 }; 389 }; 390 391 pmu-a55 { 392 compatible = "arm,cortex-a55-pmu"; 393 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 394 }; 395 396 pmu-a76 { 397 compatible = "arm,cortex-a76-pmu"; 398 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 399 }; 400 401 psci { 402 compatible = "arm,psci-1.0"; 403 method = "smc"; 404 }; 405 406 spll: clock-0 { 407 compatible = "fixed-clock"; 408 clock-frequency = <702000000>; 409 clock-output-names = "spll"; 410 #clock-cells = <0>; 411 }; 412 413 timer { 414 compatible = "arm,armv8-timer"; 415 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 416 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 417 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 418 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 419 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 420 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 421 }; 422 423 xin24m: clock-1 { 424 compatible = "fixed-clock"; 425 clock-frequency = <24000000>; 426 clock-output-names = "xin24m"; 427 #clock-cells = <0>; 428 }; 429 430 xin32k: clock-2 { 431 compatible = "fixed-clock"; 432 clock-frequency = <32768>; 433 clock-output-names = "xin32k"; 434 #clock-cells = <0>; 435 }; 436 437 reserved-memory { 438 #address-cells = <2>; 439 #size-cells = <2>; 440 ranges; 441 442 scmi_shmem: shmem@10f000 { 443 compatible = "arm,scmi-shmem"; 444 reg = <0x0 0x0010f000 0x0 0x100>; 445 no-map; 446 }; 447 }; 448 449 gpu: gpu@fb000000 { 450 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 451 reg = <0x0 0xfb000000 0x0 0x200000>; 452 #cooling-cells = <2>; 453 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 454 assigned-clock-rates = <200000000>; 455 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 456 <&cru CLK_GPU_STACKS>; 457 clock-names = "core", "coregroup", "stacks"; 458 dynamic-power-coefficient = <2982>; 459 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 460 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 461 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 462 interrupt-names = "job", "mmu", "gpu"; 463 power-domains = <&power RK3588_PD_GPU>; 464 status = "disabled"; 465 }; 466 467 usb_host0_xhci: usb@fc000000 { 468 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 469 reg = <0x0 0xfc000000 0x0 0x400000>; 470 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 471 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 472 <&cru ACLK_USB3OTG0>; 473 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 474 dr_mode = "otg"; 475 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 476 phy-names = "usb2-phy", "usb3-phy"; 477 phy_type = "utmi_wide"; 478 power-domains = <&power RK3588_PD_USB>; 479 resets = <&cru SRST_A_USB3OTG0>; 480 snps,dis_enblslpm_quirk; 481 snps,dis-u1-entry-quirk; 482 snps,dis-u2-entry-quirk; 483 snps,dis-u2-freeclk-exists-quirk; 484 snps,dis-del-phy-power-chg-quirk; 485 snps,dis-tx-ipgap-linecheck-quirk; 486 status = "disabled"; 487 }; 488 489 usb_host0_ehci: usb@fc800000 { 490 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 491 reg = <0x0 0xfc800000 0x0 0x40000>; 492 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 493 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 494 phys = <&u2phy2_host>; 495 phy-names = "usb"; 496 power-domains = <&power RK3588_PD_USB>; 497 status = "disabled"; 498 }; 499 500 usb_host0_ohci: usb@fc840000 { 501 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 502 reg = <0x0 0xfc840000 0x0 0x40000>; 503 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 504 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 505 phys = <&u2phy2_host>; 506 phy-names = "usb"; 507 power-domains = <&power RK3588_PD_USB>; 508 status = "disabled"; 509 }; 510 511 usb_host1_ehci: usb@fc880000 { 512 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 513 reg = <0x0 0xfc880000 0x0 0x40000>; 514 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 516 phys = <&u2phy3_host>; 517 phy-names = "usb"; 518 power-domains = <&power RK3588_PD_USB>; 519 status = "disabled"; 520 }; 521 522 usb_host1_ohci: usb@fc8c0000 { 523 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 524 reg = <0x0 0xfc8c0000 0x0 0x40000>; 525 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 526 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 527 phys = <&u2phy3_host>; 528 phy-names = "usb"; 529 power-domains = <&power RK3588_PD_USB>; 530 status = "disabled"; 531 }; 532 533 usb_host2_xhci: usb@fcd00000 { 534 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 535 reg = <0x0 0xfcd00000 0x0 0x400000>; 536 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 537 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 538 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 539 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 540 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 541 dr_mode = "host"; 542 phys = <&combphy2_psu PHY_TYPE_USB3>; 543 phy-names = "usb3-phy"; 544 phy_type = "utmi_wide"; 545 resets = <&cru SRST_A_USB3OTG2>; 546 snps,dis_enblslpm_quirk; 547 snps,dis-u2-freeclk-exists-quirk; 548 snps,dis-del-phy-power-chg-quirk; 549 snps,dis-tx-ipgap-linecheck-quirk; 550 snps,dis_rxdet_inp3_quirk; 551 status = "disabled"; 552 }; 553 554 mmu600_pcie: iommu@fc900000 { 555 compatible = "arm,smmu-v3"; 556 reg = <0x0 0xfc900000 0x0 0x200000>; 557 interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>, 558 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>, 559 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>, 560 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>; 561 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 562 #iommu-cells = <1>; 563 }; 564 565 mmu600_php: iommu@fcb00000 { 566 compatible = "arm,smmu-v3"; 567 reg = <0x0 0xfcb00000 0x0 0x200000>; 568 interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>, 569 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>, 570 <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>, 571 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>; 572 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 573 #iommu-cells = <1>; 574 status = "disabled"; 575 }; 576 577 pmu1grf: syscon@fd58a000 { 578 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 579 reg = <0x0 0xfd58a000 0x0 0x10000>; 580 }; 581 582 sys_grf: syscon@fd58c000 { 583 compatible = "rockchip,rk3588-sys-grf", "syscon"; 584 reg = <0x0 0xfd58c000 0x0 0x1000>; 585 }; 586 587 mipidcphy0_grf: syscon@fd5e8000 { 588 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 589 reg = <0x0 0xfd5e8000 0x0 0x4000>; 590 }; 591 592 mipidcphy1_grf: syscon@fd5ec000 { 593 compatible = "rockchip,rk3588-dcphy-grf", "syscon"; 594 reg = <0x0 0xfd5ec000 0x0 0x4000>; 595 }; 596 597 vop_grf: syscon@fd5a4000 { 598 compatible = "rockchip,rk3588-vop-grf", "syscon"; 599 reg = <0x0 0xfd5a4000 0x0 0x2000>; 600 }; 601 602 vo0_grf: syscon@fd5a6000 { 603 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 604 reg = <0x0 0xfd5a6000 0x0 0x2000>; 605 clocks = <&cru PCLK_VO0GRF>; 606 }; 607 608 vo1_grf: syscon@fd5a8000 { 609 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 610 reg = <0x0 0xfd5a8000 0x0 0x4000>; 611 clocks = <&cru PCLK_VO1GRF>; 612 }; 613 614 usb_grf: syscon@fd5ac000 { 615 compatible = "rockchip,rk3588-usb-grf", "syscon"; 616 reg = <0x0 0xfd5ac000 0x0 0x4000>; 617 }; 618 619 php_grf: syscon@fd5b0000 { 620 compatible = "rockchip,rk3588-php-grf", "syscon"; 621 reg = <0x0 0xfd5b0000 0x0 0x1000>; 622 }; 623 624 csidphy0_grf: syscon@fd5b4000 { 625 compatible = "rockchip,rk3588-csidphy-grf", "syscon"; 626 reg = <0x0 0xfd5b4000 0x0 0x1000>; 627 }; 628 629 csidphy1_grf: syscon@fd5b5000 { 630 compatible = "rockchip,rk3588-csidphy-grf", "syscon"; 631 reg = <0x0 0xfd5b5000 0x0 0x1000>; 632 }; 633 634 pipe_phy0_grf: syscon@fd5bc000 { 635 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 636 reg = <0x0 0xfd5bc000 0x0 0x100>; 637 }; 638 639 pipe_phy2_grf: syscon@fd5c4000 { 640 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 641 reg = <0x0 0xfd5c4000 0x0 0x100>; 642 }; 643 644 usbdpphy0_grf: syscon@fd5c8000 { 645 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 646 reg = <0x0 0xfd5c8000 0x0 0x4000>; 647 }; 648 649 usb2phy0_grf: syscon@fd5d0000 { 650 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 651 reg = <0x0 0xfd5d0000 0x0 0x4000>; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 655 u2phy0: usb2phy@0 { 656 compatible = "rockchip,rk3588-usb2phy"; 657 reg = <0x0 0x10>; 658 #clock-cells = <0>; 659 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 660 clock-names = "phyclk"; 661 clock-output-names = "usb480m_phy0"; 662 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 663 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 664 reset-names = "phy", "apb"; 665 status = "disabled"; 666 667 u2phy0_otg: otg-port { 668 #phy-cells = <0>; 669 status = "disabled"; 670 }; 671 }; 672 }; 673 674 usb2phy2_grf: syscon@fd5d8000 { 675 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 676 reg = <0x0 0xfd5d8000 0x0 0x4000>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 680 u2phy2: usb2phy@8000 { 681 compatible = "rockchip,rk3588-usb2phy"; 682 reg = <0x8000 0x10>; 683 #clock-cells = <0>; 684 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 685 clock-names = "phyclk"; 686 clock-output-names = "usb480m_phy2"; 687 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 688 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 689 reset-names = "phy", "apb"; 690 status = "disabled"; 691 692 u2phy2_host: host-port { 693 #phy-cells = <0>; 694 status = "disabled"; 695 }; 696 }; 697 }; 698 699 usb2phy3_grf: syscon@fd5dc000 { 700 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 701 reg = <0x0 0xfd5dc000 0x0 0x4000>; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 705 u2phy3: usb2phy@c000 { 706 compatible = "rockchip,rk3588-usb2phy"; 707 reg = <0xc000 0x10>; 708 #clock-cells = <0>; 709 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 710 clock-names = "phyclk"; 711 clock-output-names = "usb480m_phy3"; 712 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 713 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 714 reset-names = "phy", "apb"; 715 status = "disabled"; 716 717 u2phy3_host: host-port { 718 #phy-cells = <0>; 719 status = "disabled"; 720 }; 721 }; 722 }; 723 724 hdptxphy0_grf: syscon@fd5e0000 { 725 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 726 reg = <0x0 0xfd5e0000 0x0 0x100>; 727 }; 728 729 ioc: syscon@fd5f0000 { 730 compatible = "rockchip,rk3588-ioc", "syscon"; 731 reg = <0x0 0xfd5f0000 0x0 0x10000>; 732 }; 733 734 system_sram1: sram@fd600000 { 735 compatible = "mmio-sram"; 736 reg = <0x0 0xfd600000 0x0 0x100000>; 737 ranges = <0x0 0x0 0xfd600000 0x100000>; 738 #address-cells = <1>; 739 #size-cells = <1>; 740 }; 741 742 cru: clock-controller@fd7c0000 { 743 compatible = "rockchip,rk3588-cru"; 744 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 745 assigned-clocks = 746 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 747 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 748 <&cru ACLK_CENTER_ROOT>, 749 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 750 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 751 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 752 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 753 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 754 <&cru CLK_GPU>; 755 assigned-clock-rates = 756 <1100000000>, <786432000>, 757 <850000000>, <1188000000>, 758 <702000000>, 759 <400000000>, <500000000>, 760 <800000000>, <100000000>, 761 <400000000>, <100000000>, 762 <200000000>, <500000000>, 763 <375000000>, <150000000>, 764 <200000000>; 765 rockchip,grf = <&php_grf>; 766 #clock-cells = <1>; 767 #reset-cells = <1>; 768 }; 769 770 i2c0: i2c@fd880000 { 771 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 772 reg = <0x0 0xfd880000 0x0 0x1000>; 773 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 774 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 775 clock-names = "i2c", "pclk"; 776 pinctrl-0 = <&i2c0m0_xfer>; 777 pinctrl-names = "default"; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 uart0: serial@fd890000 { 784 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 785 reg = <0x0 0xfd890000 0x0 0x100>; 786 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 787 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 788 clock-names = "baudclk", "apb_pclk"; 789 dmas = <&dmac0 6>, <&dmac0 7>; 790 dma-names = "tx", "rx"; 791 pinctrl-0 = <&uart0m1_xfer>; 792 pinctrl-names = "default"; 793 reg-shift = <2>; 794 reg-io-width = <4>; 795 status = "disabled"; 796 }; 797 798 pwm0: pwm@fd8b0000 { 799 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 800 reg = <0x0 0xfd8b0000 0x0 0x10>; 801 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 802 clock-names = "pwm", "pclk"; 803 pinctrl-0 = <&pwm0m0_pins>; 804 pinctrl-names = "default"; 805 #pwm-cells = <3>; 806 status = "disabled"; 807 }; 808 809 pwm1: pwm@fd8b0010 { 810 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 811 reg = <0x0 0xfd8b0010 0x0 0x10>; 812 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 813 clock-names = "pwm", "pclk"; 814 pinctrl-0 = <&pwm1m0_pins>; 815 pinctrl-names = "default"; 816 #pwm-cells = <3>; 817 status = "disabled"; 818 }; 819 820 pwm2: pwm@fd8b0020 { 821 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 822 reg = <0x0 0xfd8b0020 0x0 0x10>; 823 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 824 clock-names = "pwm", "pclk"; 825 pinctrl-0 = <&pwm2m0_pins>; 826 pinctrl-names = "default"; 827 #pwm-cells = <3>; 828 status = "disabled"; 829 }; 830 831 pwm3: pwm@fd8b0030 { 832 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 833 reg = <0x0 0xfd8b0030 0x0 0x10>; 834 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 835 clock-names = "pwm", "pclk"; 836 pinctrl-0 = <&pwm3m0_pins>; 837 pinctrl-names = "default"; 838 #pwm-cells = <3>; 839 status = "disabled"; 840 }; 841 842 pmu: power-management@fd8d8000 { 843 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 844 reg = <0x0 0xfd8d8000 0x0 0x400>; 845 846 power: power-controller { 847 compatible = "rockchip,rk3588-power-controller"; 848 #address-cells = <1>; 849 #power-domain-cells = <1>; 850 #size-cells = <0>; 851 status = "okay"; 852 853 /* These power domains are grouped by VD_NPU */ 854 pd_npu: power-domain@RK3588_PD_NPU { 855 reg = <RK3588_PD_NPU>; 856 #power-domain-cells = <0>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 860 power-domain@RK3588_PD_NPUTOP { 861 reg = <RK3588_PD_NPUTOP>; 862 clocks = <&cru HCLK_NPU_ROOT>, 863 <&cru PCLK_NPU_ROOT>, 864 <&cru CLK_NPU_DSU0>, 865 <&cru HCLK_NPU_CM0_ROOT>; 866 pm_qos = <&qos_npu0_mwr>, 867 <&qos_npu0_mro>, 868 <&qos_mcu_npu>; 869 #power-domain-cells = <0>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 power-domain@RK3588_PD_NPU1 { 874 reg = <RK3588_PD_NPU1>; 875 clocks = <&cru HCLK_NPU_ROOT>, 876 <&cru PCLK_NPU_ROOT>, 877 <&cru CLK_NPU_DSU0>; 878 pm_qos = <&qos_npu1>; 879 #power-domain-cells = <0>; 880 }; 881 power-domain@RK3588_PD_NPU2 { 882 reg = <RK3588_PD_NPU2>; 883 clocks = <&cru HCLK_NPU_ROOT>, 884 <&cru PCLK_NPU_ROOT>, 885 <&cru CLK_NPU_DSU0>; 886 pm_qos = <&qos_npu2>; 887 #power-domain-cells = <0>; 888 }; 889 }; 890 }; 891 /* These power domains are grouped by VD_GPU */ 892 pd_gpu: power-domain@RK3588_PD_GPU { 893 reg = <RK3588_PD_GPU>; 894 clocks = <&cru CLK_GPU>, 895 <&cru CLK_GPU_COREGROUP>, 896 <&cru CLK_GPU_STACKS>; 897 pm_qos = <&qos_gpu_m0>, 898 <&qos_gpu_m1>, 899 <&qos_gpu_m2>, 900 <&qos_gpu_m3>; 901 #power-domain-cells = <0>; 902 }; 903 /* These power domains are grouped by VD_VCODEC */ 904 power-domain@RK3588_PD_VCODEC { 905 reg = <RK3588_PD_VCODEC>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 #power-domain-cells = <0>; 909 910 power-domain@RK3588_PD_RKVDEC0 { 911 reg = <RK3588_PD_RKVDEC0>; 912 clocks = <&cru HCLK_RKVDEC0>, 913 <&cru HCLK_VDPU_ROOT>, 914 <&cru ACLK_VDPU_ROOT>, 915 <&cru ACLK_RKVDEC0>, 916 <&cru ACLK_RKVDEC_CCU>; 917 pm_qos = <&qos_rkvdec0>; 918 #power-domain-cells = <0>; 919 }; 920 power-domain@RK3588_PD_RKVDEC1 { 921 reg = <RK3588_PD_RKVDEC1>; 922 clocks = <&cru HCLK_RKVDEC1>, 923 <&cru HCLK_VDPU_ROOT>, 924 <&cru ACLK_VDPU_ROOT>, 925 <&cru ACLK_RKVDEC1>; 926 pm_qos = <&qos_rkvdec1>; 927 #power-domain-cells = <0>; 928 }; 929 power-domain@RK3588_PD_VENC0 { 930 reg = <RK3588_PD_VENC0>; 931 clocks = <&cru HCLK_RKVENC0>, 932 <&cru ACLK_RKVENC0>; 933 pm_qos = <&qos_rkvenc0_m0ro>, 934 <&qos_rkvenc0_m1ro>, 935 <&qos_rkvenc0_m2wo>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 #power-domain-cells = <0>; 939 940 power-domain@RK3588_PD_VENC1 { 941 reg = <RK3588_PD_VENC1>; 942 clocks = <&cru HCLK_RKVENC1>, 943 <&cru HCLK_RKVENC0>, 944 <&cru ACLK_RKVENC0>, 945 <&cru ACLK_RKVENC1>; 946 pm_qos = <&qos_rkvenc1_m0ro>, 947 <&qos_rkvenc1_m1ro>, 948 <&qos_rkvenc1_m2wo>; 949 #power-domain-cells = <0>; 950 }; 951 }; 952 }; 953 /* These power domains are grouped by VD_LOGIC */ 954 power-domain@RK3588_PD_VDPU { 955 reg = <RK3588_PD_VDPU>; 956 clocks = <&cru HCLK_VDPU_ROOT>, 957 <&cru ACLK_VDPU_LOW_ROOT>, 958 <&cru ACLK_VDPU_ROOT>, 959 <&cru ACLK_JPEG_DECODER_ROOT>, 960 <&cru ACLK_IEP2P0>, 961 <&cru HCLK_IEP2P0>, 962 <&cru ACLK_JPEG_ENCODER0>, 963 <&cru HCLK_JPEG_ENCODER0>, 964 <&cru ACLK_JPEG_ENCODER1>, 965 <&cru HCLK_JPEG_ENCODER1>, 966 <&cru ACLK_JPEG_ENCODER2>, 967 <&cru HCLK_JPEG_ENCODER2>, 968 <&cru ACLK_JPEG_ENCODER3>, 969 <&cru HCLK_JPEG_ENCODER3>, 970 <&cru ACLK_JPEG_DECODER>, 971 <&cru HCLK_JPEG_DECODER>, 972 <&cru ACLK_RGA2>, 973 <&cru HCLK_RGA2>; 974 pm_qos = <&qos_iep>, 975 <&qos_jpeg_dec>, 976 <&qos_jpeg_enc0>, 977 <&qos_jpeg_enc1>, 978 <&qos_jpeg_enc2>, 979 <&qos_jpeg_enc3>, 980 <&qos_rga2_mro>, 981 <&qos_rga2_mwo>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 #power-domain-cells = <0>; 985 986 987 power-domain@RK3588_PD_AV1 { 988 reg = <RK3588_PD_AV1>; 989 clocks = <&cru PCLK_AV1>, 990 <&cru ACLK_AV1>, 991 <&cru HCLK_VDPU_ROOT>; 992 pm_qos = <&qos_av1>; 993 #power-domain-cells = <0>; 994 }; 995 power-domain@RK3588_PD_RKVDEC0 { 996 reg = <RK3588_PD_RKVDEC0>; 997 clocks = <&cru HCLK_RKVDEC0>, 998 <&cru HCLK_VDPU_ROOT>, 999 <&cru ACLK_VDPU_ROOT>, 1000 <&cru ACLK_RKVDEC0>; 1001 pm_qos = <&qos_rkvdec0>; 1002 #power-domain-cells = <0>; 1003 }; 1004 power-domain@RK3588_PD_RKVDEC1 { 1005 reg = <RK3588_PD_RKVDEC1>; 1006 clocks = <&cru HCLK_RKVDEC1>, 1007 <&cru HCLK_VDPU_ROOT>, 1008 <&cru ACLK_VDPU_ROOT>; 1009 pm_qos = <&qos_rkvdec1>; 1010 #power-domain-cells = <0>; 1011 }; 1012 power-domain@RK3588_PD_RGA30 { 1013 reg = <RK3588_PD_RGA30>; 1014 clocks = <&cru ACLK_RGA3_0>, 1015 <&cru HCLK_RGA3_0>; 1016 pm_qos = <&qos_rga3_0>; 1017 #power-domain-cells = <0>; 1018 }; 1019 }; 1020 power-domain@RK3588_PD_VOP { 1021 reg = <RK3588_PD_VOP>; 1022 clocks = <&cru PCLK_VOP_ROOT>, 1023 <&cru HCLK_VOP_ROOT>, 1024 <&cru ACLK_VOP>; 1025 pm_qos = <&qos_vop_m0>, 1026 <&qos_vop_m1>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 #power-domain-cells = <0>; 1030 1031 power-domain@RK3588_PD_VO0 { 1032 reg = <RK3588_PD_VO0>; 1033 clocks = <&cru PCLK_VO0_ROOT>, 1034 <&cru PCLK_VO0_S_ROOT>, 1035 <&cru HCLK_VO0_S_ROOT>, 1036 <&cru ACLK_VO0_ROOT>, 1037 <&cru HCLK_HDCP0>, 1038 <&cru ACLK_HDCP0>, 1039 <&cru HCLK_VOP_ROOT>; 1040 pm_qos = <&qos_hdcp0>; 1041 #power-domain-cells = <0>; 1042 }; 1043 }; 1044 power-domain@RK3588_PD_VO1 { 1045 reg = <RK3588_PD_VO1>; 1046 clocks = <&cru PCLK_VO1_ROOT>, 1047 <&cru PCLK_VO1_S_ROOT>, 1048 <&cru HCLK_VO1_S_ROOT>, 1049 <&cru HCLK_HDCP1>, 1050 <&cru ACLK_HDCP1>, 1051 <&cru ACLK_HDMIRX_ROOT>, 1052 <&cru HCLK_VO1USB_TOP_ROOT>; 1053 pm_qos = <&qos_hdcp1>, 1054 <&qos_hdmirx>; 1055 #power-domain-cells = <0>; 1056 }; 1057 power-domain@RK3588_PD_VI { 1058 reg = <RK3588_PD_VI>; 1059 clocks = <&cru HCLK_VI_ROOT>, 1060 <&cru PCLK_VI_ROOT>, 1061 <&cru HCLK_ISP0>, 1062 <&cru ACLK_ISP0>, 1063 <&cru HCLK_VICAP>, 1064 <&cru ACLK_VICAP>; 1065 pm_qos = <&qos_isp0_mro>, 1066 <&qos_isp0_mwo>, 1067 <&qos_vicap_m0>, 1068 <&qos_vicap_m1>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 #power-domain-cells = <0>; 1072 1073 power-domain@RK3588_PD_ISP1 { 1074 reg = <RK3588_PD_ISP1>; 1075 clocks = <&cru HCLK_ISP1>, 1076 <&cru ACLK_ISP1>, 1077 <&cru HCLK_VI_ROOT>, 1078 <&cru PCLK_VI_ROOT>; 1079 pm_qos = <&qos_isp1_mwo>, 1080 <&qos_isp1_mro>; 1081 #power-domain-cells = <0>; 1082 }; 1083 power-domain@RK3588_PD_FEC { 1084 reg = <RK3588_PD_FEC>; 1085 clocks = <&cru HCLK_FISHEYE0>, 1086 <&cru ACLK_FISHEYE0>, 1087 <&cru HCLK_FISHEYE1>, 1088 <&cru ACLK_FISHEYE1>, 1089 <&cru PCLK_VI_ROOT>; 1090 pm_qos = <&qos_fisheye0>, 1091 <&qos_fisheye1>; 1092 #power-domain-cells = <0>; 1093 }; 1094 }; 1095 power-domain@RK3588_PD_RGA31 { 1096 reg = <RK3588_PD_RGA31>; 1097 clocks = <&cru HCLK_RGA3_1>, 1098 <&cru ACLK_RGA3_1>; 1099 pm_qos = <&qos_rga3_1>; 1100 #power-domain-cells = <0>; 1101 }; 1102 power-domain@RK3588_PD_USB { 1103 reg = <RK3588_PD_USB>; 1104 clocks = <&cru PCLK_PHP_ROOT>, 1105 <&cru ACLK_USB_ROOT>, 1106 <&cru ACLK_USB>, 1107 <&cru HCLK_USB_ROOT>, 1108 <&cru HCLK_HOST0>, 1109 <&cru HCLK_HOST_ARB0>, 1110 <&cru HCLK_HOST1>, 1111 <&cru HCLK_HOST_ARB1>; 1112 pm_qos = <&qos_usb3_0>, 1113 <&qos_usb3_1>, 1114 <&qos_usb2host_0>, 1115 <&qos_usb2host_1>; 1116 #power-domain-cells = <0>; 1117 }; 1118 power-domain@RK3588_PD_GMAC { 1119 reg = <RK3588_PD_GMAC>; 1120 clocks = <&cru PCLK_PHP_ROOT>, 1121 <&cru ACLK_PCIE_ROOT>, 1122 <&cru ACLK_PHP_ROOT>; 1123 #power-domain-cells = <0>; 1124 }; 1125 power-domain@RK3588_PD_PCIE { 1126 reg = <RK3588_PD_PCIE>; 1127 clocks = <&cru PCLK_PHP_ROOT>, 1128 <&cru ACLK_PCIE_ROOT>, 1129 <&cru ACLK_PHP_ROOT>; 1130 #power-domain-cells = <0>; 1131 }; 1132 power-domain@RK3588_PD_SDIO { 1133 reg = <RK3588_PD_SDIO>; 1134 clocks = <&cru HCLK_SDIO>, 1135 <&cru HCLK_NVM_ROOT>; 1136 pm_qos = <&qos_sdio>; 1137 #power-domain-cells = <0>; 1138 }; 1139 power-domain@RK3588_PD_AUDIO { 1140 reg = <RK3588_PD_AUDIO>; 1141 clocks = <&cru HCLK_AUDIO_ROOT>, 1142 <&cru PCLK_AUDIO_ROOT>; 1143 #power-domain-cells = <0>; 1144 }; 1145 power-domain@RK3588_PD_SDMMC { 1146 reg = <RK3588_PD_SDMMC>; 1147 pm_qos = <&qos_sdmmc>; 1148 #power-domain-cells = <0>; 1149 }; 1150 }; 1151 }; 1152 1153 rknn_core_0: npu@fdab0000 { 1154 compatible = "rockchip,rk3588-rknn-core"; 1155 reg = <0x0 0xfdab0000 0x0 0x1000>, 1156 <0x0 0xfdab1000 0x0 0x1000>, 1157 <0x0 0xfdab3000 0x0 0x1000>; 1158 reg-names = "pc", "cna", "core"; 1159 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1160 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, 1161 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1162 clock-names = "aclk", "hclk", "npu", "pclk"; 1163 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1164 assigned-clock-rates = <200000000>; 1165 resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; 1166 reset-names = "srst_a", "srst_h"; 1167 power-domains = <&power RK3588_PD_NPUTOP>; 1168 iommus = <&rknn_mmu_0>; 1169 status = "disabled"; 1170 }; 1171 1172 rknn_mmu_0: iommu@fdab9000 { 1173 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1174 reg = <0x0 0xfdab9000 0x0 0x100>, 1175 <0x0 0xfdaba000 0x0 0x100>; 1176 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 1178 clock-names = "aclk", "iface"; 1179 #iommu-cells = <0>; 1180 power-domains = <&power RK3588_PD_NPUTOP>; 1181 status = "disabled"; 1182 }; 1183 1184 rknn_core_1: npu@fdac0000 { 1185 compatible = "rockchip,rk3588-rknn-core"; 1186 reg = <0x0 0xfdac0000 0x0 0x1000>, 1187 <0x0 0xfdac1000 0x0 0x1000>, 1188 <0x0 0xfdac3000 0x0 0x1000>; 1189 reg-names = "pc", "cna", "core"; 1190 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>, 1192 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1193 clock-names = "aclk", "hclk", "npu", "pclk"; 1194 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1195 assigned-clock-rates = <200000000>; 1196 resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; 1197 reset-names = "srst_a", "srst_h"; 1198 power-domains = <&power RK3588_PD_NPU1>; 1199 iommus = <&rknn_mmu_1>; 1200 status = "disabled"; 1201 }; 1202 1203 rknn_mmu_1: iommu@fdaca000 { 1204 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1205 reg = <0x0 0xfdaca000 0x0 0x100>; 1206 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1207 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 1208 clock-names = "aclk", "iface"; 1209 #iommu-cells = <0>; 1210 power-domains = <&power RK3588_PD_NPU1>; 1211 status = "disabled"; 1212 }; 1213 1214 rknn_core_2: npu@fdad0000 { 1215 compatible = "rockchip,rk3588-rknn-core"; 1216 reg = <0x0 0xfdad0000 0x0 0x1000>, 1217 <0x0 0xfdad1000 0x0 0x1000>, 1218 <0x0 0xfdad3000 0x0 0x1000>; 1219 reg-names = "pc", "cna", "core"; 1220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>, 1222 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; 1223 clock-names = "aclk", "hclk", "npu", "pclk"; 1224 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 1225 assigned-clock-rates = <200000000>; 1226 resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>; 1227 reset-names = "srst_a", "srst_h"; 1228 power-domains = <&power RK3588_PD_NPU2>; 1229 iommus = <&rknn_mmu_2>; 1230 status = "disabled"; 1231 }; 1232 1233 rknn_mmu_2: iommu@fdada000 { 1234 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1235 reg = <0x0 0xfdada000 0x0 0x100>; 1236 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1237 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 1238 clock-names = "aclk", "iface"; 1239 #iommu-cells = <0>; 1240 power-domains = <&power RK3588_PD_NPU2>; 1241 status = "disabled"; 1242 }; 1243 1244 vpu121: video-codec@fdb50000 { 1245 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1246 reg = <0x0 0xfdb50000 0x0 0x800>; 1247 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1248 interrupt-names = "vdpu"; 1249 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1250 clock-names = "aclk", "hclk"; 1251 iommus = <&vpu121_mmu>; 1252 power-domains = <&power RK3588_PD_VDPU>; 1253 }; 1254 1255 vpu121_mmu: iommu@fdb50800 { 1256 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1257 reg = <0x0 0xfdb50800 0x0 0x40>; 1258 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1259 clock-names = "aclk", "iface"; 1260 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1261 power-domains = <&power RK3588_PD_VDPU>; 1262 #iommu-cells = <0>; 1263 }; 1264 1265 rga: rga@fdb80000 { 1266 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1267 reg = <0x0 0xfdb80000 0x0 0x180>; 1268 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1269 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1270 clock-names = "aclk", "hclk", "sclk"; 1271 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1272 reset-names = "core", "axi", "ahb"; 1273 power-domains = <&power RK3588_PD_VDPU>; 1274 }; 1275 1276 vepu121_0: video-codec@fdba0000 { 1277 compatible = "rockchip,rk3588-vepu121"; 1278 reg = <0x0 0xfdba0000 0x0 0x800>; 1279 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1280 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1281 clock-names = "aclk", "hclk"; 1282 iommus = <&vepu121_0_mmu>; 1283 power-domains = <&power RK3588_PD_VDPU>; 1284 }; 1285 1286 vepu121_0_mmu: iommu@fdba0800 { 1287 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1288 reg = <0x0 0xfdba0800 0x0 0x40>; 1289 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1290 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1291 clock-names = "aclk", "iface"; 1292 power-domains = <&power RK3588_PD_VDPU>; 1293 #iommu-cells = <0>; 1294 }; 1295 1296 vepu121_1: video-codec@fdba4000 { 1297 compatible = "rockchip,rk3588-vepu121"; 1298 reg = <0x0 0xfdba4000 0x0 0x800>; 1299 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1300 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1301 clock-names = "aclk", "hclk"; 1302 iommus = <&vepu121_1_mmu>; 1303 power-domains = <&power RK3588_PD_VDPU>; 1304 }; 1305 1306 vepu121_1_mmu: iommu@fdba4800 { 1307 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1308 reg = <0x0 0xfdba4800 0x0 0x40>; 1309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1310 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1311 clock-names = "aclk", "iface"; 1312 power-domains = <&power RK3588_PD_VDPU>; 1313 #iommu-cells = <0>; 1314 }; 1315 1316 vepu121_2: video-codec@fdba8000 { 1317 compatible = "rockchip,rk3588-vepu121"; 1318 reg = <0x0 0xfdba8000 0x0 0x800>; 1319 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1320 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1321 clock-names = "aclk", "hclk"; 1322 iommus = <&vepu121_2_mmu>; 1323 power-domains = <&power RK3588_PD_VDPU>; 1324 }; 1325 1326 vepu121_2_mmu: iommu@fdba8800 { 1327 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1328 reg = <0x0 0xfdba8800 0x0 0x40>; 1329 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1330 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1331 clock-names = "aclk", "iface"; 1332 power-domains = <&power RK3588_PD_VDPU>; 1333 #iommu-cells = <0>; 1334 }; 1335 1336 vepu121_3: video-codec@fdbac000 { 1337 compatible = "rockchip,rk3588-vepu121"; 1338 reg = <0x0 0xfdbac000 0x0 0x800>; 1339 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1340 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1341 clock-names = "aclk", "hclk"; 1342 iommus = <&vepu121_3_mmu>; 1343 power-domains = <&power RK3588_PD_VDPU>; 1344 }; 1345 1346 vepu121_3_mmu: iommu@fdbac800 { 1347 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1348 reg = <0x0 0xfdbac800 0x0 0x40>; 1349 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1350 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1351 clock-names = "aclk", "iface"; 1352 power-domains = <&power RK3588_PD_VDPU>; 1353 #iommu-cells = <0>; 1354 }; 1355 1356 av1d: video-codec@fdc70000 { 1357 compatible = "rockchip,rk3588-av1-vpu"; 1358 reg = <0x0 0xfdc70000 0x0 0x800>; 1359 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1360 interrupt-names = "vdpu"; 1361 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1362 assigned-clock-rates = <400000000>, <400000000>; 1363 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1364 clock-names = "aclk", "hclk"; 1365 power-domains = <&power RK3588_PD_AV1>; 1366 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1367 }; 1368 1369 vop: vop@fdd90000 { 1370 compatible = "rockchip,rk3588-vop"; 1371 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1372 reg-names = "vop", "gamma-lut"; 1373 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1374 clocks = <&cru ACLK_VOP>, 1375 <&cru HCLK_VOP>, 1376 <&cru DCLK_VOP0>, 1377 <&cru DCLK_VOP1>, 1378 <&cru DCLK_VOP2>, 1379 <&cru DCLK_VOP3>, 1380 <&cru PCLK_VOP_ROOT>, 1381 <&hdptxphy0>; 1382 clock-names = "aclk", 1383 "hclk", 1384 "dclk_vp0", 1385 "dclk_vp1", 1386 "dclk_vp2", 1387 "dclk_vp3", 1388 "pclk_vop", 1389 "pll_hdmiphy0"; 1390 iommus = <&vop_mmu>; 1391 power-domains = <&power RK3588_PD_VOP>; 1392 rockchip,grf = <&sys_grf>; 1393 rockchip,vop-grf = <&vop_grf>; 1394 rockchip,vo1-grf = <&vo1_grf>; 1395 rockchip,pmu = <&pmu>; 1396 status = "disabled"; 1397 1398 vop_out: ports { 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 1402 vp0: port@0 { 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 reg = <0>; 1406 }; 1407 1408 vp1: port@1 { 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 reg = <1>; 1412 }; 1413 1414 vp2: port@2 { 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 reg = <2>; 1418 }; 1419 1420 vp3: port@3 { 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 reg = <3>; 1424 }; 1425 }; 1426 }; 1427 1428 vop_mmu: iommu@fdd97e00 { 1429 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1430 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1431 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1432 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1433 clock-names = "aclk", "iface"; 1434 #iommu-cells = <0>; 1435 power-domains = <&power RK3588_PD_VOP>; 1436 status = "disabled"; 1437 }; 1438 1439 spdif_tx2: spdif-tx@fddb0000 { 1440 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1441 reg = <0x0 0xfddb0000 0x0 0x1000>; 1442 assigned-clock-parents = <&cru PLL_AUPLL>; 1443 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 1444 clock-names = "mclk", "hclk"; 1445 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; 1446 dma-names = "tx"; 1447 dmas = <&dmac1 6>; 1448 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1449 power-domains = <&power RK3588_PD_VO0>; 1450 #sound-dai-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 i2s4_8ch: i2s@fddc0000 { 1455 compatible = "rockchip,rk3588-i2s-tdm"; 1456 reg = <0x0 0xfddc0000 0x0 0x1000>; 1457 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1458 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1459 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1460 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1461 assigned-clock-parents = <&cru PLL_AUPLL>; 1462 dmas = <&dmac2 0>; 1463 dma-names = "tx"; 1464 power-domains = <&power RK3588_PD_VO0>; 1465 resets = <&cru SRST_M_I2S4_8CH_TX>; 1466 reset-names = "tx-m"; 1467 #sound-dai-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spdif_tx3: spdif-tx@fdde0000 { 1472 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1473 reg = <0x0 0xfdde0000 0x0 0x1000>; 1474 assigned-clock-parents = <&cru PLL_AUPLL>; 1475 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 1476 clock-names = "mclk", "hclk"; 1477 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1478 dma-names = "tx"; 1479 dmas = <&dmac1 7>; 1480 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1481 power-domains = <&power RK3588_PD_VO1>; 1482 #sound-dai-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 i2s5_8ch: i2s@fddf0000 { 1487 compatible = "rockchip,rk3588-i2s-tdm"; 1488 reg = <0x0 0xfddf0000 0x0 0x1000>; 1489 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1490 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1491 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1492 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1493 assigned-clock-parents = <&cru PLL_AUPLL>; 1494 dmas = <&dmac2 2>; 1495 dma-names = "tx"; 1496 power-domains = <&power RK3588_PD_VO1>; 1497 resets = <&cru SRST_M_I2S5_8CH_TX>; 1498 reset-names = "tx-m"; 1499 #sound-dai-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 i2s9_8ch: i2s@fddfc000 { 1504 compatible = "rockchip,rk3588-i2s-tdm"; 1505 reg = <0x0 0xfddfc000 0x0 0x1000>; 1506 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1507 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1508 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1509 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1510 assigned-clock-parents = <&cru PLL_AUPLL>; 1511 dmas = <&dmac2 23>; 1512 dma-names = "rx"; 1513 power-domains = <&power RK3588_PD_VO1>; 1514 resets = <&cru SRST_M_I2S9_8CH_RX>; 1515 reset-names = "rx-m"; 1516 #sound-dai-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 1520 dsi0: dsi@fde20000 { 1521 compatible = "rockchip,rk3588-mipi-dsi2"; 1522 reg = <0x0 0xfde20000 0x0 0x10000>; 1523 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; 1524 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1525 clock-names = "pclk", "sys"; 1526 resets = <&cru SRST_P_DSIHOST0>; 1527 reset-names = "apb"; 1528 power-domains = <&power RK3588_PD_VOP>; 1529 phys = <&mipidcphy0 PHY_TYPE_DPHY>; 1530 phy-names = "dcphy"; 1531 rockchip,grf = <&vop_grf>; 1532 status = "disabled"; 1533 1534 ports { 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 1538 dsi0_in: port@0 { 1539 reg = <0>; 1540 }; 1541 1542 dsi0_out: port@1 { 1543 reg = <1>; 1544 }; 1545 }; 1546 }; 1547 1548 dsi1: dsi@fde30000 { 1549 compatible = "rockchip,rk3588-mipi-dsi2"; 1550 reg = <0x0 0xfde30000 0x0 0x10000>; 1551 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; 1552 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; 1553 clock-names = "pclk", "sys"; 1554 resets = <&cru SRST_P_DSIHOST1>; 1555 reset-names = "apb"; 1556 power-domains = <&power RK3588_PD_VOP>; 1557 phys = <&mipidcphy1 PHY_TYPE_DPHY>; 1558 phy-names = "dcphy"; 1559 rockchip,grf = <&vop_grf>; 1560 status = "disabled"; 1561 1562 ports { 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 1566 dsi1_in: port@0 { 1567 reg = <0>; 1568 }; 1569 1570 dsi1_out: port@1 { 1571 reg = <1>; 1572 }; 1573 }; 1574 }; 1575 1576 dp0: dp@fde50000 { 1577 compatible = "rockchip,rk3588-dp"; 1578 reg = <0x0 0xfde50000 0x0 0x4000>; 1579 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 1580 assigned-clocks = <&cru CLK_AUX16M_0>; 1581 assigned-clock-rates = <16000000>; 1582 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, 1583 <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, 1584 <&cru MCLK_SPDIF2_DP0>; 1585 clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; 1586 phys = <&usbdp_phy0 PHY_TYPE_DP>; 1587 power-domains = <&power RK3588_PD_VO0>; 1588 resets = <&cru SRST_DP0>; 1589 #sound-dai-cells = <0>; 1590 status = "disabled"; 1591 1592 ports { 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 1596 dp0_in: port@0 { 1597 reg = <0>; 1598 }; 1599 1600 dp0_out: port@1 { 1601 reg = <1>; 1602 }; 1603 }; 1604 }; 1605 1606 hdmi0: hdmi@fde80000 { 1607 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1608 reg = <0x0 0xfde80000 0x0 0x20000>; 1609 clocks = <&cru PCLK_HDMITX0>, 1610 <&cru CLK_HDMITX0_EARC>, 1611 <&cru CLK_HDMITX0_REF>, 1612 <&cru MCLK_I2S5_8CH_TX>, 1613 <&cru CLK_HDMIHDP0>, 1614 <&cru HCLK_VO1>; 1615 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1616 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1618 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1619 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1620 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1621 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1622 phys = <&hdptxphy0>; 1623 pinctrl-names = "default"; 1624 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1625 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1626 power-domains = <&power RK3588_PD_VO1>; 1627 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1628 reset-names = "ref", "hdp"; 1629 rockchip,grf = <&sys_grf>; 1630 rockchip,vo-grf = <&vo1_grf>; 1631 #sound-dai-cells = <0>; 1632 status = "disabled"; 1633 1634 ports { 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 hdmi0_in: port@0 { 1639 reg = <0>; 1640 }; 1641 1642 hdmi0_out: port@1 { 1643 reg = <1>; 1644 }; 1645 }; 1646 }; 1647 1648 edp0: edp@fdec0000 { 1649 compatible = "rockchip,rk3588-edp"; 1650 reg = <0x0 0xfdec0000 0x0 0x1000>; 1651 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; 1652 clock-names = "dp", "pclk"; 1653 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 1654 phys = <&hdptxphy0>; 1655 phy-names = "dp"; 1656 power-domains = <&power RK3588_PD_VO1>; 1657 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1658 reset-names = "dp", "apb"; 1659 rockchip,grf = <&vo1_grf>; 1660 status = "disabled"; 1661 1662 ports { 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 1666 edp0_in: port@0 { 1667 reg = <0>; 1668 }; 1669 1670 edp0_out: port@1 { 1671 reg = <1>; 1672 }; 1673 }; 1674 }; 1675 1676 qos_gpu_m0: qos@fdf35000 { 1677 compatible = "rockchip,rk3588-qos", "syscon"; 1678 reg = <0x0 0xfdf35000 0x0 0x20>; 1679 }; 1680 1681 qos_gpu_m1: qos@fdf35200 { 1682 compatible = "rockchip,rk3588-qos", "syscon"; 1683 reg = <0x0 0xfdf35200 0x0 0x20>; 1684 }; 1685 1686 qos_gpu_m2: qos@fdf35400 { 1687 compatible = "rockchip,rk3588-qos", "syscon"; 1688 reg = <0x0 0xfdf35400 0x0 0x20>; 1689 }; 1690 1691 qos_gpu_m3: qos@fdf35600 { 1692 compatible = "rockchip,rk3588-qos", "syscon"; 1693 reg = <0x0 0xfdf35600 0x0 0x20>; 1694 }; 1695 1696 qos_rga3_1: qos@fdf36000 { 1697 compatible = "rockchip,rk3588-qos", "syscon"; 1698 reg = <0x0 0xfdf36000 0x0 0x20>; 1699 }; 1700 1701 qos_sdio: qos@fdf39000 { 1702 compatible = "rockchip,rk3588-qos", "syscon"; 1703 reg = <0x0 0xfdf39000 0x0 0x20>; 1704 }; 1705 1706 qos_sdmmc: qos@fdf3d800 { 1707 compatible = "rockchip,rk3588-qos", "syscon"; 1708 reg = <0x0 0xfdf3d800 0x0 0x20>; 1709 }; 1710 1711 qos_usb3_1: qos@fdf3e000 { 1712 compatible = "rockchip,rk3588-qos", "syscon"; 1713 reg = <0x0 0xfdf3e000 0x0 0x20>; 1714 }; 1715 1716 qos_usb3_0: qos@fdf3e200 { 1717 compatible = "rockchip,rk3588-qos", "syscon"; 1718 reg = <0x0 0xfdf3e200 0x0 0x20>; 1719 }; 1720 1721 qos_usb2host_0: qos@fdf3e400 { 1722 compatible = "rockchip,rk3588-qos", "syscon"; 1723 reg = <0x0 0xfdf3e400 0x0 0x20>; 1724 }; 1725 1726 qos_usb2host_1: qos@fdf3e600 { 1727 compatible = "rockchip,rk3588-qos", "syscon"; 1728 reg = <0x0 0xfdf3e600 0x0 0x20>; 1729 }; 1730 1731 qos_fisheye0: qos@fdf40000 { 1732 compatible = "rockchip,rk3588-qos", "syscon"; 1733 reg = <0x0 0xfdf40000 0x0 0x20>; 1734 }; 1735 1736 qos_fisheye1: qos@fdf40200 { 1737 compatible = "rockchip,rk3588-qos", "syscon"; 1738 reg = <0x0 0xfdf40200 0x0 0x20>; 1739 }; 1740 1741 qos_isp0_mro: qos@fdf40400 { 1742 compatible = "rockchip,rk3588-qos", "syscon"; 1743 reg = <0x0 0xfdf40400 0x0 0x20>; 1744 }; 1745 1746 qos_isp0_mwo: qos@fdf40500 { 1747 compatible = "rockchip,rk3588-qos", "syscon"; 1748 reg = <0x0 0xfdf40500 0x0 0x20>; 1749 }; 1750 1751 qos_vicap_m0: qos@fdf40600 { 1752 compatible = "rockchip,rk3588-qos", "syscon"; 1753 reg = <0x0 0xfdf40600 0x0 0x20>; 1754 }; 1755 1756 qos_vicap_m1: qos@fdf40800 { 1757 compatible = "rockchip,rk3588-qos", "syscon"; 1758 reg = <0x0 0xfdf40800 0x0 0x20>; 1759 }; 1760 1761 qos_isp1_mwo: qos@fdf41000 { 1762 compatible = "rockchip,rk3588-qos", "syscon"; 1763 reg = <0x0 0xfdf41000 0x0 0x20>; 1764 }; 1765 1766 qos_isp1_mro: qos@fdf41100 { 1767 compatible = "rockchip,rk3588-qos", "syscon"; 1768 reg = <0x0 0xfdf41100 0x0 0x20>; 1769 }; 1770 1771 qos_rkvenc0_m0ro: qos@fdf60000 { 1772 compatible = "rockchip,rk3588-qos", "syscon"; 1773 reg = <0x0 0xfdf60000 0x0 0x20>; 1774 }; 1775 1776 qos_rkvenc0_m1ro: qos@fdf60200 { 1777 compatible = "rockchip,rk3588-qos", "syscon"; 1778 reg = <0x0 0xfdf60200 0x0 0x20>; 1779 }; 1780 1781 qos_rkvenc0_m2wo: qos@fdf60400 { 1782 compatible = "rockchip,rk3588-qos", "syscon"; 1783 reg = <0x0 0xfdf60400 0x0 0x20>; 1784 }; 1785 1786 qos_rkvenc1_m0ro: qos@fdf61000 { 1787 compatible = "rockchip,rk3588-qos", "syscon"; 1788 reg = <0x0 0xfdf61000 0x0 0x20>; 1789 }; 1790 1791 qos_rkvenc1_m1ro: qos@fdf61200 { 1792 compatible = "rockchip,rk3588-qos", "syscon"; 1793 reg = <0x0 0xfdf61200 0x0 0x20>; 1794 }; 1795 1796 qos_rkvenc1_m2wo: qos@fdf61400 { 1797 compatible = "rockchip,rk3588-qos", "syscon"; 1798 reg = <0x0 0xfdf61400 0x0 0x20>; 1799 }; 1800 1801 qos_rkvdec0: qos@fdf62000 { 1802 compatible = "rockchip,rk3588-qos", "syscon"; 1803 reg = <0x0 0xfdf62000 0x0 0x20>; 1804 }; 1805 1806 qos_rkvdec1: qos@fdf63000 { 1807 compatible = "rockchip,rk3588-qos", "syscon"; 1808 reg = <0x0 0xfdf63000 0x0 0x20>; 1809 }; 1810 1811 qos_av1: qos@fdf64000 { 1812 compatible = "rockchip,rk3588-qos", "syscon"; 1813 reg = <0x0 0xfdf64000 0x0 0x20>; 1814 }; 1815 1816 qos_iep: qos@fdf66000 { 1817 compatible = "rockchip,rk3588-qos", "syscon"; 1818 reg = <0x0 0xfdf66000 0x0 0x20>; 1819 }; 1820 1821 qos_jpeg_dec: qos@fdf66200 { 1822 compatible = "rockchip,rk3588-qos", "syscon"; 1823 reg = <0x0 0xfdf66200 0x0 0x20>; 1824 }; 1825 1826 qos_jpeg_enc0: qos@fdf66400 { 1827 compatible = "rockchip,rk3588-qos", "syscon"; 1828 reg = <0x0 0xfdf66400 0x0 0x20>; 1829 }; 1830 1831 qos_jpeg_enc1: qos@fdf66600 { 1832 compatible = "rockchip,rk3588-qos", "syscon"; 1833 reg = <0x0 0xfdf66600 0x0 0x20>; 1834 }; 1835 1836 qos_jpeg_enc2: qos@fdf66800 { 1837 compatible = "rockchip,rk3588-qos", "syscon"; 1838 reg = <0x0 0xfdf66800 0x0 0x20>; 1839 }; 1840 1841 qos_jpeg_enc3: qos@fdf66a00 { 1842 compatible = "rockchip,rk3588-qos", "syscon"; 1843 reg = <0x0 0xfdf66a00 0x0 0x20>; 1844 }; 1845 1846 qos_rga2_mro: qos@fdf66c00 { 1847 compatible = "rockchip,rk3588-qos", "syscon"; 1848 reg = <0x0 0xfdf66c00 0x0 0x20>; 1849 }; 1850 1851 qos_rga2_mwo: qos@fdf66e00 { 1852 compatible = "rockchip,rk3588-qos", "syscon"; 1853 reg = <0x0 0xfdf66e00 0x0 0x20>; 1854 }; 1855 1856 qos_rga3_0: qos@fdf67000 { 1857 compatible = "rockchip,rk3588-qos", "syscon"; 1858 reg = <0x0 0xfdf67000 0x0 0x20>; 1859 }; 1860 1861 qos_vdpu: qos@fdf67200 { 1862 compatible = "rockchip,rk3588-qos", "syscon"; 1863 reg = <0x0 0xfdf67200 0x0 0x20>; 1864 }; 1865 1866 qos_npu1: qos@fdf70000 { 1867 compatible = "rockchip,rk3588-qos", "syscon"; 1868 reg = <0x0 0xfdf70000 0x0 0x20>; 1869 }; 1870 1871 qos_npu2: qos@fdf71000 { 1872 compatible = "rockchip,rk3588-qos", "syscon"; 1873 reg = <0x0 0xfdf71000 0x0 0x20>; 1874 }; 1875 1876 qos_npu0_mwr: qos@fdf72000 { 1877 compatible = "rockchip,rk3588-qos", "syscon"; 1878 reg = <0x0 0xfdf72000 0x0 0x20>; 1879 }; 1880 1881 qos_npu0_mro: qos@fdf72200 { 1882 compatible = "rockchip,rk3588-qos", "syscon"; 1883 reg = <0x0 0xfdf72200 0x0 0x20>; 1884 }; 1885 1886 qos_mcu_npu: qos@fdf72400 { 1887 compatible = "rockchip,rk3588-qos", "syscon"; 1888 reg = <0x0 0xfdf72400 0x0 0x20>; 1889 }; 1890 1891 qos_hdcp0: qos@fdf80000 { 1892 compatible = "rockchip,rk3588-qos", "syscon"; 1893 reg = <0x0 0xfdf80000 0x0 0x20>; 1894 }; 1895 1896 qos_hdcp1: qos@fdf81000 { 1897 compatible = "rockchip,rk3588-qos", "syscon"; 1898 reg = <0x0 0xfdf81000 0x0 0x20>; 1899 }; 1900 1901 qos_hdmirx: qos@fdf81200 { 1902 compatible = "rockchip,rk3588-qos", "syscon"; 1903 reg = <0x0 0xfdf81200 0x0 0x20>; 1904 }; 1905 1906 qos_vop_m0: qos@fdf82000 { 1907 compatible = "rockchip,rk3588-qos", "syscon"; 1908 reg = <0x0 0xfdf82000 0x0 0x20>; 1909 }; 1910 1911 qos_vop_m1: qos@fdf82200 { 1912 compatible = "rockchip,rk3588-qos", "syscon"; 1913 reg = <0x0 0xfdf82200 0x0 0x20>; 1914 }; 1915 1916 dfi: dfi@fe060000 { 1917 reg = <0x00 0xfe060000 0x00 0x10000>; 1918 compatible = "rockchip,rk3588-dfi"; 1919 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1920 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1921 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1922 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1923 rockchip,pmu = <&pmu1grf>; 1924 }; 1925 1926 pcie2x1l1: pcie@fe180000 { 1927 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1928 bus-range = <0x30 0x3f>; 1929 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1930 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1931 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1932 clock-names = "aclk_mst", "aclk_slv", 1933 "aclk_dbi", "pclk", 1934 "aux", "pipe"; 1935 device_type = "pci"; 1936 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1937 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1938 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1939 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1940 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1941 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1942 #interrupt-cells = <1>; 1943 interrupt-map-mask = <0 0 0 7>; 1944 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1945 <0 0 0 2 &pcie2x1l1_intc 1>, 1946 <0 0 0 3 &pcie2x1l1_intc 2>, 1947 <0 0 0 4 &pcie2x1l1_intc 3>; 1948 linux,pci-domain = <3>; 1949 max-link-speed = <2>; 1950 msi-map = <0x3000 &its0 0x3000 0x1000>; 1951 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>; 1952 num-lanes = <1>; 1953 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1954 phy-names = "pcie-phy"; 1955 power-domains = <&power RK3588_PD_PCIE>; 1956 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1957 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1958 <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 1959 reg = <0xa 0x40c00000 0x0 0x00400000>, 1960 <0x0 0xfe180000 0x0 0x00010000>, 1961 <0x0 0xf3000000 0x0 0x00100000>; 1962 reg-names = "dbi", "apb", "config"; 1963 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1964 reset-names = "pwr", "pipe"; 1965 #address-cells = <3>; 1966 #size-cells = <2>; 1967 status = "disabled"; 1968 1969 pcie2x1l1_intc: legacy-interrupt-controller { 1970 interrupt-controller; 1971 #address-cells = <0>; 1972 #interrupt-cells = <1>; 1973 interrupt-parent = <&gic>; 1974 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1975 }; 1976 }; 1977 1978 pcie2x1l2: pcie@fe190000 { 1979 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1980 bus-range = <0x40 0x4f>; 1981 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1982 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1983 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1984 clock-names = "aclk_mst", "aclk_slv", 1985 "aclk_dbi", "pclk", 1986 "aux", "pipe"; 1987 device_type = "pci"; 1988 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1989 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1990 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1991 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1992 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1993 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1994 #interrupt-cells = <1>; 1995 interrupt-map-mask = <0 0 0 7>; 1996 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1997 <0 0 0 2 &pcie2x1l2_intc 1>, 1998 <0 0 0 3 &pcie2x1l2_intc 2>, 1999 <0 0 0 4 &pcie2x1l2_intc 3>; 2000 linux,pci-domain = <4>; 2001 max-link-speed = <2>; 2002 msi-map = <0x4000 &its0 0x4000 0x1000>; 2003 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>; 2004 num-lanes = <1>; 2005 phys = <&combphy0_ps PHY_TYPE_PCIE>; 2006 phy-names = "pcie-phy"; 2007 power-domains = <&power RK3588_PD_PCIE>; 2008 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 2009 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 2010 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 2011 reg = <0xa 0x41000000 0x0 0x00400000>, 2012 <0x0 0xfe190000 0x0 0x00010000>, 2013 <0x0 0xf4000000 0x0 0x00100000>; 2014 reg-names = "dbi", "apb", "config"; 2015 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 2016 reset-names = "pwr", "pipe"; 2017 #address-cells = <3>; 2018 #size-cells = <2>; 2019 status = "disabled"; 2020 2021 pcie2x1l2_intc: legacy-interrupt-controller { 2022 interrupt-controller; 2023 #address-cells = <0>; 2024 #interrupt-cells = <1>; 2025 interrupt-parent = <&gic>; 2026 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 2027 }; 2028 }; 2029 2030 gmac1: ethernet@fe1c0000 { 2031 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 2032 reg = <0x0 0xfe1c0000 0x0 0x10000>; 2033 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 2034 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 2035 interrupt-names = "macirq", "eth_wake_irq"; 2036 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 2037 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 2038 <&cru CLK_GMAC1_PTP_REF>; 2039 clock-names = "stmmaceth", "clk_mac_ref", 2040 "pclk_mac", "aclk_mac", 2041 "ptp_ref"; 2042 power-domains = <&power RK3588_PD_GMAC>; 2043 resets = <&cru SRST_A_GMAC1>; 2044 reset-names = "stmmaceth"; 2045 rockchip,grf = <&sys_grf>; 2046 rockchip,php-grf = <&php_grf>; 2047 snps,axi-config = <&gmac1_stmmac_axi_setup>; 2048 snps,mixed-burst; 2049 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 2050 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 2051 snps,tso; 2052 status = "disabled"; 2053 2054 mdio1: mdio { 2055 compatible = "snps,dwmac-mdio"; 2056 #address-cells = <0x1>; 2057 #size-cells = <0x0>; 2058 }; 2059 2060 gmac1_stmmac_axi_setup: stmmac-axi-config { 2061 snps,blen = <0 0 0 0 16 8 4>; 2062 snps,wr_osr_lmt = <4>; 2063 snps,rd_osr_lmt = <8>; 2064 }; 2065 2066 gmac1_mtl_rx_setup: rx-queues-config { 2067 snps,rx-queues-to-use = <2>; 2068 queue0 {}; 2069 queue1 {}; 2070 }; 2071 2072 gmac1_mtl_tx_setup: tx-queues-config { 2073 snps,tx-queues-to-use = <2>; 2074 queue0 {}; 2075 queue1 {}; 2076 }; 2077 }; 2078 2079 sata0: sata@fe210000 { 2080 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 2081 reg = <0 0xfe210000 0 0x1000>; 2082 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 2083 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 2084 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 2085 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 2086 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 2087 ports-implemented = <0x1>; 2088 #address-cells = <1>; 2089 #size-cells = <0>; 2090 status = "disabled"; 2091 2092 sata-port@0 { 2093 reg = <0>; 2094 hba-port-cap = <HBA_PORT_FBSCP>; 2095 phys = <&combphy0_ps PHY_TYPE_SATA>; 2096 phy-names = "sata-phy"; 2097 snps,rx-ts-max = <32>; 2098 snps,tx-ts-max = <32>; 2099 }; 2100 }; 2101 2102 sata2: sata@fe230000 { 2103 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 2104 reg = <0 0xfe230000 0 0x1000>; 2105 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 2106 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 2107 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 2108 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 2109 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 2110 ports-implemented = <0x1>; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 status = "disabled"; 2114 2115 sata-port@0 { 2116 reg = <0>; 2117 hba-port-cap = <HBA_PORT_FBSCP>; 2118 phys = <&combphy2_psu PHY_TYPE_SATA>; 2119 phy-names = "sata-phy"; 2120 snps,rx-ts-max = <32>; 2121 snps,tx-ts-max = <32>; 2122 }; 2123 }; 2124 2125 sfc: spi@fe2b0000 { 2126 compatible = "rockchip,sfc"; 2127 reg = <0x0 0xfe2b0000 0x0 0x4000>; 2128 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 2129 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2130 clock-names = "clk_sfc", "hclk_sfc"; 2131 #address-cells = <1>; 2132 #size-cells = <0>; 2133 status = "disabled"; 2134 }; 2135 2136 sdmmc: mmc@fe2c0000 { 2137 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2138 reg = <0x0 0xfe2c0000 0x0 0x4000>; 2139 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 2140 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 2141 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 2142 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2143 fifo-depth = <0x100>; 2144 max-frequency = <200000000>; 2145 pinctrl-names = "default"; 2146 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 2147 power-domains = <&power RK3588_PD_SDMMC>; 2148 status = "disabled"; 2149 }; 2150 2151 sdio: mmc@fe2d0000 { 2152 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 2153 reg = <0x00 0xfe2d0000 0x00 0x4000>; 2154 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 2155 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 2156 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 2157 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2158 fifo-depth = <0x100>; 2159 max-frequency = <200000000>; 2160 pinctrl-names = "default"; 2161 pinctrl-0 = <&sdiom1_pins>; 2162 power-domains = <&power RK3588_PD_SDIO>; 2163 status = "disabled"; 2164 }; 2165 2166 sdhci: mmc@fe2e0000 { 2167 compatible = "rockchip,rk3588-dwcmshc"; 2168 reg = <0x0 0xfe2e0000 0x0 0x10000>; 2169 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 2170 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 2171 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 2172 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 2173 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2174 <&cru TMCLK_EMMC>; 2175 clock-names = "core", "bus", "axi", "block", "timer"; 2176 max-frequency = <200000000>; 2177 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 2178 <&emmc_cmd>, <&emmc_data_strobe>; 2179 pinctrl-names = "default"; 2180 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 2181 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 2182 <&cru SRST_T_EMMC>; 2183 reset-names = "core", "bus", "axi", "block", "timer"; 2184 supports-cqe; 2185 status = "disabled"; 2186 }; 2187 2188 rng@fe378000 { 2189 compatible = "rockchip,rk3588-rng"; 2190 reg = <0x0 0xfe378000 0x0 0x200>; 2191 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; 2192 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 2193 resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; 2194 }; 2195 2196 i2s0_8ch: i2s@fe470000 { 2197 compatible = "rockchip,rk3588-i2s-tdm"; 2198 reg = <0x0 0xfe470000 0x0 0x1000>; 2199 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 2200 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 2201 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2202 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 2203 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 2204 dmas = <&dmac0 0>, <&dmac0 1>; 2205 dma-names = "tx", "rx"; 2206 power-domains = <&power RK3588_PD_AUDIO>; 2207 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 2208 reset-names = "tx-m", "rx-m"; 2209 rockchip,trcm-sync-tx-only; 2210 pinctrl-names = "default"; 2211 pinctrl-0 = <&i2s0_lrck 2212 &i2s0_sclk 2213 &i2s0_sdi0 2214 &i2s0_sdi1 2215 &i2s0_sdi2 2216 &i2s0_sdi3 2217 &i2s0_sdo0 2218 &i2s0_sdo1 2219 &i2s0_sdo2 2220 &i2s0_sdo3>; 2221 #sound-dai-cells = <0>; 2222 status = "disabled"; 2223 }; 2224 2225 i2s1_8ch: i2s@fe480000 { 2226 compatible = "rockchip,rk3588-i2s-tdm"; 2227 reg = <0x0 0xfe480000 0x0 0x1000>; 2228 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 2229 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 2230 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2231 dmas = <&dmac0 2>, <&dmac0 3>; 2232 dma-names = "tx", "rx"; 2233 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 2234 reset-names = "tx-m", "rx-m"; 2235 rockchip,trcm-sync-tx-only; 2236 pinctrl-names = "default"; 2237 pinctrl-0 = <&i2s1m0_lrck 2238 &i2s1m0_sclk 2239 &i2s1m0_sdi0 2240 &i2s1m0_sdi1 2241 &i2s1m0_sdi2 2242 &i2s1m0_sdi3 2243 &i2s1m0_sdo0 2244 &i2s1m0_sdo1 2245 &i2s1m0_sdo2 2246 &i2s1m0_sdo3>; 2247 #sound-dai-cells = <0>; 2248 status = "disabled"; 2249 }; 2250 2251 i2s2_2ch: i2s@fe490000 { 2252 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2253 reg = <0x0 0xfe490000 0x0 0x1000>; 2254 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 2255 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2256 clock-names = "i2s_clk", "i2s_hclk"; 2257 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 2258 assigned-clock-parents = <&cru PLL_AUPLL>; 2259 dmas = <&dmac1 0>, <&dmac1 1>; 2260 dma-names = "tx", "rx"; 2261 power-domains = <&power RK3588_PD_AUDIO>; 2262 pinctrl-names = "default"; 2263 pinctrl-0 = <&i2s2m1_lrck 2264 &i2s2m1_sclk 2265 &i2s2m1_sdi 2266 &i2s2m1_sdo>; 2267 #sound-dai-cells = <0>; 2268 status = "disabled"; 2269 }; 2270 2271 i2s3_2ch: i2s@fe4a0000 { 2272 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2273 reg = <0x0 0xfe4a0000 0x0 0x1000>; 2274 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 2275 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 2276 clock-names = "i2s_clk", "i2s_hclk"; 2277 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2278 assigned-clock-parents = <&cru PLL_AUPLL>; 2279 dmas = <&dmac1 2>, <&dmac1 3>; 2280 dma-names = "tx", "rx"; 2281 power-domains = <&power RK3588_PD_AUDIO>; 2282 pinctrl-names = "default"; 2283 pinctrl-0 = <&i2s3_lrck 2284 &i2s3_sclk 2285 &i2s3_sdi 2286 &i2s3_sdo>; 2287 #sound-dai-cells = <0>; 2288 status = "disabled"; 2289 }; 2290 2291 spdif_tx0: spdif-tx@fe4e0000 { 2292 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2293 reg = <0x0 0xfe4e0000 0x0 0x1000>; 2294 assigned-clock-parents = <&cru PLL_AUPLL>; 2295 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 2296 clock-names = "mclk", "hclk"; 2297 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 2298 dma-names = "tx"; 2299 dmas = <&dmac0 5>; 2300 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 2301 pinctrl-0 = <&spdif0m0_tx>; 2302 pinctrl-names = "default"; 2303 power-domains = <&power RK3588_PD_AUDIO>; 2304 #sound-dai-cells = <0>; 2305 status = "disabled"; 2306 }; 2307 2308 spdif_tx1: spdif-tx@fe4f0000 { 2309 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2310 reg = <0x0 0xfe4f0000 0x0 0x1000>; 2311 assigned-clock-parents = <&cru PLL_AUPLL>; 2312 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 2313 clock-names = "mclk", "hclk"; 2314 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 2315 dma-names = "tx"; 2316 dmas = <&dmac1 5>; 2317 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 2318 pinctrl-0 = <&spdif1m0_tx>; 2319 pinctrl-names = "default"; 2320 power-domains = <&power RK3588_PD_AUDIO>; 2321 #sound-dai-cells = <0>; 2322 status = "disabled"; 2323 }; 2324 2325 gic: interrupt-controller@fe600000 { 2326 compatible = "arm,gic-v3"; 2327 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2328 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2329 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2330 interrupt-controller; 2331 dma-noncoherent; 2332 mbi-alias = <0x0 0xfe610000>; 2333 mbi-ranges = <424 56>; 2334 msi-controller; 2335 ranges; 2336 #address-cells = <2>; 2337 #interrupt-cells = <4>; 2338 #size-cells = <2>; 2339 2340 its0: msi-controller@fe640000 { 2341 compatible = "arm,gic-v3-its"; 2342 reg = <0x0 0xfe640000 0x0 0x20000>; 2343 dma-noncoherent; 2344 msi-controller; 2345 #msi-cells = <1>; 2346 }; 2347 2348 its1: msi-controller@fe660000 { 2349 compatible = "arm,gic-v3-its"; 2350 reg = <0x0 0xfe660000 0x0 0x20000>; 2351 dma-noncoherent; 2352 msi-controller; 2353 #msi-cells = <1>; 2354 }; 2355 2356 ppi-partitions { 2357 ppi_partition0: interrupt-partition-0 { 2358 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2359 }; 2360 2361 ppi_partition1: interrupt-partition-1 { 2362 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2363 }; 2364 }; 2365 }; 2366 2367 dmac0: dma-controller@fea10000 { 2368 compatible = "arm,pl330", "arm,primecell"; 2369 reg = <0x0 0xfea10000 0x0 0x4000>; 2370 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2371 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2372 arm,pl330-periph-burst; 2373 clocks = <&cru ACLK_DMAC0>; 2374 clock-names = "apb_pclk"; 2375 #dma-cells = <1>; 2376 }; 2377 2378 dmac1: dma-controller@fea30000 { 2379 compatible = "arm,pl330", "arm,primecell"; 2380 reg = <0x0 0xfea30000 0x0 0x4000>; 2381 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2382 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2383 arm,pl330-periph-burst; 2384 clocks = <&cru ACLK_DMAC1>; 2385 clock-names = "apb_pclk"; 2386 #dma-cells = <1>; 2387 }; 2388 2389 i2c1: i2c@fea90000 { 2390 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2391 reg = <0x0 0xfea90000 0x0 0x1000>; 2392 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2393 clock-names = "i2c", "pclk"; 2394 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2395 pinctrl-0 = <&i2c1m0_xfer>; 2396 pinctrl-names = "default"; 2397 #address-cells = <1>; 2398 #size-cells = <0>; 2399 status = "disabled"; 2400 }; 2401 2402 i2c2: i2c@feaa0000 { 2403 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2404 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2405 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2406 clock-names = "i2c", "pclk"; 2407 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2408 pinctrl-0 = <&i2c2m0_xfer>; 2409 pinctrl-names = "default"; 2410 #address-cells = <1>; 2411 #size-cells = <0>; 2412 status = "disabled"; 2413 }; 2414 2415 i2c3: i2c@feab0000 { 2416 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2417 reg = <0x0 0xfeab0000 0x0 0x1000>; 2418 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2419 clock-names = "i2c", "pclk"; 2420 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2421 pinctrl-0 = <&i2c3m0_xfer>; 2422 pinctrl-names = "default"; 2423 #address-cells = <1>; 2424 #size-cells = <0>; 2425 status = "disabled"; 2426 }; 2427 2428 i2c4: i2c@feac0000 { 2429 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2430 reg = <0x0 0xfeac0000 0x0 0x1000>; 2431 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2432 clock-names = "i2c", "pclk"; 2433 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2434 pinctrl-0 = <&i2c4m0_xfer>; 2435 pinctrl-names = "default"; 2436 #address-cells = <1>; 2437 #size-cells = <0>; 2438 status = "disabled"; 2439 }; 2440 2441 i2c5: i2c@fead0000 { 2442 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2443 reg = <0x0 0xfead0000 0x0 0x1000>; 2444 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2445 clock-names = "i2c", "pclk"; 2446 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2447 pinctrl-0 = <&i2c5m0_xfer>; 2448 pinctrl-names = "default"; 2449 #address-cells = <1>; 2450 #size-cells = <0>; 2451 status = "disabled"; 2452 }; 2453 2454 timer0: timer@feae0000 { 2455 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2456 reg = <0x0 0xfeae0000 0x0 0x20>; 2457 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2458 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2459 clock-names = "pclk", "timer"; 2460 }; 2461 2462 wdt: watchdog@feaf0000 { 2463 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2464 reg = <0x0 0xfeaf0000 0x0 0x100>; 2465 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2466 clock-names = "tclk", "pclk"; 2467 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2468 }; 2469 2470 spi0: spi@feb00000 { 2471 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2472 reg = <0x0 0xfeb00000 0x0 0x1000>; 2473 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2474 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2475 clock-names = "spiclk", "apb_pclk"; 2476 dmas = <&dmac0 14>, <&dmac0 15>; 2477 dma-names = "tx", "rx"; 2478 num-cs = <2>; 2479 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2480 pinctrl-names = "default"; 2481 #address-cells = <1>; 2482 #size-cells = <0>; 2483 status = "disabled"; 2484 }; 2485 2486 spi1: spi@feb10000 { 2487 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2488 reg = <0x0 0xfeb10000 0x0 0x1000>; 2489 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2490 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2491 clock-names = "spiclk", "apb_pclk"; 2492 dmas = <&dmac0 16>, <&dmac0 17>; 2493 dma-names = "tx", "rx"; 2494 num-cs = <2>; 2495 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2496 pinctrl-names = "default"; 2497 #address-cells = <1>; 2498 #size-cells = <0>; 2499 status = "disabled"; 2500 }; 2501 2502 spi2: spi@feb20000 { 2503 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2504 reg = <0x0 0xfeb20000 0x0 0x1000>; 2505 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2506 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2507 clock-names = "spiclk", "apb_pclk"; 2508 dmas = <&dmac1 15>, <&dmac1 16>; 2509 dma-names = "tx", "rx"; 2510 num-cs = <2>; 2511 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2512 pinctrl-names = "default"; 2513 #address-cells = <1>; 2514 #size-cells = <0>; 2515 status = "disabled"; 2516 }; 2517 2518 spi3: spi@feb30000 { 2519 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2520 reg = <0x0 0xfeb30000 0x0 0x1000>; 2521 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2522 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2523 clock-names = "spiclk", "apb_pclk"; 2524 dmas = <&dmac1 17>, <&dmac1 18>; 2525 dma-names = "tx", "rx"; 2526 num-cs = <2>; 2527 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2528 pinctrl-names = "default"; 2529 #address-cells = <1>; 2530 #size-cells = <0>; 2531 status = "disabled"; 2532 }; 2533 2534 uart1: serial@feb40000 { 2535 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2536 reg = <0x0 0xfeb40000 0x0 0x100>; 2537 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2538 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2539 clock-names = "baudclk", "apb_pclk"; 2540 dmas = <&dmac0 8>, <&dmac0 9>; 2541 dma-names = "tx", "rx"; 2542 pinctrl-0 = <&uart1m1_xfer>; 2543 pinctrl-names = "default"; 2544 reg-io-width = <4>; 2545 reg-shift = <2>; 2546 status = "disabled"; 2547 }; 2548 2549 uart2: serial@feb50000 { 2550 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2551 reg = <0x0 0xfeb50000 0x0 0x100>; 2552 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2553 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2554 clock-names = "baudclk", "apb_pclk"; 2555 dmas = <&dmac0 10>, <&dmac0 11>; 2556 dma-names = "tx", "rx"; 2557 pinctrl-0 = <&uart2m1_xfer>; 2558 pinctrl-names = "default"; 2559 reg-io-width = <4>; 2560 reg-shift = <2>; 2561 status = "disabled"; 2562 }; 2563 2564 uart3: serial@feb60000 { 2565 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2566 reg = <0x0 0xfeb60000 0x0 0x100>; 2567 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2568 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2569 clock-names = "baudclk", "apb_pclk"; 2570 dmas = <&dmac0 12>, <&dmac0 13>; 2571 dma-names = "tx", "rx"; 2572 pinctrl-0 = <&uart3m1_xfer>; 2573 pinctrl-names = "default"; 2574 reg-io-width = <4>; 2575 reg-shift = <2>; 2576 status = "disabled"; 2577 }; 2578 2579 uart4: serial@feb70000 { 2580 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2581 reg = <0x0 0xfeb70000 0x0 0x100>; 2582 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2583 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2584 clock-names = "baudclk", "apb_pclk"; 2585 dmas = <&dmac1 9>, <&dmac1 10>; 2586 dma-names = "tx", "rx"; 2587 pinctrl-0 = <&uart4m1_xfer>; 2588 pinctrl-names = "default"; 2589 reg-io-width = <4>; 2590 reg-shift = <2>; 2591 status = "disabled"; 2592 }; 2593 2594 uart5: serial@feb80000 { 2595 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2596 reg = <0x0 0xfeb80000 0x0 0x100>; 2597 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2598 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2599 clock-names = "baudclk", "apb_pclk"; 2600 dmas = <&dmac1 11>, <&dmac1 12>; 2601 dma-names = "tx", "rx"; 2602 pinctrl-0 = <&uart5m1_xfer>; 2603 pinctrl-names = "default"; 2604 reg-io-width = <4>; 2605 reg-shift = <2>; 2606 status = "disabled"; 2607 }; 2608 2609 uart6: serial@feb90000 { 2610 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2611 reg = <0x0 0xfeb90000 0x0 0x100>; 2612 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2613 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2614 clock-names = "baudclk", "apb_pclk"; 2615 dmas = <&dmac1 13>, <&dmac1 14>; 2616 dma-names = "tx", "rx"; 2617 pinctrl-0 = <&uart6m1_xfer>; 2618 pinctrl-names = "default"; 2619 reg-io-width = <4>; 2620 reg-shift = <2>; 2621 status = "disabled"; 2622 }; 2623 2624 uart7: serial@feba0000 { 2625 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2626 reg = <0x0 0xfeba0000 0x0 0x100>; 2627 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2628 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2629 clock-names = "baudclk", "apb_pclk"; 2630 dmas = <&dmac2 7>, <&dmac2 8>; 2631 dma-names = "tx", "rx"; 2632 pinctrl-0 = <&uart7m1_xfer>; 2633 pinctrl-names = "default"; 2634 reg-io-width = <4>; 2635 reg-shift = <2>; 2636 status = "disabled"; 2637 }; 2638 2639 uart8: serial@febb0000 { 2640 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2641 reg = <0x0 0xfebb0000 0x0 0x100>; 2642 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2643 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2644 clock-names = "baudclk", "apb_pclk"; 2645 dmas = <&dmac2 9>, <&dmac2 10>; 2646 dma-names = "tx", "rx"; 2647 pinctrl-0 = <&uart8m1_xfer>; 2648 pinctrl-names = "default"; 2649 reg-io-width = <4>; 2650 reg-shift = <2>; 2651 status = "disabled"; 2652 }; 2653 2654 uart9: serial@febc0000 { 2655 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2656 reg = <0x0 0xfebc0000 0x0 0x100>; 2657 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2658 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2659 clock-names = "baudclk", "apb_pclk"; 2660 dmas = <&dmac2 11>, <&dmac2 12>; 2661 dma-names = "tx", "rx"; 2662 pinctrl-0 = <&uart9m1_xfer>; 2663 pinctrl-names = "default"; 2664 reg-io-width = <4>; 2665 reg-shift = <2>; 2666 status = "disabled"; 2667 }; 2668 2669 pwm4: pwm@febd0000 { 2670 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2671 reg = <0x0 0xfebd0000 0x0 0x10>; 2672 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2673 clock-names = "pwm", "pclk"; 2674 pinctrl-0 = <&pwm4m0_pins>; 2675 pinctrl-names = "default"; 2676 #pwm-cells = <3>; 2677 status = "disabled"; 2678 }; 2679 2680 pwm5: pwm@febd0010 { 2681 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2682 reg = <0x0 0xfebd0010 0x0 0x10>; 2683 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2684 clock-names = "pwm", "pclk"; 2685 pinctrl-0 = <&pwm5m0_pins>; 2686 pinctrl-names = "default"; 2687 #pwm-cells = <3>; 2688 status = "disabled"; 2689 }; 2690 2691 pwm6: pwm@febd0020 { 2692 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2693 reg = <0x0 0xfebd0020 0x0 0x10>; 2694 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2695 clock-names = "pwm", "pclk"; 2696 pinctrl-0 = <&pwm6m0_pins>; 2697 pinctrl-names = "default"; 2698 #pwm-cells = <3>; 2699 status = "disabled"; 2700 }; 2701 2702 pwm7: pwm@febd0030 { 2703 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2704 reg = <0x0 0xfebd0030 0x0 0x10>; 2705 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2706 clock-names = "pwm", "pclk"; 2707 pinctrl-0 = <&pwm7m0_pins>; 2708 pinctrl-names = "default"; 2709 #pwm-cells = <3>; 2710 status = "disabled"; 2711 }; 2712 2713 pwm8: pwm@febe0000 { 2714 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2715 reg = <0x0 0xfebe0000 0x0 0x10>; 2716 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2717 clock-names = "pwm", "pclk"; 2718 pinctrl-0 = <&pwm8m0_pins>; 2719 pinctrl-names = "default"; 2720 #pwm-cells = <3>; 2721 status = "disabled"; 2722 }; 2723 2724 pwm9: pwm@febe0010 { 2725 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2726 reg = <0x0 0xfebe0010 0x0 0x10>; 2727 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2728 clock-names = "pwm", "pclk"; 2729 pinctrl-0 = <&pwm9m0_pins>; 2730 pinctrl-names = "default"; 2731 #pwm-cells = <3>; 2732 status = "disabled"; 2733 }; 2734 2735 pwm10: pwm@febe0020 { 2736 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2737 reg = <0x0 0xfebe0020 0x0 0x10>; 2738 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2739 clock-names = "pwm", "pclk"; 2740 pinctrl-0 = <&pwm10m0_pins>; 2741 pinctrl-names = "default"; 2742 #pwm-cells = <3>; 2743 status = "disabled"; 2744 }; 2745 2746 pwm11: pwm@febe0030 { 2747 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2748 reg = <0x0 0xfebe0030 0x0 0x10>; 2749 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2750 clock-names = "pwm", "pclk"; 2751 pinctrl-0 = <&pwm11m0_pins>; 2752 pinctrl-names = "default"; 2753 #pwm-cells = <3>; 2754 status = "disabled"; 2755 }; 2756 2757 pwm12: pwm@febf0000 { 2758 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2759 reg = <0x0 0xfebf0000 0x0 0x10>; 2760 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2761 clock-names = "pwm", "pclk"; 2762 pinctrl-0 = <&pwm12m0_pins>; 2763 pinctrl-names = "default"; 2764 #pwm-cells = <3>; 2765 status = "disabled"; 2766 }; 2767 2768 pwm13: pwm@febf0010 { 2769 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2770 reg = <0x0 0xfebf0010 0x0 0x10>; 2771 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2772 clock-names = "pwm", "pclk"; 2773 pinctrl-0 = <&pwm13m0_pins>; 2774 pinctrl-names = "default"; 2775 #pwm-cells = <3>; 2776 status = "disabled"; 2777 }; 2778 2779 pwm14: pwm@febf0020 { 2780 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2781 reg = <0x0 0xfebf0020 0x0 0x10>; 2782 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2783 clock-names = "pwm", "pclk"; 2784 pinctrl-0 = <&pwm14m0_pins>; 2785 pinctrl-names = "default"; 2786 #pwm-cells = <3>; 2787 status = "disabled"; 2788 }; 2789 2790 pwm15: pwm@febf0030 { 2791 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2792 reg = <0x0 0xfebf0030 0x0 0x10>; 2793 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2794 clock-names = "pwm", "pclk"; 2795 pinctrl-0 = <&pwm15m0_pins>; 2796 pinctrl-names = "default"; 2797 #pwm-cells = <3>; 2798 status = "disabled"; 2799 }; 2800 2801 thermal_zones: thermal-zones { 2802 /* sensor near the center of the SoC */ 2803 package_thermal: package-thermal { 2804 polling-delay-passive = <0>; 2805 polling-delay = <0>; 2806 thermal-sensors = <&tsadc 0>; 2807 2808 trips { 2809 package_crit: package-crit { 2810 temperature = <115000>; 2811 hysteresis = <0>; 2812 type = "critical"; 2813 }; 2814 }; 2815 }; 2816 2817 /* sensor between A76 cores 0 and 1 */ 2818 bigcore0_thermal: bigcore0-thermal { 2819 polling-delay-passive = <100>; 2820 polling-delay = <0>; 2821 thermal-sensors = <&tsadc 1>; 2822 2823 trips { 2824 bigcore0_alert: bigcore0-alert { 2825 temperature = <85000>; 2826 hysteresis = <2000>; 2827 type = "passive"; 2828 }; 2829 2830 bigcore0_crit: bigcore0-crit { 2831 temperature = <115000>; 2832 hysteresis = <0>; 2833 type = "critical"; 2834 }; 2835 }; 2836 2837 cooling-maps { 2838 map0 { 2839 trip = <&bigcore0_alert>; 2840 cooling-device = 2841 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2842 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2843 }; 2844 }; 2845 }; 2846 2847 /* sensor between A76 cores 2 and 3 */ 2848 bigcore2_thermal: bigcore2-thermal { 2849 polling-delay-passive = <100>; 2850 polling-delay = <0>; 2851 thermal-sensors = <&tsadc 2>; 2852 2853 trips { 2854 bigcore2_alert: bigcore2-alert { 2855 temperature = <85000>; 2856 hysteresis = <2000>; 2857 type = "passive"; 2858 }; 2859 2860 bigcore2_crit: bigcore2-crit { 2861 temperature = <115000>; 2862 hysteresis = <0>; 2863 type = "critical"; 2864 }; 2865 }; 2866 2867 cooling-maps { 2868 map0 { 2869 trip = <&bigcore2_alert>; 2870 cooling-device = 2871 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2872 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2873 }; 2874 }; 2875 }; 2876 2877 /* sensor between the four A55 cores */ 2878 little_core_thermal: littlecore-thermal { 2879 polling-delay-passive = <100>; 2880 polling-delay = <0>; 2881 thermal-sensors = <&tsadc 3>; 2882 2883 trips { 2884 littlecore_alert: littlecore-alert { 2885 temperature = <85000>; 2886 hysteresis = <2000>; 2887 type = "passive"; 2888 }; 2889 2890 littlecore_crit: littlecore-crit { 2891 temperature = <115000>; 2892 hysteresis = <0>; 2893 type = "critical"; 2894 }; 2895 }; 2896 2897 cooling-maps { 2898 map0 { 2899 trip = <&littlecore_alert>; 2900 cooling-device = 2901 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2902 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2903 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2904 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2905 }; 2906 }; 2907 }; 2908 2909 /* sensor near the PD_CENTER power domain */ 2910 center_thermal: center-thermal { 2911 polling-delay-passive = <0>; 2912 polling-delay = <0>; 2913 thermal-sensors = <&tsadc 4>; 2914 2915 trips { 2916 center_crit: center-crit { 2917 temperature = <115000>; 2918 hysteresis = <0>; 2919 type = "critical"; 2920 }; 2921 }; 2922 }; 2923 2924 gpu_thermal: gpu-thermal { 2925 polling-delay-passive = <100>; 2926 polling-delay = <0>; 2927 thermal-sensors = <&tsadc 5>; 2928 2929 trips { 2930 gpu_alert: gpu-alert { 2931 temperature = <85000>; 2932 hysteresis = <2000>; 2933 type = "passive"; 2934 }; 2935 2936 gpu_crit: gpu-crit { 2937 temperature = <115000>; 2938 hysteresis = <0>; 2939 type = "critical"; 2940 }; 2941 }; 2942 2943 cooling-maps { 2944 map0 { 2945 trip = <&gpu_alert>; 2946 cooling-device = 2947 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2948 }; 2949 }; 2950 }; 2951 2952 npu_thermal: npu-thermal { 2953 polling-delay-passive = <0>; 2954 polling-delay = <0>; 2955 thermal-sensors = <&tsadc 6>; 2956 2957 trips { 2958 npu_crit: npu-crit { 2959 temperature = <115000>; 2960 hysteresis = <0>; 2961 type = "critical"; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 tsadc: tsadc@fec00000 { 2968 compatible = "rockchip,rk3588-tsadc"; 2969 reg = <0x0 0xfec00000 0x0 0x400>; 2970 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2971 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2972 clock-names = "tsadc", "apb_pclk"; 2973 assigned-clocks = <&cru CLK_TSADC>; 2974 assigned-clock-rates = <2000000>; 2975 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2976 reset-names = "tsadc-apb", "tsadc"; 2977 rockchip,hw-tshut-temp = <120000>; 2978 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2979 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2980 pinctrl-0 = <&tsadc_shut_org>; 2981 pinctrl-1 = <&tsadc_gpio_func>; 2982 pinctrl-names = "default", "sleep"; 2983 #thermal-sensor-cells = <1>; 2984 status = "disabled"; 2985 }; 2986 2987 saradc: adc@fec10000 { 2988 compatible = "rockchip,rk3588-saradc"; 2989 reg = <0x0 0xfec10000 0x0 0x10000>; 2990 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2991 #io-channel-cells = <1>; 2992 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2993 clock-names = "saradc", "apb_pclk"; 2994 resets = <&cru SRST_P_SARADC>; 2995 reset-names = "saradc-apb"; 2996 status = "disabled"; 2997 }; 2998 2999 i2c6: i2c@fec80000 { 3000 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3001 reg = <0x0 0xfec80000 0x0 0x1000>; 3002 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 3003 clock-names = "i2c", "pclk"; 3004 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 3005 pinctrl-0 = <&i2c6m0_xfer>; 3006 pinctrl-names = "default"; 3007 #address-cells = <1>; 3008 #size-cells = <0>; 3009 status = "disabled"; 3010 }; 3011 3012 i2c7: i2c@fec90000 { 3013 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3014 reg = <0x0 0xfec90000 0x0 0x1000>; 3015 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 3016 clock-names = "i2c", "pclk"; 3017 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 3018 pinctrl-0 = <&i2c7m0_xfer>; 3019 pinctrl-names = "default"; 3020 #address-cells = <1>; 3021 #size-cells = <0>; 3022 status = "disabled"; 3023 }; 3024 3025 i2c8: i2c@feca0000 { 3026 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 3027 reg = <0x0 0xfeca0000 0x0 0x1000>; 3028 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 3029 clock-names = "i2c", "pclk"; 3030 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 3031 pinctrl-0 = <&i2c8m0_xfer>; 3032 pinctrl-names = "default"; 3033 #address-cells = <1>; 3034 #size-cells = <0>; 3035 status = "disabled"; 3036 }; 3037 3038 spi4: spi@fecb0000 { 3039 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 3040 reg = <0x0 0xfecb0000 0x0 0x1000>; 3041 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 3042 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 3043 clock-names = "spiclk", "apb_pclk"; 3044 dmas = <&dmac2 13>, <&dmac2 14>; 3045 dma-names = "tx", "rx"; 3046 num-cs = <2>; 3047 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 3048 pinctrl-names = "default"; 3049 #address-cells = <1>; 3050 #size-cells = <0>; 3051 status = "disabled"; 3052 }; 3053 3054 otp: efuse@fecc0000 { 3055 compatible = "rockchip,rk3588-otp"; 3056 reg = <0x0 0xfecc0000 0x0 0x400>; 3057 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 3058 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 3059 clock-names = "otp", "apb_pclk", "phy", "arb"; 3060 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 3061 <&cru SRST_OTPC_ARB>; 3062 reset-names = "otp", "apb", "arb"; 3063 #address-cells = <1>; 3064 #size-cells = <1>; 3065 3066 cpu_code: cpu-code@2 { 3067 reg = <0x02 0x2>; 3068 }; 3069 3070 otp_id: id@7 { 3071 reg = <0x07 0x10>; 3072 }; 3073 3074 cpub0_leakage: cpu-leakage@17 { 3075 reg = <0x17 0x1>; 3076 }; 3077 3078 cpub1_leakage: cpu-leakage@18 { 3079 reg = <0x18 0x1>; 3080 }; 3081 3082 cpul_leakage: cpu-leakage@19 { 3083 reg = <0x19 0x1>; 3084 }; 3085 3086 log_leakage: log-leakage@1a { 3087 reg = <0x1a 0x1>; 3088 }; 3089 3090 gpu_leakage: gpu-leakage@1b { 3091 reg = <0x1b 0x1>; 3092 }; 3093 3094 otp_cpu_version: cpu-version@1c { 3095 reg = <0x1c 0x1>; 3096 bits = <3 3>; 3097 }; 3098 3099 npu_leakage: npu-leakage@28 { 3100 reg = <0x28 0x1>; 3101 }; 3102 3103 codec_leakage: codec-leakage@29 { 3104 reg = <0x29 0x1>; 3105 }; 3106 }; 3107 3108 dmac2: dma-controller@fed10000 { 3109 compatible = "arm,pl330", "arm,primecell"; 3110 reg = <0x0 0xfed10000 0x0 0x4000>; 3111 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 3112 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 3113 arm,pl330-periph-burst; 3114 clocks = <&cru ACLK_DMAC2>; 3115 clock-names = "apb_pclk"; 3116 #dma-cells = <1>; 3117 }; 3118 3119 hdptxphy0: phy@fed60000 { 3120 compatible = "rockchip,rk3588-hdptx-phy"; 3121 reg = <0x0 0xfed60000 0x0 0x2000>; 3122 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 3123 clock-names = "ref", "apb"; 3124 #clock-cells = <0>; 3125 #phy-cells = <0>; 3126 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 3127 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 3128 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 3129 <&cru SRST_HDPTX0_LCPLL>; 3130 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 3131 "lcpll"; 3132 rockchip,grf = <&hdptxphy0_grf>; 3133 status = "disabled"; 3134 }; 3135 3136 usbdp_phy0: phy@fed80000 { 3137 compatible = "rockchip,rk3588-usbdp-phy"; 3138 reg = <0x0 0xfed80000 0x0 0x10000>; 3139 #phy-cells = <1>; 3140 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 3141 <&cru CLK_USBDP_PHY0_IMMORTAL>, 3142 <&cru PCLK_USBDPPHY0>, 3143 <&u2phy0>; 3144 clock-names = "refclk", "immortal", "pclk", "utmi"; 3145 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 3146 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 3147 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 3148 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 3149 <&cru SRST_P_USBDPPHY0>; 3150 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 3151 rockchip,u2phy-grf = <&usb2phy0_grf>; 3152 rockchip,usb-grf = <&usb_grf>; 3153 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 3154 rockchip,vo-grf = <&vo0_grf>; 3155 status = "disabled"; 3156 }; 3157 3158 mipidcphy0: phy@feda0000 { 3159 compatible = "rockchip,rk3588-mipi-dcphy"; 3160 reg = <0x0 0xfeda0000 0x0 0x10000>; 3161 rockchip,grf = <&mipidcphy0_grf>; 3162 clocks = <&cru PCLK_MIPI_DCPHY0>, 3163 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3164 clock-names = "pclk", "ref"; 3165 resets = <&cru SRST_M_MIPI_DCPHY0>, 3166 <&cru SRST_P_MIPI_DCPHY0>, 3167 <&cru SRST_P_MIPI_DCPHY0_GRF>, 3168 <&cru SRST_S_MIPI_DCPHY0>; 3169 reset-names = "m_phy", "apb", "grf", "s_phy"; 3170 #phy-cells = <1>; 3171 status = "disabled"; 3172 }; 3173 3174 mipidcphy1: phy@fedb0000 { 3175 compatible = "rockchip,rk3588-mipi-dcphy"; 3176 reg = <0x0 0xfedb0000 0x0 0x10000>; 3177 rockchip,grf = <&mipidcphy1_grf>; 3178 clocks = <&cru PCLK_MIPI_DCPHY1>, 3179 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 3180 clock-names = "pclk", "ref"; 3181 resets = <&cru SRST_M_MIPI_DCPHY1>, 3182 <&cru SRST_P_MIPI_DCPHY1>, 3183 <&cru SRST_P_MIPI_DCPHY1_GRF>, 3184 <&cru SRST_S_MIPI_DCPHY1>; 3185 reset-names = "m_phy", "apb", "grf", "s_phy"; 3186 #phy-cells = <1>; 3187 status = "disabled"; 3188 }; 3189 3190 csi_dphy0: phy@fedc0000 { 3191 compatible = "rockchip,rk3588-csi-dphy"; 3192 reg = <0x0 0xfedc0000 0x0 0x8000>; 3193 clocks = <&cru PCLK_CSIPHY0>; 3194 clock-names = "pclk"; 3195 #phy-cells = <0>; 3196 resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; 3197 reset-names = "apb", "phy"; 3198 rockchip,grf = <&csidphy0_grf>; 3199 status = "disabled"; 3200 }; 3201 3202 csi_dphy1: phy@fedc8000 { 3203 compatible = "rockchip,rk3588-csi-dphy"; 3204 reg = <0x0 0xfedc8000 0x0 0x8000>; 3205 clocks = <&cru PCLK_CSIPHY1>; 3206 clock-names = "pclk"; 3207 #phy-cells = <0>; 3208 resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; 3209 reset-names = "apb", "phy"; 3210 rockchip,grf = <&csidphy1_grf>; 3211 status = "disabled"; 3212 }; 3213 3214 combphy0_ps: phy@fee00000 { 3215 compatible = "rockchip,rk3588-naneng-combphy"; 3216 reg = <0x0 0xfee00000 0x0 0x100>; 3217 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 3218 <&cru PCLK_PHP_ROOT>; 3219 clock-names = "ref", "apb", "pipe"; 3220 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 3221 assigned-clock-rates = <100000000>; 3222 #phy-cells = <1>; 3223 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 3224 reset-names = "phy", "apb"; 3225 rockchip,pipe-grf = <&php_grf>; 3226 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 3227 status = "disabled"; 3228 }; 3229 3230 combphy2_psu: phy@fee20000 { 3231 compatible = "rockchip,rk3588-naneng-combphy"; 3232 reg = <0x0 0xfee20000 0x0 0x100>; 3233 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 3234 <&cru PCLK_PHP_ROOT>; 3235 clock-names = "ref", "apb", "pipe"; 3236 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 3237 assigned-clock-rates = <100000000>; 3238 #phy-cells = <1>; 3239 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 3240 reset-names = "phy", "apb"; 3241 rockchip,pipe-grf = <&php_grf>; 3242 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 3243 status = "disabled"; 3244 }; 3245 3246 system_sram2: sram@ff001000 { 3247 compatible = "mmio-sram"; 3248 reg = <0x0 0xff001000 0x0 0xef000>; 3249 ranges = <0x0 0x0 0xff001000 0xef000>; 3250 #address-cells = <1>; 3251 #size-cells = <1>; 3252 }; 3253 3254 pinctrl: pinctrl { 3255 compatible = "rockchip,rk3588-pinctrl"; 3256 ranges; 3257 rockchip,grf = <&ioc>; 3258 #address-cells = <2>; 3259 #size-cells = <2>; 3260 3261 gpio0: gpio@fd8a0000 { 3262 compatible = "rockchip,gpio-bank"; 3263 reg = <0x0 0xfd8a0000 0x0 0x100>; 3264 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 3265 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 3266 gpio-controller; 3267 gpio-ranges = <&pinctrl 0 0 32>; 3268 interrupt-controller; 3269 #gpio-cells = <2>; 3270 #interrupt-cells = <2>; 3271 }; 3272 3273 gpio1: gpio@fec20000 { 3274 compatible = "rockchip,gpio-bank"; 3275 reg = <0x0 0xfec20000 0x0 0x100>; 3276 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 3277 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3278 gpio-controller; 3279 gpio-ranges = <&pinctrl 0 32 32>; 3280 interrupt-controller; 3281 #gpio-cells = <2>; 3282 #interrupt-cells = <2>; 3283 }; 3284 3285 gpio2: gpio@fec30000 { 3286 compatible = "rockchip,gpio-bank"; 3287 reg = <0x0 0xfec30000 0x0 0x100>; 3288 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 3289 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3290 gpio-controller; 3291 gpio-ranges = <&pinctrl 0 64 32>; 3292 interrupt-controller; 3293 #gpio-cells = <2>; 3294 #interrupt-cells = <2>; 3295 }; 3296 3297 gpio3: gpio@fec40000 { 3298 compatible = "rockchip,gpio-bank"; 3299 reg = <0x0 0xfec40000 0x0 0x100>; 3300 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 3301 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3302 gpio-controller; 3303 gpio-ranges = <&pinctrl 0 96 32>; 3304 interrupt-controller; 3305 #gpio-cells = <2>; 3306 #interrupt-cells = <2>; 3307 }; 3308 3309 gpio4: gpio@fec50000 { 3310 compatible = "rockchip,gpio-bank"; 3311 reg = <0x0 0xfec50000 0x0 0x100>; 3312 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 3313 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3314 gpio-controller; 3315 gpio-ranges = <&pinctrl 0 128 32>; 3316 interrupt-controller; 3317 #gpio-cells = <2>; 3318 #interrupt-cells = <2>; 3319 }; 3320 }; 3321}; 3322 3323#include "rk3588-base-pinctrl.dtsi"
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