rk356x-base.dtsi

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4 */
   5
   6#include <dt-bindings/clock/rk3568-cru.h>
   7#include <dt-bindings/interrupt-controller/arm-gic.h>
   8#include <dt-bindings/interrupt-controller/irq.h>
   9#include <dt-bindings/phy/phy.h>
  10#include <dt-bindings/pinctrl/rockchip.h>
  11#include <dt-bindings/power/rk3568-power.h>
  12#include <dt-bindings/soc/rockchip,boot-mode.h>
  13#include <dt-bindings/thermal/thermal.h>
  14
  15/ {
  16	interrupt-parent = <&gic>;
  17	#address-cells = <2>;
  18	#size-cells = <2>;
  19
  20	aliases {
  21		gpio0 = &gpio0;
  22		gpio1 = &gpio1;
  23		gpio2 = &gpio2;
  24		gpio3 = &gpio3;
  25		gpio4 = &gpio4;
  26		i2c0 = &i2c0;
  27		i2c1 = &i2c1;
  28		i2c2 = &i2c2;
  29		i2c3 = &i2c3;
  30		i2c4 = &i2c4;
  31		i2c5 = &i2c5;
  32		serial0 = &uart0;
  33		serial1 = &uart1;
  34		serial2 = &uart2;
  35		serial3 = &uart3;
  36		serial4 = &uart4;
  37		serial5 = &uart5;
  38		serial6 = &uart6;
  39		serial7 = &uart7;
  40		serial8 = &uart8;
  41		serial9 = &uart9;
  42		spi0 = &spi0;
  43		spi1 = &spi1;
  44		spi2 = &spi2;
  45		spi3 = &spi3;
  46	};
  47
  48	cpus {
  49		#address-cells = <2>;
  50		#size-cells = <0>;
  51
  52		cpu0: cpu@0 {
  53			device_type = "cpu";
  54			compatible = "arm,cortex-a55";
  55			reg = <0x0 0x0>;
  56			clocks = <&scmi_clk SCMI_CLK_CPU>;
  57			#cooling-cells = <2>;
  58			enable-method = "psci";
  59			i-cache-size = <0x8000>;
  60			i-cache-line-size = <64>;
  61			i-cache-sets = <128>;
  62			d-cache-size = <0x8000>;
  63			d-cache-line-size = <64>;
  64			d-cache-sets = <128>;
  65			next-level-cache = <&l3_cache>;
  66		};
  67
  68		cpu1: cpu@100 {
  69			device_type = "cpu";
  70			compatible = "arm,cortex-a55";
  71			reg = <0x0 0x100>;
  72			clocks = <&scmi_clk SCMI_CLK_CPU>;
  73			#cooling-cells = <2>;
  74			enable-method = "psci";
  75			i-cache-size = <0x8000>;
  76			i-cache-line-size = <64>;
  77			i-cache-sets = <128>;
  78			d-cache-size = <0x8000>;
  79			d-cache-line-size = <64>;
  80			d-cache-sets = <128>;
  81			next-level-cache = <&l3_cache>;
  82		};
  83
  84		cpu2: cpu@200 {
  85			device_type = "cpu";
  86			compatible = "arm,cortex-a55";
  87			reg = <0x0 0x200>;
  88			clocks = <&scmi_clk SCMI_CLK_CPU>;
  89			#cooling-cells = <2>;
  90			enable-method = "psci";
  91			i-cache-size = <0x8000>;
  92			i-cache-line-size = <64>;
  93			i-cache-sets = <128>;
  94			d-cache-size = <0x8000>;
  95			d-cache-line-size = <64>;
  96			d-cache-sets = <128>;
  97			next-level-cache = <&l3_cache>;
  98		};
  99
 100		cpu3: cpu@300 {
 101			device_type = "cpu";
 102			compatible = "arm,cortex-a55";
 103			reg = <0x0 0x300>;
 104			clocks = <&scmi_clk SCMI_CLK_CPU>;
 105			#cooling-cells = <2>;
 106			enable-method = "psci";
 107			i-cache-size = <0x8000>;
 108			i-cache-line-size = <64>;
 109			i-cache-sets = <128>;
 110			d-cache-size = <0x8000>;
 111			d-cache-line-size = <64>;
 112			d-cache-sets = <128>;
 113			next-level-cache = <&l3_cache>;
 114		};
 115	};
 116
 117	/*
 118	 * There are no private per-core L2 caches, but only the
 119	 * L3 cache that appears to the CPU cores as L2 caches
 120	 */
 121	l3_cache: l3-cache {
 122		compatible = "cache";
 123		cache-level = <2>;
 124		cache-unified;
 125		cache-size = <0x80000>;
 126		cache-line-size = <64>;
 127		cache-sets = <512>;
 128	};
 129
 130	display_subsystem: display-subsystem {
 131		compatible = "rockchip,display-subsystem";
 132		ports = <&vop_out>;
 133	};
 134
 135	firmware {
 136		scmi: scmi {
 137			compatible = "arm,scmi-smc";
 138			arm,smc-id = <0x82000010>;
 139			shmem = <&scmi_shmem>;
 140			#address-cells = <1>;
 141			#size-cells = <0>;
 142
 143			scmi_clk: protocol@14 {
 144				reg = <0x14>;
 145				#clock-cells = <1>;
 146			};
 147		};
 148	};
 149
 150	hdmi_sound: hdmi-sound {
 151		compatible = "simple-audio-card";
 152		simple-audio-card,name = "HDMI";
 153		simple-audio-card,format = "i2s";
 154		simple-audio-card,mclk-fs = <256>;
 155		status = "disabled";
 156
 157		simple-audio-card,codec {
 158			sound-dai = <&hdmi>;
 159		};
 160
 161		simple-audio-card,cpu {
 162			sound-dai = <&i2s0_8ch>;
 163		};
 164	};
 165
 166	pmu {
 167		compatible = "arm,cortex-a55-pmu";
 168		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
 169			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 170			     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 171			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 172		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 173	};
 174
 175	psci {
 176		compatible = "arm,psci-1.0";
 177		method = "smc";
 178	};
 179
 180	reserved-memory {
 181		#address-cells = <2>;
 182		#size-cells = <2>;
 183		ranges;
 184
 185		scmi_shmem: shmem@10f000 {
 186			compatible = "arm,scmi-shmem";
 187			reg = <0x0 0x0010f000 0x0 0x100>;
 188			no-map;
 189		};
 190	};
 191
 192	timer {
 193		compatible = "arm,armv8-timer";
 194		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 195			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 196			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 197			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 198		arm,no-tick-in-suspend;
 199	};
 200
 201	xin24m: xin24m {
 202		compatible = "fixed-clock";
 203		clock-frequency = <24000000>;
 204		clock-output-names = "xin24m";
 205		#clock-cells = <0>;
 206	};
 207
 208	xin32k: xin32k {
 209		compatible = "fixed-clock";
 210		clock-frequency = <32768>;
 211		clock-output-names = "xin32k";
 212		pinctrl-0 = <&clk32k_out0>;
 213		pinctrl-names = "default";
 214		#clock-cells = <0>;
 215	};
 216
 217	sata1: sata@fc400000 {
 218		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 219		reg = <0 0xfc400000 0 0x1000>;
 220		clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
 221			 <&cru CLK_SATA1_RXOOB>;
 222		clock-names = "sata", "pmalive", "rxoob";
 223		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 224		phys = <&combphy1 PHY_TYPE_SATA>;
 225		phy-names = "sata-phy";
 226		ports-implemented = <0x1>;
 227		power-domains = <&power RK3568_PD_PIPE>;
 228		status = "disabled";
 229	};
 230
 231	sata2: sata@fc800000 {
 232		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 233		reg = <0 0xfc800000 0 0x1000>;
 234		clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
 235			 <&cru CLK_SATA2_RXOOB>;
 236		clock-names = "sata", "pmalive", "rxoob";
 237		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 238		phys = <&combphy2 PHY_TYPE_SATA>;
 239		phy-names = "sata-phy";
 240		ports-implemented = <0x1>;
 241		power-domains = <&power RK3568_PD_PIPE>;
 242		status = "disabled";
 243	};
 244
 245	usb_host0_xhci: usb@fcc00000 {
 246		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 247		reg = <0x0 0xfcc00000 0x0 0x400000>;
 248		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 249		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
 250			 <&cru ACLK_USB3OTG0>;
 251		clock-names = "ref_clk", "suspend_clk",
 252			      "bus_clk";
 253		dr_mode = "otg";
 254		phy_type = "utmi_wide";
 255		power-domains = <&power RK3568_PD_PIPE>;
 256		resets = <&cru SRST_USB3OTG0>;
 257		snps,dis_u2_susphy_quirk;
 258		status = "disabled";
 259	};
 260
 261	usb_host1_xhci: usb@fd000000 {
 262		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 263		reg = <0x0 0xfd000000 0x0 0x400000>;
 264		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 265		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
 266			 <&cru ACLK_USB3OTG1>;
 267		clock-names = "ref_clk", "suspend_clk",
 268			      "bus_clk";
 269		dr_mode = "host";
 270		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
 271		phy-names = "usb2-phy", "usb3-phy";
 272		phy_type = "utmi_wide";
 273		power-domains = <&power RK3568_PD_PIPE>;
 274		resets = <&cru SRST_USB3OTG1>;
 275		snps,dis_u2_susphy_quirk;
 276		status = "disabled";
 277	};
 278
 279	gic: interrupt-controller@fd400000 {
 280		compatible = "arm,gic-v3";
 281		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
 282		      <0x0 0xfd460000 0 0x80000>; /* GICR */
 283		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 284		interrupt-controller;
 285		#interrupt-cells = <3>;
 286		mbi-alias = <0x0 0xfd410000>;
 287		mbi-ranges = <296 24>;
 288		msi-controller;
 289		ranges;
 290		#address-cells = <2>;
 291		#size-cells = <2>;
 292		dma-noncoherent;
 293
 294		its: msi-controller@fd440000 {
 295			compatible = "arm,gic-v3-its";
 296			reg = <0x0 0xfd440000 0 0x20000>;
 297			dma-noncoherent;
 298			msi-controller;
 299			#msi-cells = <1>;
 300		};
 301	};
 302
 303	usb_host0_ehci: usb@fd800000 {
 304		compatible = "generic-ehci";
 305		reg = <0x0 0xfd800000 0x0 0x40000>;
 306		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 307		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 308			 <&cru PCLK_USB>;
 309		phys = <&usb2phy1_otg>;
 310		phy-names = "usb";
 311		status = "disabled";
 312	};
 313
 314	usb_host0_ohci: usb@fd840000 {
 315		compatible = "generic-ohci";
 316		reg = <0x0 0xfd840000 0x0 0x40000>;
 317		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 318		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 319			 <&cru PCLK_USB>;
 320		phys = <&usb2phy1_otg>;
 321		phy-names = "usb";
 322		status = "disabled";
 323	};
 324
 325	usb_host1_ehci: usb@fd880000 {
 326		compatible = "generic-ehci";
 327		reg = <0x0 0xfd880000 0x0 0x40000>;
 328		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 329		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 330			 <&cru PCLK_USB>;
 331		phys = <&usb2phy1_host>;
 332		phy-names = "usb";
 333		status = "disabled";
 334	};
 335
 336	usb_host1_ohci: usb@fd8c0000 {
 337		compatible = "generic-ohci";
 338		reg = <0x0 0xfd8c0000 0x0 0x40000>;
 339		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 340		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 341			 <&cru PCLK_USB>;
 342		phys = <&usb2phy1_host>;
 343		phy-names = "usb";
 344		status = "disabled";
 345	};
 346
 347	pmugrf: syscon@fdc20000 {
 348		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
 349		reg = <0x0 0xfdc20000 0x0 0x10000>;
 350
 351		pmu_io_domains: io-domains {
 352			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
 353			status = "disabled";
 354		};
 355	};
 356
 357	pipegrf: syscon@fdc50000 {
 358		reg = <0x0 0xfdc50000 0x0 0x1000>;
 359	};
 360
 361	grf: syscon@fdc60000 {
 362		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 363		reg = <0x0 0xfdc60000 0x0 0x10000>;
 364	};
 365
 366	pipe_phy_grf1: syscon@fdc80000 {
 367		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 368		reg = <0x0 0xfdc80000 0x0 0x1000>;
 369	};
 370
 371	pipe_phy_grf2: syscon@fdc90000 {
 372		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 373		reg = <0x0 0xfdc90000 0x0 0x1000>;
 374	};
 375
 376	usb2phy0_grf: syscon@fdca0000 {
 377		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 378		reg = <0x0 0xfdca0000 0x0 0x8000>;
 379	};
 380
 381	usb2phy1_grf: syscon@fdca8000 {
 382		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 383		reg = <0x0 0xfdca8000 0x0 0x8000>;
 384	};
 385
 386	pmucru: clock-controller@fdd00000 {
 387		compatible = "rockchip,rk3568-pmucru";
 388		reg = <0x0 0xfdd00000 0x0 0x1000>;
 389		#clock-cells = <1>;
 390		#reset-cells = <1>;
 391	};
 392
 393	cru: clock-controller@fdd20000 {
 394		compatible = "rockchip,rk3568-cru";
 395		reg = <0x0 0xfdd20000 0x0 0x1000>;
 396		clocks = <&xin24m>;
 397		clock-names = "xin24m";
 398		#clock-cells = <1>;
 399		#reset-cells = <1>;
 400		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
 401		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
 402		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
 403		rockchip,grf = <&grf>;
 404	};
 405
 406	i2c0: i2c@fdd40000 {
 407		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 408		reg = <0x0 0xfdd40000 0x0 0x1000>;
 409		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 410		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
 411		clock-names = "i2c", "pclk";
 412		pinctrl-0 = <&i2c0_xfer>;
 413		pinctrl-names = "default";
 414		#address-cells = <1>;
 415		#size-cells = <0>;
 416		status = "disabled";
 417	};
 418
 419	uart0: serial@fdd50000 {
 420		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 421		reg = <0x0 0xfdd50000 0x0 0x100>;
 422		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 423		clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
 424		clock-names = "baudclk", "apb_pclk";
 425		dmas = <&dmac0 0>, <&dmac0 1>;
 426		pinctrl-0 = <&uart0_xfer>;
 427		pinctrl-names = "default";
 428		reg-io-width = <4>;
 429		reg-shift = <2>;
 430		status = "disabled";
 431	};
 432
 433	pwm0: pwm@fdd70000 {
 434		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 435		reg = <0x0 0xfdd70000 0x0 0x10>;
 436		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 437		clock-names = "pwm", "pclk";
 438		pinctrl-0 = <&pwm0m0_pins>;
 439		pinctrl-names = "default";
 440		#pwm-cells = <3>;
 441		status = "disabled";
 442	};
 443
 444	pwm1: pwm@fdd70010 {
 445		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 446		reg = <0x0 0xfdd70010 0x0 0x10>;
 447		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 448		clock-names = "pwm", "pclk";
 449		pinctrl-0 = <&pwm1m0_pins>;
 450		pinctrl-names = "default";
 451		#pwm-cells = <3>;
 452		status = "disabled";
 453	};
 454
 455	pwm2: pwm@fdd70020 {
 456		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 457		reg = <0x0 0xfdd70020 0x0 0x10>;
 458		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 459		clock-names = "pwm", "pclk";
 460		pinctrl-0 = <&pwm2m0_pins>;
 461		pinctrl-names = "default";
 462		#pwm-cells = <3>;
 463		status = "disabled";
 464	};
 465
 466	pwm3: pwm@fdd70030 {
 467		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 468		reg = <0x0 0xfdd70030 0x0 0x10>;
 469		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 470		clock-names = "pwm", "pclk";
 471		pinctrl-0 = <&pwm3_pins>;
 472		pinctrl-names = "default";
 473		#pwm-cells = <3>;
 474		status = "disabled";
 475	};
 476
 477	pmu: power-management@fdd90000 {
 478		compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
 479		reg = <0x0 0xfdd90000 0x0 0x1000>;
 480
 481		power: power-controller {
 482			compatible = "rockchip,rk3568-power-controller";
 483			#power-domain-cells = <1>;
 484			#address-cells = <1>;
 485			#size-cells = <0>;
 486
 487			/* These power domains are grouped by VD_GPU */
 488			power-domain@RK3568_PD_GPU {
 489				reg = <RK3568_PD_GPU>;
 490				clocks = <&cru ACLK_GPU_PRE>,
 491					 <&cru PCLK_GPU_PRE>;
 492				pm_qos = <&qos_gpu>;
 493				#power-domain-cells = <0>;
 494			};
 495
 496			/* These power domains are grouped by VD_LOGIC */
 497			power-domain@RK3568_PD_VI {
 498				reg = <RK3568_PD_VI>;
 499				clocks = <&cru HCLK_VI>,
 500					 <&cru PCLK_VI>;
 501				pm_qos = <&qos_isp>,
 502					 <&qos_vicap0>,
 503					 <&qos_vicap1>;
 504				#power-domain-cells = <0>;
 505			};
 506
 507			power-domain@RK3568_PD_VO {
 508				reg = <RK3568_PD_VO>;
 509				clocks = <&cru HCLK_VO>,
 510					 <&cru PCLK_VO>,
 511					 <&cru ACLK_VOP_PRE>;
 512				pm_qos = <&qos_hdcp>,
 513					 <&qos_vop_m0>,
 514					 <&qos_vop_m1>;
 515				#power-domain-cells = <0>;
 516			};
 517
 518			power-domain@RK3568_PD_RGA {
 519				reg = <RK3568_PD_RGA>;
 520				clocks = <&cru HCLK_RGA_PRE>,
 521					 <&cru PCLK_RGA_PRE>;
 522				pm_qos = <&qos_ebc>,
 523					 <&qos_iep>,
 524					 <&qos_jpeg_dec>,
 525					 <&qos_jpeg_enc>,
 526					 <&qos_rga_rd>,
 527					 <&qos_rga_wr>;
 528				#power-domain-cells = <0>;
 529			};
 530
 531			power-domain@RK3568_PD_VPU {
 532				reg = <RK3568_PD_VPU>;
 533				clocks = <&cru HCLK_VPU_PRE>;
 534				pm_qos = <&qos_vpu>;
 535				#power-domain-cells = <0>;
 536			};
 537
 538			power-domain@RK3568_PD_RKVDEC {
 539				clocks = <&cru HCLK_RKVDEC_PRE>;
 540				reg = <RK3568_PD_RKVDEC>;
 541				pm_qos = <&qos_rkvdec>;
 542				#power-domain-cells = <0>;
 543			};
 544
 545			power-domain@RK3568_PD_RKVENC {
 546				reg = <RK3568_PD_RKVENC>;
 547				clocks = <&cru HCLK_RKVENC_PRE>;
 548				pm_qos = <&qos_rkvenc_rd_m0>,
 549					 <&qos_rkvenc_rd_m1>,
 550					 <&qos_rkvenc_wr_m0>;
 551				#power-domain-cells = <0>;
 552			};
 553		};
 554	};
 555
 556	gpu: gpu@fde60000 {
 557		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
 558		reg = <0x0 0xfde60000 0x0 0x4000>;
 559		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 560			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 561			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 562		interrupt-names = "job", "mmu", "gpu";
 563		clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU>;
 564		clock-names = "gpu", "bus";
 565		#cooling-cells = <2>;
 566		power-domains = <&power RK3568_PD_GPU>;
 567		status = "disabled";
 568	};
 569
 570	vpu: video-codec@fdea0400 {
 571		compatible = "rockchip,rk3568-vpu";
 572		reg = <0x0 0xfdea0000 0x0 0x800>;
 573		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 574		interrupt-names = "vdpu";
 575		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 576		clock-names = "aclk", "hclk";
 577		iommus = <&vdpu_mmu>;
 578		power-domains = <&power RK3568_PD_VPU>;
 579	};
 580
 581	vdpu_mmu: iommu@fdea0800 {
 582		compatible = "rockchip,rk3568-iommu";
 583		reg = <0x0 0xfdea0800 0x0 0x40>;
 584		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 585		clock-names = "aclk", "iface";
 586		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 587		power-domains = <&power RK3568_PD_VPU>;
 588		#iommu-cells = <0>;
 589	};
 590
 591	rga: rga@fdeb0000 {
 592		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
 593		reg = <0x0 0xfdeb0000 0x0 0x180>;
 594		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 595		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
 596		clock-names = "aclk", "hclk", "sclk";
 597		resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 598		reset-names = "core", "axi", "ahb";
 599		power-domains = <&power RK3568_PD_RGA>;
 600	};
 601
 602	vepu: video-codec@fdee0000 {
 603		compatible = "rockchip,rk3568-vepu";
 604		reg = <0x0 0xfdee0000 0x0 0x800>;
 605		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 606		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 607		clock-names = "aclk", "hclk";
 608		iommus = <&vepu_mmu>;
 609		power-domains = <&power RK3568_PD_RGA>;
 610	};
 611
 612	vepu_mmu: iommu@fdee0800 {
 613		compatible = "rockchip,rk3568-iommu";
 614		reg = <0x0 0xfdee0800 0x0 0x40>;
 615		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 616		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 617		clock-names = "aclk", "iface";
 618		power-domains = <&power RK3568_PD_RGA>;
 619		#iommu-cells = <0>;
 620	};
 621
 622	vicap: video-capture@fdfe0000 {
 623		compatible = "rockchip,rk3568-vicap";
 624		reg = <0x0 0xfdfe0000 0x0 0x200>;
 625		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 626		assigned-clocks = <&cru DCLK_VICAP>;
 627		assigned-clock-rates = <300000000>;
 628		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
 629			 <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
 630		clock-names = "aclk", "hclk", "dclk", "iclk";
 631		iommus = <&vicap_mmu>;
 632		power-domains = <&power RK3568_PD_VI>;
 633		resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
 634			 <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
 635			 <&cru SRST_I_VICAP>;
 636		reset-names = "arst", "hrst", "drst", "prst", "irst";
 637		rockchip,grf = <&grf>;
 638		status = "disabled";
 639
 640		ports {
 641			#address-cells = <1>;
 642			#size-cells = <0>;
 643
 644			vicap_dvp: port@0 {
 645				reg = <0>;
 646			};
 647
 648			vicap_mipi: port@1 {
 649				reg = <1>;
 650			};
 651		};
 652	};
 653
 654	vicap_mmu: iommu@fdfe0800 {
 655		compatible = "rockchip,rk3568-iommu";
 656		reg = <0x0 0xfdfe0800 0x0 0x100>;
 657		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 658		clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
 659		clock-names = "aclk", "iface";
 660		#iommu-cells = <0>;
 661		power-domains = <&power RK3568_PD_VI>;
 662		rockchip,disable-mmu-reset;
 663		status = "disabled";
 664	};
 665
 666	sdmmc2: mmc@fe000000 {
 667		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 668		reg = <0x0 0xfe000000 0x0 0x4000>;
 669		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 670		clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
 671			 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
 672		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 673		fifo-depth = <0x100>;
 674		max-frequency = <150000000>;
 675		resets = <&cru SRST_SDMMC2>;
 676		reset-names = "reset";
 677		status = "disabled";
 678	};
 679
 680	gmac1: ethernet@fe010000 {
 681		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
 682		reg = <0x0 0xfe010000 0x0 0x10000>;
 683		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 684			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 685		interrupt-names = "macirq", "eth_wake_irq";
 686		clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
 687			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
 688			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
 689			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
 690		clock-names = "stmmaceth", "mac_clk_rx",
 691			      "mac_clk_tx", "clk_mac_refout",
 692			      "aclk_mac", "pclk_mac",
 693			      "clk_mac_speed", "ptp_ref";
 694		resets = <&cru SRST_A_GMAC1>;
 695		reset-names = "stmmaceth";
 696		rockchip,grf = <&grf>;
 697		snps,axi-config = <&gmac1_stmmac_axi_setup>;
 698		snps,mixed-burst;
 699		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
 700		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
 701		snps,tso;
 702		status = "disabled";
 703
 704		mdio1: mdio {
 705			compatible = "snps,dwmac-mdio";
 706			#address-cells = <0x1>;
 707			#size-cells = <0x0>;
 708		};
 709
 710		gmac1_stmmac_axi_setup: stmmac-axi-config {
 711			snps,blen = <0 0 0 0 16 8 4>;
 712			snps,rd_osr_lmt = <8>;
 713			snps,wr_osr_lmt = <4>;
 714		};
 715
 716		gmac1_mtl_rx_setup: rx-queues-config {
 717			snps,rx-queues-to-use = <1>;
 718			queue0 {};
 719		};
 720
 721		gmac1_mtl_tx_setup: tx-queues-config {
 722			snps,tx-queues-to-use = <1>;
 723			queue0 {};
 724		};
 725	};
 726
 727	vop: vop@fe040000 {
 728		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
 729		reg-names = "vop", "gamma-lut";
 730		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 731		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
 732			 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
 733		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
 734		iommus = <&vop_mmu>;
 735		power-domains = <&power RK3568_PD_VO>;
 736		rockchip,grf = <&grf>;
 737		status = "disabled";
 738
 739		vop_out: ports {
 740			#address-cells = <1>;
 741			#size-cells = <0>;
 742
 743			vp0: port@0 {
 744				reg = <0>;
 745				#address-cells = <1>;
 746				#size-cells = <0>;
 747			};
 748
 749			vp1: port@1 {
 750				reg = <1>;
 751				#address-cells = <1>;
 752				#size-cells = <0>;
 753			};
 754
 755			vp2: port@2 {
 756				reg = <2>;
 757				#address-cells = <1>;
 758				#size-cells = <0>;
 759			};
 760		};
 761	};
 762
 763	vop_mmu: iommu@fe043e00 {
 764		compatible = "rockchip,rk3568-iommu";
 765		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
 766		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 767		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 768		clock-names = "aclk", "iface";
 769		#iommu-cells = <0>;
 770		power-domains = <&power RK3568_PD_VO>;
 771		status = "disabled";
 772	};
 773
 774	dsi0: dsi@fe060000 {
 775		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 776		reg = <0x00 0xfe060000 0x00 0x10000>;
 777		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 778		clock-names = "pclk";
 779		clocks = <&cru PCLK_DSITX_0>;
 780		phy-names = "dphy";
 781		phys = <&dsi_dphy0>;
 782		power-domains = <&power RK3568_PD_VO>;
 783		reset-names = "apb";
 784		resets = <&cru SRST_P_DSITX_0>;
 785		rockchip,grf = <&grf>;
 786		status = "disabled";
 787
 788		ports {
 789			#address-cells = <1>;
 790			#size-cells = <0>;
 791
 792			dsi0_in: port@0 {
 793				reg = <0>;
 794			};
 795
 796			dsi0_out: port@1 {
 797				reg = <1>;
 798			};
 799		};
 800	};
 801
 802	dsi1: dsi@fe070000 {
 803		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 804		reg = <0x0 0xfe070000 0x0 0x10000>;
 805		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 806		clock-names = "pclk";
 807		clocks = <&cru PCLK_DSITX_1>;
 808		phy-names = "dphy";
 809		phys = <&dsi_dphy1>;
 810		power-domains = <&power RK3568_PD_VO>;
 811		reset-names = "apb";
 812		resets = <&cru SRST_P_DSITX_1>;
 813		rockchip,grf = <&grf>;
 814		status = "disabled";
 815
 816		ports {
 817			#address-cells = <1>;
 818			#size-cells = <0>;
 819
 820			dsi1_in: port@0 {
 821				reg = <0>;
 822			};
 823
 824			dsi1_out: port@1 {
 825				reg = <1>;
 826			};
 827		};
 828	};
 829
 830	hdmi: hdmi@fe0a0000 {
 831		compatible = "rockchip,rk3568-dw-hdmi";
 832		reg = <0x0 0xfe0a0000 0x0 0x20000>;
 833		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 834		clocks = <&cru PCLK_HDMI_HOST>,
 835			 <&cru CLK_HDMI_SFR>,
 836			 <&cru CLK_HDMI_CEC>,
 837			 <&pmucru CLK_HDMI_REF>,
 838			 <&cru HCLK_VO>;
 839		clock-names = "iahb", "isfr", "cec", "ref";
 840		pinctrl-names = "default";
 841		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
 842		power-domains = <&power RK3568_PD_VO>;
 843		reg-io-width = <4>;
 844		rockchip,grf = <&grf>;
 845		#sound-dai-cells = <0>;
 846		status = "disabled";
 847
 848		ports {
 849			#address-cells = <1>;
 850			#size-cells = <0>;
 851
 852			hdmi_in: port@0 {
 853				reg = <0>;
 854			};
 855
 856			hdmi_out: port@1 {
 857				reg = <1>;
 858			};
 859		};
 860	};
 861
 862	qos_gpu: qos@fe128000 {
 863		compatible = "rockchip,rk3568-qos", "syscon";
 864		reg = <0x0 0xfe128000 0x0 0x20>;
 865	};
 866
 867	qos_rkvenc_rd_m0: qos@fe138080 {
 868		compatible = "rockchip,rk3568-qos", "syscon";
 869		reg = <0x0 0xfe138080 0x0 0x20>;
 870	};
 871
 872	qos_rkvenc_rd_m1: qos@fe138100 {
 873		compatible = "rockchip,rk3568-qos", "syscon";
 874		reg = <0x0 0xfe138100 0x0 0x20>;
 875	};
 876
 877	qos_rkvenc_wr_m0: qos@fe138180 {
 878		compatible = "rockchip,rk3568-qos", "syscon";
 879		reg = <0x0 0xfe138180 0x0 0x20>;
 880	};
 881
 882	qos_isp: qos@fe148000 {
 883		compatible = "rockchip,rk3568-qos", "syscon";
 884		reg = <0x0 0xfe148000 0x0 0x20>;
 885	};
 886
 887	qos_vicap0: qos@fe148080 {
 888		compatible = "rockchip,rk3568-qos", "syscon";
 889		reg = <0x0 0xfe148080 0x0 0x20>;
 890	};
 891
 892	qos_vicap1: qos@fe148100 {
 893		compatible = "rockchip,rk3568-qos", "syscon";
 894		reg = <0x0 0xfe148100 0x0 0x20>;
 895	};
 896
 897	qos_vpu: qos@fe150000 {
 898		compatible = "rockchip,rk3568-qos", "syscon";
 899		reg = <0x0 0xfe150000 0x0 0x20>;
 900	};
 901
 902	qos_ebc: qos@fe158000 {
 903		compatible = "rockchip,rk3568-qos", "syscon";
 904		reg = <0x0 0xfe158000 0x0 0x20>;
 905	};
 906
 907	qos_iep: qos@fe158100 {
 908		compatible = "rockchip,rk3568-qos", "syscon";
 909		reg = <0x0 0xfe158100 0x0 0x20>;
 910	};
 911
 912	qos_jpeg_dec: qos@fe158180 {
 913		compatible = "rockchip,rk3568-qos", "syscon";
 914		reg = <0x0 0xfe158180 0x0 0x20>;
 915	};
 916
 917	qos_jpeg_enc: qos@fe158200 {
 918		compatible = "rockchip,rk3568-qos", "syscon";
 919		reg = <0x0 0xfe158200 0x0 0x20>;
 920	};
 921
 922	qos_rga_rd: qos@fe158280 {
 923		compatible = "rockchip,rk3568-qos", "syscon";
 924		reg = <0x0 0xfe158280 0x0 0x20>;
 925	};
 926
 927	qos_rga_wr: qos@fe158300 {
 928		compatible = "rockchip,rk3568-qos", "syscon";
 929		reg = <0x0 0xfe158300 0x0 0x20>;
 930	};
 931
 932	qos_npu: qos@fe180000 {
 933		compatible = "rockchip,rk3568-qos", "syscon";
 934		reg = <0x0 0xfe180000 0x0 0x20>;
 935	};
 936
 937	qos_pcie2x1: qos@fe190000 {
 938		compatible = "rockchip,rk3568-qos", "syscon";
 939		reg = <0x0 0xfe190000 0x0 0x20>;
 940	};
 941
 942	qos_sata1: qos@fe190280 {
 943		compatible = "rockchip,rk3568-qos", "syscon";
 944		reg = <0x0 0xfe190280 0x0 0x20>;
 945	};
 946
 947	qos_sata2: qos@fe190300 {
 948		compatible = "rockchip,rk3568-qos", "syscon";
 949		reg = <0x0 0xfe190300 0x0 0x20>;
 950	};
 951
 952	qos_usb3_0: qos@fe190380 {
 953		compatible = "rockchip,rk3568-qos", "syscon";
 954		reg = <0x0 0xfe190380 0x0 0x20>;
 955	};
 956
 957	qos_usb3_1: qos@fe190400 {
 958		compatible = "rockchip,rk3568-qos", "syscon";
 959		reg = <0x0 0xfe190400 0x0 0x20>;
 960	};
 961
 962	qos_rkvdec: qos@fe198000 {
 963		compatible = "rockchip,rk3568-qos", "syscon";
 964		reg = <0x0 0xfe198000 0x0 0x20>;
 965	};
 966
 967	qos_hdcp: qos@fe1a8000 {
 968		compatible = "rockchip,rk3568-qos", "syscon";
 969		reg = <0x0 0xfe1a8000 0x0 0x20>;
 970	};
 971
 972	qos_vop_m0: qos@fe1a8080 {
 973		compatible = "rockchip,rk3568-qos", "syscon";
 974		reg = <0x0 0xfe1a8080 0x0 0x20>;
 975	};
 976
 977	qos_vop_m1: qos@fe1a8100 {
 978		compatible = "rockchip,rk3568-qos", "syscon";
 979		reg = <0x0 0xfe1a8100 0x0 0x20>;
 980	};
 981
 982	dfi: dfi@fe230000 {
 983		compatible = "rockchip,rk3568-dfi";
 984		reg = <0x00 0xfe230000 0x00 0x400>;
 985		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 986		rockchip,pmu = <&pmugrf>;
 987	};
 988
 989	pcie2x1: pcie@fe260000 {
 990		compatible = "rockchip,rk3568-pcie";
 991		reg = <0x3 0xc0000000 0x0 0x00400000>,
 992		      <0x0 0xfe260000 0x0 0x00010000>,
 993		      <0x0 0xf4000000 0x0 0x00100000>;
 994		reg-names = "dbi", "apb", "config";
 995		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 996			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 997			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 998			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 999			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1000		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1001		bus-range = <0x0 0xf>;
1002		clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
1003			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
1004			 <&cru CLK_PCIE20_AUX_NDFT>;
1005		clock-names = "aclk_mst", "aclk_slv",
1006			      "aclk_dbi", "pclk", "aux";
1007		device_type = "pci";
1008		#interrupt-cells = <1>;
1009		interrupt-map-mask = <0 0 0 7>;
1010		interrupt-map = <0 0 0 1 &pcie_intc 0>,
1011				<0 0 0 2 &pcie_intc 1>,
1012				<0 0 0 3 &pcie_intc 2>,
1013				<0 0 0 4 &pcie_intc 3>;
1014		linux,pci-domain = <0>;
1015		num-ib-windows = <6>;
1016		num-ob-windows = <2>;
1017		max-link-speed = <2>;
1018		msi-map = <0x0 &its 0x0 0x1000>;
1019		num-lanes = <1>;
1020		phys = <&combphy2 PHY_TYPE_PCIE>;
1021		phy-names = "pcie-phy";
1022		power-domains = <&power RK3568_PD_PIPE>;
1023		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1024			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
1025			 <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1026		resets = <&cru SRST_PCIE20_POWERUP>;
1027		reset-names = "pipe";
1028		#address-cells = <3>;
1029		#size-cells = <2>;
1030		status = "disabled";
1031
1032		pcie_intc: legacy-interrupt-controller {
1033			#address-cells = <0>;
1034			#interrupt-cells = <1>;
1035			interrupt-controller;
1036			interrupt-parent = <&gic>;
1037			interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
1038		};
1039	};
1040
1041	sdmmc0: mmc@fe2b0000 {
1042		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1043		reg = <0x0 0xfe2b0000 0x0 0x4000>;
1044		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1045		clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1046			 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1047		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1048		fifo-depth = <0x100>;
1049		max-frequency = <150000000>;
1050		resets = <&cru SRST_SDMMC0>;
1051		reset-names = "reset";
1052		status = "disabled";
1053	};
1054
1055	sdmmc1: mmc@fe2c0000 {
1056		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1057		reg = <0x0 0xfe2c0000 0x0 0x4000>;
1058		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1059		clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1060			 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1061		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1062		fifo-depth = <0x100>;
1063		max-frequency = <150000000>;
1064		resets = <&cru SRST_SDMMC1>;
1065		reset-names = "reset";
1066		status = "disabled";
1067	};
1068
1069	sfc: spi@fe300000 {
1070		compatible = "rockchip,sfc";
1071		reg = <0x0 0xfe300000 0x0 0x4000>;
1072		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1073		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1074		clock-names = "clk_sfc", "hclk_sfc";
1075		pinctrl-0 = <&fspi_pins>;
1076		pinctrl-names = "default";
1077		status = "disabled";
1078	};
1079
1080	sdhci: mmc@fe310000 {
1081		compatible = "rockchip,rk3568-dwcmshc";
1082		reg = <0x0 0xfe310000 0x0 0x10000>;
1083		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1084		assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1085		assigned-clock-rates = <200000000>, <24000000>;
1086		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1087			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1088			 <&cru TCLK_EMMC>;
1089		clock-names = "core", "bus", "axi", "block", "timer";
1090		status = "disabled";
1091	};
1092
1093	/*
1094	 * Testing showed that the HWRNG found in RK3566 produces unacceptably
1095	 * low quality of random data, so the HWRNG isn't enabled for all RK356x
1096	 * SoC variants despite its presence.
1097	 */
1098	rng: rng@fe388000 {
1099		compatible = "rockchip,rk3568-rng";
1100		reg = <0x0 0xfe388000 0x0 0x4000>;
1101		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
1102		clock-names = "core", "ahb";
1103		resets = <&cru SRST_TRNG_NS>;
1104		status = "disabled";
1105	};
1106
1107	i2s0_8ch: i2s@fe400000 {
1108		compatible = "rockchip,rk3568-i2s-tdm";
1109		reg = <0x0 0xfe400000 0x0 0x1000>;
1110		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1111		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1112		assigned-clock-rates = <1188000000>, <1188000000>;
1113		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1114		clock-names = "mclk_tx", "mclk_rx", "hclk";
1115		dmas = <&dmac1 0>;
1116		dma-names = "tx";
1117		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1118		reset-names = "tx-m", "rx-m";
1119		rockchip,grf = <&grf>;
1120		#sound-dai-cells = <0>;
1121		status = "disabled";
1122	};
1123
1124	i2s1_8ch: i2s@fe410000 {
1125		compatible = "rockchip,rk3568-i2s-tdm";
1126		reg = <0x0 0xfe410000 0x0 0x1000>;
1127		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1128		assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1129		assigned-clock-rates = <1188000000>, <1188000000>;
1130		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1131			 <&cru HCLK_I2S1_8CH>;
1132		clock-names = "mclk_tx", "mclk_rx", "hclk";
1133		dmas = <&dmac1 3>, <&dmac1 2>;
1134		dma-names = "rx", "tx";
1135		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1136		reset-names = "tx-m", "rx-m";
1137		rockchip,grf = <&grf>;
1138		pinctrl-names = "default";
1139		pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1140			     &i2s1m0_lrcktx &i2s1m0_lrckrx
1141			     &i2s1m0_sdi0   &i2s1m0_sdi1
1142			     &i2s1m0_sdi2   &i2s1m0_sdi3
1143			     &i2s1m0_sdo0   &i2s1m0_sdo1
1144			     &i2s1m0_sdo2   &i2s1m0_sdo3>;
1145		#sound-dai-cells = <0>;
1146		status = "disabled";
1147	};
1148
1149	i2s2_2ch: i2s@fe420000 {
1150		compatible = "rockchip,rk3568-i2s-tdm";
1151		reg = <0x0 0xfe420000 0x0 0x1000>;
1152		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1153		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1154		assigned-clock-rates = <1188000000>;
1155		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1156		clock-names = "mclk_tx", "mclk_rx", "hclk";
1157		dmas = <&dmac1 4>, <&dmac1 5>;
1158		dma-names = "tx", "rx";
1159		resets = <&cru SRST_M_I2S2_2CH>;
1160		reset-names = "tx-m";
1161		rockchip,grf = <&grf>;
1162		pinctrl-names = "default";
1163		pinctrl-0 = <&i2s2m0_sclktx
1164				&i2s2m0_lrcktx
1165				&i2s2m0_sdi
1166				&i2s2m0_sdo>;
1167		#sound-dai-cells = <0>;
1168		status = "disabled";
1169	};
1170
1171	i2s3_2ch: i2s@fe430000 {
1172		compatible = "rockchip,rk3568-i2s-tdm";
1173		reg = <0x0 0xfe430000 0x0 0x1000>;
1174		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1175		clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1176			 <&cru HCLK_I2S3_2CH>;
1177		clock-names = "mclk_tx", "mclk_rx", "hclk";
1178		dmas = <&dmac1 6>, <&dmac1 7>;
1179		dma-names = "tx", "rx";
1180		resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1181		reset-names = "tx-m", "rx-m";
1182		rockchip,grf = <&grf>;
1183		#sound-dai-cells = <0>;
1184		status = "disabled";
1185	};
1186
1187	pdm: pdm@fe440000 {
1188		compatible = "rockchip,rk3568-pdm";
1189		reg = <0x0 0xfe440000 0x0 0x1000>;
1190		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1191		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1192		clock-names = "pdm_clk", "pdm_hclk";
1193		dmas = <&dmac1 9>;
1194		dma-names = "rx";
1195		pinctrl-0 = <&pdmm0_clk
1196			     &pdmm0_clk1
1197			     &pdmm0_sdi0
1198			     &pdmm0_sdi1
1199			     &pdmm0_sdi2
1200			     &pdmm0_sdi3>;
1201		pinctrl-names = "default";
1202		resets = <&cru SRST_M_PDM>;
1203		reset-names = "pdm-m";
1204		#sound-dai-cells = <0>;
1205		status = "disabled";
1206	};
1207
1208	spdif: spdif@fe460000 {
1209		compatible = "rockchip,rk3568-spdif";
1210		reg = <0x0 0xfe460000 0x0 0x1000>;
1211		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1212		clock-names = "mclk", "hclk";
1213		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1214		dmas = <&dmac1 1>;
1215		dma-names = "tx";
1216		pinctrl-names = "default";
1217		pinctrl-0 = <&spdifm0_tx>;
1218		#sound-dai-cells = <0>;
1219		status = "disabled";
1220	};
1221
1222	dmac0: dma-controller@fe530000 {
1223		compatible = "arm,pl330", "arm,primecell";
1224		reg = <0x0 0xfe530000 0x0 0x4000>;
1225		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1226			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1227		arm,pl330-periph-burst;
1228		clocks = <&cru ACLK_BUS>;
1229		clock-names = "apb_pclk";
1230		#dma-cells = <1>;
1231	};
1232
1233	dmac1: dma-controller@fe550000 {
1234		compatible = "arm,pl330", "arm,primecell";
1235		reg = <0x0 0xfe550000 0x0 0x4000>;
1236		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1237			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1238		arm,pl330-periph-burst;
1239		clocks = <&cru ACLK_BUS>;
1240		clock-names = "apb_pclk";
1241		#dma-cells = <1>;
1242	};
1243
1244	i2c1: i2c@fe5a0000 {
1245		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1246		reg = <0x0 0xfe5a0000 0x0 0x1000>;
1247		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1248		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1249		clock-names = "i2c", "pclk";
1250		pinctrl-0 = <&i2c1_xfer>;
1251		pinctrl-names = "default";
1252		#address-cells = <1>;
1253		#size-cells = <0>;
1254		status = "disabled";
1255	};
1256
1257	i2c2: i2c@fe5b0000 {
1258		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1259		reg = <0x0 0xfe5b0000 0x0 0x1000>;
1260		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1261		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1262		clock-names = "i2c", "pclk";
1263		pinctrl-0 = <&i2c2m0_xfer>;
1264		pinctrl-names = "default";
1265		#address-cells = <1>;
1266		#size-cells = <0>;
1267		status = "disabled";
1268	};
1269
1270	i2c3: i2c@fe5c0000 {
1271		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1272		reg = <0x0 0xfe5c0000 0x0 0x1000>;
1273		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1274		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1275		clock-names = "i2c", "pclk";
1276		pinctrl-0 = <&i2c3m0_xfer>;
1277		pinctrl-names = "default";
1278		#address-cells = <1>;
1279		#size-cells = <0>;
1280		status = "disabled";
1281	};
1282
1283	i2c4: i2c@fe5d0000 {
1284		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1285		reg = <0x0 0xfe5d0000 0x0 0x1000>;
1286		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1287		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1288		clock-names = "i2c", "pclk";
1289		pinctrl-0 = <&i2c4m0_xfer>;
1290		pinctrl-names = "default";
1291		#address-cells = <1>;
1292		#size-cells = <0>;
1293		status = "disabled";
1294	};
1295
1296	i2c5: i2c@fe5e0000 {
1297		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1298		reg = <0x0 0xfe5e0000 0x0 0x1000>;
1299		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1300		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1301		clock-names = "i2c", "pclk";
1302		pinctrl-0 = <&i2c5m0_xfer>;
1303		pinctrl-names = "default";
1304		#address-cells = <1>;
1305		#size-cells = <0>;
1306		status = "disabled";
1307	};
1308
1309	wdt: watchdog@fe600000 {
1310		compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1311		reg = <0x0 0xfe600000 0x0 0x100>;
1312		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1313		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1314		clock-names = "tclk", "pclk";
1315	};
1316
1317	spi0: spi@fe610000 {
1318		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1319		reg = <0x0 0xfe610000 0x0 0x1000>;
1320		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1321		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1322		clock-names = "spiclk", "apb_pclk";
1323		dmas = <&dmac0 20>, <&dmac0 21>;
1324		dma-names = "tx", "rx";
1325		pinctrl-names = "default";
1326		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1327		#address-cells = <1>;
1328		#size-cells = <0>;
1329		status = "disabled";
1330	};
1331
1332	spi1: spi@fe620000 {
1333		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1334		reg = <0x0 0xfe620000 0x0 0x1000>;
1335		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1336		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1337		clock-names = "spiclk", "apb_pclk";
1338		dmas = <&dmac0 22>, <&dmac0 23>;
1339		dma-names = "tx", "rx";
1340		pinctrl-names = "default";
1341		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1342		#address-cells = <1>;
1343		#size-cells = <0>;
1344		status = "disabled";
1345	};
1346
1347	spi2: spi@fe630000 {
1348		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1349		reg = <0x0 0xfe630000 0x0 0x1000>;
1350		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1351		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1352		clock-names = "spiclk", "apb_pclk";
1353		dmas = <&dmac0 24>, <&dmac0 25>;
1354		dma-names = "tx", "rx";
1355		pinctrl-names = "default";
1356		pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1357		#address-cells = <1>;
1358		#size-cells = <0>;
1359		status = "disabled";
1360	};
1361
1362	spi3: spi@fe640000 {
1363		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1364		reg = <0x0 0xfe640000 0x0 0x1000>;
1365		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1366		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1367		clock-names = "spiclk", "apb_pclk";
1368		dmas = <&dmac0 26>, <&dmac0 27>;
1369		dma-names = "tx", "rx";
1370		pinctrl-names = "default";
1371		pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1372		#address-cells = <1>;
1373		#size-cells = <0>;
1374		status = "disabled";
1375	};
1376
1377	uart1: serial@fe650000 {
1378		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1379		reg = <0x0 0xfe650000 0x0 0x100>;
1380		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1381		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1382		clock-names = "baudclk", "apb_pclk";
1383		dmas = <&dmac0 2>, <&dmac0 3>;
1384		pinctrl-0 = <&uart1m0_xfer>;
1385		pinctrl-names = "default";
1386		reg-io-width = <4>;
1387		reg-shift = <2>;
1388		status = "disabled";
1389	};
1390
1391	uart2: serial@fe660000 {
1392		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1393		reg = <0x0 0xfe660000 0x0 0x100>;
1394		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1395		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1396		clock-names = "baudclk", "apb_pclk";
1397		dmas = <&dmac0 4>, <&dmac0 5>;
1398		pinctrl-0 = <&uart2m0_xfer>;
1399		pinctrl-names = "default";
1400		reg-io-width = <4>;
1401		reg-shift = <2>;
1402		status = "disabled";
1403	};
1404
1405	uart3: serial@fe670000 {
1406		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1407		reg = <0x0 0xfe670000 0x0 0x100>;
1408		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1409		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1410		clock-names = "baudclk", "apb_pclk";
1411		dmas = <&dmac0 6>, <&dmac0 7>;
1412		pinctrl-0 = <&uart3m0_xfer>;
1413		pinctrl-names = "default";
1414		reg-io-width = <4>;
1415		reg-shift = <2>;
1416		status = "disabled";
1417	};
1418
1419	uart4: serial@fe680000 {
1420		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1421		reg = <0x0 0xfe680000 0x0 0x100>;
1422		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1423		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1424		clock-names = "baudclk", "apb_pclk";
1425		dmas = <&dmac0 8>, <&dmac0 9>;
1426		pinctrl-0 = <&uart4m0_xfer>;
1427		pinctrl-names = "default";
1428		reg-io-width = <4>;
1429		reg-shift = <2>;
1430		status = "disabled";
1431	};
1432
1433	uart5: serial@fe690000 {
1434		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1435		reg = <0x0 0xfe690000 0x0 0x100>;
1436		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1437		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1438		clock-names = "baudclk", "apb_pclk";
1439		dmas = <&dmac0 10>, <&dmac0 11>;
1440		pinctrl-0 = <&uart5m0_xfer>;
1441		pinctrl-names = "default";
1442		reg-io-width = <4>;
1443		reg-shift = <2>;
1444		status = "disabled";
1445	};
1446
1447	uart6: serial@fe6a0000 {
1448		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1449		reg = <0x0 0xfe6a0000 0x0 0x100>;
1450		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1451		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1452		clock-names = "baudclk", "apb_pclk";
1453		dmas = <&dmac0 12>, <&dmac0 13>;
1454		pinctrl-0 = <&uart6m0_xfer>;
1455		pinctrl-names = "default";
1456		reg-io-width = <4>;
1457		reg-shift = <2>;
1458		status = "disabled";
1459	};
1460
1461	uart7: serial@fe6b0000 {
1462		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1463		reg = <0x0 0xfe6b0000 0x0 0x100>;
1464		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1465		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1466		clock-names = "baudclk", "apb_pclk";
1467		dmas = <&dmac0 14>, <&dmac0 15>;
1468		pinctrl-0 = <&uart7m0_xfer>;
1469		pinctrl-names = "default";
1470		reg-io-width = <4>;
1471		reg-shift = <2>;
1472		status = "disabled";
1473	};
1474
1475	uart8: serial@fe6c0000 {
1476		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1477		reg = <0x0 0xfe6c0000 0x0 0x100>;
1478		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1479		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1480		clock-names = "baudclk", "apb_pclk";
1481		dmas = <&dmac0 16>, <&dmac0 17>;
1482		pinctrl-0 = <&uart8m0_xfer>;
1483		pinctrl-names = "default";
1484		reg-io-width = <4>;
1485		reg-shift = <2>;
1486		status = "disabled";
1487	};
1488
1489	uart9: serial@fe6d0000 {
1490		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1491		reg = <0x0 0xfe6d0000 0x0 0x100>;
1492		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1493		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1494		clock-names = "baudclk", "apb_pclk";
1495		dmas = <&dmac0 18>, <&dmac0 19>;
1496		pinctrl-0 = <&uart9m0_xfer>;
1497		pinctrl-names = "default";
1498		reg-io-width = <4>;
1499		reg-shift = <2>;
1500		status = "disabled";
1501	};
1502
1503	thermal_zones: thermal-zones {
1504		cpu_thermal: cpu-thermal {
1505			polling-delay-passive = <100>;
1506			polling-delay = <1000>;
1507
1508			thermal-sensors = <&tsadc 0>;
1509
1510			trips {
1511				cpu_alert0: cpu_alert0 {
1512					temperature = <70000>;
1513					hysteresis = <2000>;
1514					type = "passive";
1515				};
1516				cpu_alert1: cpu_alert1 {
1517					temperature = <75000>;
1518					hysteresis = <2000>;
1519					type = "passive";
1520				};
1521				cpu_crit: cpu_crit {
1522					temperature = <95000>;
1523					hysteresis = <2000>;
1524					type = "critical";
1525				};
1526			};
1527
1528			cooling-maps {
1529				map0 {
1530					trip = <&cpu_alert0>;
1531					cooling-device =
1532						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1533						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1534						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1535						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1536				};
1537			};
1538		};
1539
1540		gpu_thermal: gpu-thermal {
1541			polling-delay-passive = <20>; /* milliseconds */
1542			polling-delay = <1000>; /* milliseconds */
1543
1544			thermal-sensors = <&tsadc 1>;
1545
1546			trips {
1547				gpu_threshold: gpu-threshold {
1548					temperature = <70000>;
1549					hysteresis = <2000>;
1550					type = "passive";
1551				};
1552				gpu_target: gpu-target {
1553					temperature = <75000>;
1554					hysteresis = <2000>;
1555					type = "passive";
1556				};
1557				gpu_crit: gpu-crit {
1558					temperature = <95000>;
1559					hysteresis = <2000>;
1560					type = "critical";
1561				};
1562			};
1563
1564			cooling-maps {
1565				map0 {
1566					trip = <&gpu_target>;
1567					cooling-device =
1568						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1569				};
1570			};
1571		};
1572	};
1573
1574	tsadc: tsadc@fe710000 {
1575		compatible = "rockchip,rk3568-tsadc";
1576		reg = <0x0 0xfe710000 0x0 0x100>;
1577		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1578		assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1579		assigned-clock-rates = <17000000>, <700000>;
1580		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1581		clock-names = "tsadc", "apb_pclk";
1582		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1583			 <&cru SRST_TSADCPHY>;
1584		rockchip,grf = <&grf>;
1585		rockchip,hw-tshut-temp = <95000>;
1586		pinctrl-names = "default", "sleep";
1587		pinctrl-0 = <&tsadc_shutorg>;
1588		pinctrl-1 = <&tsadc_pin>;
1589		#thermal-sensor-cells = <1>;
1590		status = "disabled";
1591	};
1592
1593	saradc: saradc@fe720000 {
1594		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1595		reg = <0x0 0xfe720000 0x0 0x100>;
1596		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1597		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1598		clock-names = "saradc", "apb_pclk";
1599		resets = <&cru SRST_P_SARADC>;
1600		reset-names = "saradc-apb";
1601		#io-channel-cells = <1>;
1602		status = "disabled";
1603	};
1604
1605	pwm4: pwm@fe6e0000 {
1606		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1607		reg = <0x0 0xfe6e0000 0x0 0x10>;
1608		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1609		clock-names = "pwm", "pclk";
1610		pinctrl-0 = <&pwm4_pins>;
1611		pinctrl-names = "default";
1612		#pwm-cells = <3>;
1613		status = "disabled";
1614	};
1615
1616	pwm5: pwm@fe6e0010 {
1617		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1618		reg = <0x0 0xfe6e0010 0x0 0x10>;
1619		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1620		clock-names = "pwm", "pclk";
1621		pinctrl-0 = <&pwm5_pins>;
1622		pinctrl-names = "default";
1623		#pwm-cells = <3>;
1624		status = "disabled";
1625	};
1626
1627	pwm6: pwm@fe6e0020 {
1628		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1629		reg = <0x0 0xfe6e0020 0x0 0x10>;
1630		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1631		clock-names = "pwm", "pclk";
1632		pinctrl-0 = <&pwm6_pins>;
1633		pinctrl-names = "default";
1634		#pwm-cells = <3>;
1635		status = "disabled";
1636	};
1637
1638	pwm7: pwm@fe6e0030 {
1639		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1640		reg = <0x0 0xfe6e0030 0x0 0x10>;
1641		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1642		clock-names = "pwm", "pclk";
1643		pinctrl-0 = <&pwm7_pins>;
1644		pinctrl-names = "default";
1645		#pwm-cells = <3>;
1646		status = "disabled";
1647	};
1648
1649	pwm8: pwm@fe6f0000 {
1650		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1651		reg = <0x0 0xfe6f0000 0x0 0x10>;
1652		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1653		clock-names = "pwm", "pclk";
1654		pinctrl-0 = <&pwm8m0_pins>;
1655		pinctrl-names = "default";
1656		#pwm-cells = <3>;
1657		status = "disabled";
1658	};
1659
1660	pwm9: pwm@fe6f0010 {
1661		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1662		reg = <0x0 0xfe6f0010 0x0 0x10>;
1663		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1664		clock-names = "pwm", "pclk";
1665		pinctrl-0 = <&pwm9m0_pins>;
1666		pinctrl-names = "default";
1667		#pwm-cells = <3>;
1668		status = "disabled";
1669	};
1670
1671	pwm10: pwm@fe6f0020 {
1672		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1673		reg = <0x0 0xfe6f0020 0x0 0x10>;
1674		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1675		clock-names = "pwm", "pclk";
1676		pinctrl-0 = <&pwm10m0_pins>;
1677		pinctrl-names = "default";
1678		#pwm-cells = <3>;
1679		status = "disabled";
1680	};
1681
1682	pwm11: pwm@fe6f0030 {
1683		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1684		reg = <0x0 0xfe6f0030 0x0 0x10>;
1685		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1686		clock-names = "pwm", "pclk";
1687		pinctrl-0 = <&pwm11m0_pins>;
1688		pinctrl-names = "default";
1689		#pwm-cells = <3>;
1690		status = "disabled";
1691	};
1692
1693	pwm12: pwm@fe700000 {
1694		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1695		reg = <0x0 0xfe700000 0x0 0x10>;
1696		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1697		clock-names = "pwm", "pclk";
1698		pinctrl-0 = <&pwm12m0_pins>;
1699		pinctrl-names = "default";
1700		#pwm-cells = <3>;
1701		status = "disabled";
1702	};
1703
1704	pwm13: pwm@fe700010 {
1705		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1706		reg = <0x0 0xfe700010 0x0 0x10>;
1707		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1708		clock-names = "pwm", "pclk";
1709		pinctrl-0 = <&pwm13m0_pins>;
1710		pinctrl-names = "default";
1711		#pwm-cells = <3>;
1712		status = "disabled";
1713	};
1714
1715	pwm14: pwm@fe700020 {
1716		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1717		reg = <0x0 0xfe700020 0x0 0x10>;
1718		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1719		clock-names = "pwm", "pclk";
1720		pinctrl-0 = <&pwm14m0_pins>;
1721		pinctrl-names = "default";
1722		#pwm-cells = <3>;
1723		status = "disabled";
1724	};
1725
1726	pwm15: pwm@fe700030 {
1727		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1728		reg = <0x0 0xfe700030 0x0 0x10>;
1729		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1730		clock-names = "pwm", "pclk";
1731		pinctrl-0 = <&pwm15m0_pins>;
1732		pinctrl-names = "default";
1733		#pwm-cells = <3>;
1734		status = "disabled";
1735	};
1736
1737	combphy1: phy@fe830000 {
1738		compatible = "rockchip,rk3568-naneng-combphy";
1739		reg = <0x0 0xfe830000 0x0 0x100>;
1740		clocks = <&pmucru CLK_PCIEPHY1_REF>,
1741			 <&cru PCLK_PIPEPHY1>,
1742			 <&cru PCLK_PIPE>;
1743		clock-names = "ref", "apb", "pipe";
1744		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1745		assigned-clock-rates = <100000000>;
1746		resets = <&cru SRST_PIPEPHY1>;
1747		reset-names = "phy";
1748		rockchip,pipe-grf = <&pipegrf>;
1749		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1750		#phy-cells = <1>;
1751		status = "disabled";
1752	};
1753
1754	combphy2: phy@fe840000 {
1755		compatible = "rockchip,rk3568-naneng-combphy";
1756		reg = <0x0 0xfe840000 0x0 0x100>;
1757		clocks = <&pmucru CLK_PCIEPHY2_REF>,
1758			 <&cru PCLK_PIPEPHY2>,
1759			 <&cru PCLK_PIPE>;
1760		clock-names = "ref", "apb", "pipe";
1761		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1762		assigned-clock-rates = <100000000>;
1763		resets = <&cru SRST_PIPEPHY2>;
1764		reset-names = "phy";
1765		rockchip,pipe-grf = <&pipegrf>;
1766		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1767		#phy-cells = <1>;
1768		status = "disabled";
1769	};
1770
1771	csi_dphy: phy@fe870000 {
1772		compatible = "rockchip,rk3568-csi-dphy";
1773		reg = <0x0 0xfe870000 0x0 0x10000>;
1774		clocks = <&cru PCLK_MIPICSIPHY>;
1775		clock-names = "pclk";
1776		#phy-cells = <0>;
1777		resets = <&cru SRST_P_MIPICSIPHY>;
1778		reset-names = "apb";
1779		rockchip,grf = <&grf>;
1780		status = "disabled";
1781	};
1782
1783	dsi_dphy0: mipi-dphy@fe850000 {
1784		compatible = "rockchip,rk3568-dsi-dphy";
1785		reg = <0x0 0xfe850000 0x0 0x10000>;
1786		clock-names = "ref", "pclk";
1787		clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1788		#phy-cells = <0>;
1789		power-domains = <&power RK3568_PD_VO>;
1790		reset-names = "apb";
1791		resets = <&cru SRST_P_MIPIDSIPHY0>;
1792		status = "disabled";
1793	};
1794
1795	dsi_dphy1: mipi-dphy@fe860000 {
1796		compatible = "rockchip,rk3568-dsi-dphy";
1797		reg = <0x0 0xfe860000 0x0 0x10000>;
1798		clock-names = "ref", "pclk";
1799		clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1800		#phy-cells = <0>;
1801		power-domains = <&power RK3568_PD_VO>;
1802		reset-names = "apb";
1803		resets = <&cru SRST_P_MIPIDSIPHY1>;
1804		status = "disabled";
1805	};
1806
1807	usb2phy0: usb2phy@fe8a0000 {
1808		compatible = "rockchip,rk3568-usb2phy";
1809		reg = <0x0 0xfe8a0000 0x0 0x10000>;
1810		clocks = <&pmucru CLK_USBPHY0_REF>;
1811		clock-names = "phyclk";
1812		clock-output-names = "clk_usbphy0_480m";
1813		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1814		rockchip,usbgrf = <&usb2phy0_grf>;
1815		#clock-cells = <0>;
1816		status = "disabled";
1817
1818		usb2phy0_host: host-port {
1819			#phy-cells = <0>;
1820			status = "disabled";
1821		};
1822
1823		usb2phy0_otg: otg-port {
1824			#phy-cells = <0>;
1825			status = "disabled";
1826		};
1827	};
1828
1829	usb2phy1: usb2phy@fe8b0000 {
1830		compatible = "rockchip,rk3568-usb2phy";
1831		reg = <0x0 0xfe8b0000 0x0 0x10000>;
1832		clocks = <&pmucru CLK_USBPHY1_REF>;
1833		clock-names = "phyclk";
1834		clock-output-names = "clk_usbphy1_480m";
1835		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1836		rockchip,usbgrf = <&usb2phy1_grf>;
1837		#clock-cells = <0>;
1838		status = "disabled";
1839
1840		usb2phy1_host: host-port {
1841			#phy-cells = <0>;
1842			status = "disabled";
1843		};
1844
1845		usb2phy1_otg: otg-port {
1846			#phy-cells = <0>;
1847			status = "disabled";
1848		};
1849	};
1850
1851	pinctrl: pinctrl {
1852		compatible = "rockchip,rk3568-pinctrl";
1853		rockchip,grf = <&grf>;
1854		rockchip,pmu = <&pmugrf>;
1855		#address-cells = <2>;
1856		#size-cells = <2>;
1857		ranges;
1858
1859		gpio0: gpio@fdd60000 {
1860			compatible = "rockchip,gpio-bank";
1861			reg = <0x0 0xfdd60000 0x0 0x100>;
1862			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1863			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1864			gpio-controller;
1865			gpio-ranges = <&pinctrl 0 0 32>;
1866			#gpio-cells = <2>;
1867			interrupt-controller;
1868			#interrupt-cells = <2>;
1869		};
1870
1871		gpio1: gpio@fe740000 {
1872			compatible = "rockchip,gpio-bank";
1873			reg = <0x0 0xfe740000 0x0 0x100>;
1874			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1875			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1876			gpio-controller;
1877			gpio-ranges = <&pinctrl 0 32 32>;
1878			#gpio-cells = <2>;
1879			interrupt-controller;
1880			#interrupt-cells = <2>;
1881		};
1882
1883		gpio2: gpio@fe750000 {
1884			compatible = "rockchip,gpio-bank";
1885			reg = <0x0 0xfe750000 0x0 0x100>;
1886			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1887			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1888			gpio-controller;
1889			gpio-ranges = <&pinctrl 0 64 32>;
1890			#gpio-cells = <2>;
1891			interrupt-controller;
1892			#interrupt-cells = <2>;
1893		};
1894
1895		gpio3: gpio@fe760000 {
1896			compatible = "rockchip,gpio-bank";
1897			reg = <0x0 0xfe760000 0x0 0x100>;
1898			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1899			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1900			gpio-controller;
1901			gpio-ranges = <&pinctrl 0 96 32>;
1902			#gpio-cells = <2>;
1903			interrupt-controller;
1904			#interrupt-cells = <2>;
1905		};
1906
1907		gpio4: gpio@fe770000 {
1908			compatible = "rockchip,gpio-bank";
1909			reg = <0x0 0xfe770000 0x0 0x100>;
1910			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1911			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1912			gpio-controller;
1913			gpio-ranges = <&pinctrl 0 128 32>;
1914			#gpio-cells = <2>;
1915			interrupt-controller;
1916			#interrupt-cells = <2>;
1917		};
1918	};
1919};
1920
1921#include "rk3568-pinctrl.dtsi"