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rk3562.dtsi
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linux-6.19.14/arch/arm64/boot/dts/rockchip/rk3562.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3562-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rockchip,rk3562-power.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/reset/rockchip,rk3562-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3562"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 }; 30 31 xin32k: clock-xin32k { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32768>; 35 clock-output-names = "xin32k"; 36 }; 37 38 xin24m: clock-xin24m { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <24000000>; 42 clock-output-names = "xin24m"; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 clocks = <&scmi_clk ARMCLK>; 55 cpu-idle-states = <&CPU_SLEEP>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 #cooling-cells = <2>; 58 dynamic-power-coefficient = <138>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0 0x1>; 65 enable-method = "psci"; 66 clocks = <&scmi_clk ARMCLK>; 67 cpu-idle-states = <&CPU_SLEEP>; 68 operating-points-v2 = <&cpu0_opp_table>; 69 #cooling-cells = <2>; 70 dynamic-power-coefficient = <138>; 71 }; 72 73 cpu2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x2>; 77 enable-method = "psci"; 78 clocks = <&scmi_clk ARMCLK>; 79 cpu-idle-states = <&CPU_SLEEP>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 #cooling-cells = <2>; 82 dynamic-power-coefficient = <138>; 83 }; 84 85 cpu3: cpu@3 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x0 0x3>; 89 enable-method = "psci"; 90 clocks = <&scmi_clk ARMCLK>; 91 cpu-idle-states = <&CPU_SLEEP>; 92 operating-points-v2 = <&cpu0_opp_table>; 93 #cooling-cells = <2>; 94 dynamic-power-coefficient = <138>; 95 }; 96 97 idle-states { 98 entry-method = "psci"; 99 100 CPU_SLEEP: cpu-sleep { 101 compatible = "arm,idle-state"; 102 local-timer-stop; 103 arm,psci-suspend-param = <0x0010000>; 104 entry-latency-us = <120>; 105 exit-latency-us = <250>; 106 min-residency-us = <900>; 107 }; 108 }; 109 }; 110 111 cpu0_opp_table: opp-table-cpu0 { 112 compatible = "operating-points-v2"; 113 opp-shared; 114 115 opp-408000000 { 116 opp-hz = /bits/ 64 <408000000>; 117 opp-microvolt = <825000 825000 1150000>; 118 clock-latency-ns = <40000>; 119 opp-suspend; 120 }; 121 opp-600000000 { 122 opp-hz = /bits/ 64 <600000000>; 123 opp-microvolt = <825000 825000 1150000>; 124 clock-latency-ns = <40000>; 125 }; 126 opp-816000000 { 127 opp-hz = /bits/ 64 <816000000>; 128 opp-microvolt = <825000 825000 1150000>; 129 clock-latency-ns = <40000>; 130 }; 131 opp-1008000000 { 132 opp-hz = /bits/ 64 <1008000000>; 133 opp-microvolt = <850000 850000 1150000>; 134 clock-latency-ns = <40000>; 135 }; 136 opp-1200000000 { 137 opp-hz = /bits/ 64 <1200000000>; 138 opp-microvolt = <925000 925000 1150000>; 139 clock-latency-ns = <40000>; 140 }; 141 opp-1416000000 { 142 opp-hz = /bits/ 64 <1416000000>; 143 opp-microvolt = <1000000 1000000 1150000>; 144 clock-latency-ns = <40000>; 145 }; 146 opp-1608000000 { 147 opp-supported-hw = <0xf9 0xffff>; 148 opp-hz = /bits/ 64 <1608000000>; 149 opp-microvolt = <1037500 1037500 1150000>; 150 clock-latency-ns = <40000>; 151 }; 152 opp-1800000000 { 153 opp-hz = /bits/ 64 <1800000000>; 154 opp-microvolt = <1125000 1125000 1150000>; 155 clock-latency-ns = <40000>; 156 }; 157 opp-2016000000 { 158 opp-hz = /bits/ 64 <2016000000>; 159 opp-microvolt = <1150000 1150000 1150000>; 160 clock-latency-ns = <40000>; 161 }; 162 163 }; 164 165 gpu_opp_table: opp-table-gpu { 166 compatible = "operating-points-v2"; 167 168 opp-300000000 { 169 opp-hz = /bits/ 64 <300000000>; 170 opp-microvolt = <825000 825000 1000000>; 171 }; 172 opp-400000000 { 173 opp-hz = /bits/ 64 <400000000>; 174 opp-microvolt = <825000 825000 1000000>; 175 }; 176 opp-500000000 { 177 opp-hz = /bits/ 64 <500000000>; 178 opp-microvolt = <825000 825000 1000000>; 179 }; 180 opp-600000000 { 181 opp-hz = /bits/ 64 <600000000>; 182 opp-microvolt = <825000 825000 1000000>; 183 }; 184 opp-700000000 { 185 opp-hz = /bits/ 64 <700000000>; 186 opp-microvolt = <900000 900000 1000000>; 187 }; 188 opp-800000000 { 189 opp-hz = /bits/ 64 <800000000>; 190 opp-microvolt = <950000 950000 1000000>; 191 }; 192 opp-900000000 { 193 opp-hz = /bits/ 64 <900000000>; 194 opp-microvolt = <1000000 1000000 1000000>; 195 }; 196 }; 197 198 arm_pmu: arm-pmu { 199 compatible = "arm,cortex-a53-pmu"; 200 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 204 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 205 }; 206 207 firmware { 208 scmi: scmi { 209 compatible = "arm,scmi-smc"; 210 shmem = <&scmi_shmem>; 211 arm,smc-id = <0x82000010>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 scmi_clk: protocol@14 { 216 reg = <0x14>; 217 #clock-cells = <1>; 218 }; 219 }; 220 }; 221 222 pinctrl: pinctrl { 223 compatible = "rockchip,rk3562-pinctrl"; 224 rockchip,grf = <&ioc_grf>; 225 #address-cells = <2>; 226 #size-cells = <2>; 227 ranges; 228 229 gpio0: gpio@ff260000 { 230 compatible = "rockchip,gpio-bank"; 231 reg = <0x0 0xff260000 0x0 0x100>; 232 clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; 233 gpio-controller; 234 gpio-ranges = <&pinctrl 0 0 32>; 235 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-controller; 237 #gpio-cells = <2>; 238 #interrupt-cells = <2>; 239 }; 240 241 gpio1: gpio@ff620000 { 242 compatible = "rockchip,gpio-bank"; 243 reg = <0x0 0xff620000 0x0 0x100>; 244 clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; 245 gpio-controller; 246 gpio-ranges = <&pinctrl 0 32 32>; 247 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-controller; 249 #gpio-cells = <2>; 250 #interrupt-cells = <2>; 251 }; 252 253 gpio2: gpio@ff630000 { 254 compatible = "rockchip,gpio-bank"; 255 reg = <0x0 0xff630000 0x0 0x100>; 256 clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; 257 gpio-controller; 258 gpio-ranges = <&pinctrl 0 64 32>; 259 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-controller; 261 #gpio-cells = <2>; 262 #interrupt-cells = <2>; 263 }; 264 265 gpio3: gpio@ffac0000 { 266 compatible = "rockchip,gpio-bank"; 267 reg = <0x0 0xffac0000 0x0 0x100>; 268 clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; 269 gpio-controller; 270 gpio-ranges = <&pinctrl 0 96 32>; 271 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-controller; 273 #gpio-cells = <2>; 274 #interrupt-cells = <2>; 275 }; 276 277 gpio4: gpio@ffad0000 { 278 compatible = "rockchip,gpio-bank"; 279 reg = <0x0 0xffad0000 0x0 0x100>; 280 clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; 281 gpio-controller; 282 gpio-ranges = <&pinctrl 0 128 32>; 283 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-controller; 285 #gpio-cells = <2>; 286 #interrupt-cells = <2>; 287 }; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 }; 294 295 reserved-memory { 296 #address-cells = <2>; 297 #size-cells = <2>; 298 ranges; 299 300 scmi_shmem: shmem@10f000 { 301 compatible = "arm,scmi-shmem"; 302 reg = <0x0 0x0010f000 0x0 0x100>; 303 no-map; 304 }; 305 }; 306 307 timer { 308 compatible = "arm,armv8-timer"; 309 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 310 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 311 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 312 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 313 }; 314 315 soc { 316 compatible = "simple-bus"; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 pcie2x1: pcie@fe000000 { 322 compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie"; 323 reg = <0x0 0xfe000000 0x0 0x400000>, 324 <0x0 0xff500000 0x0 0x10000>, 325 <0x0 0xfc000000 0x0 0x100000>; 326 reg-names = "dbi", "apb", "config"; 327 bus-range = <0x0 0xff>; 328 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 329 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 330 <&cru CLK_PCIE20_AUX>; 331 clock-names = "aclk_mst", "aclk_slv", 332 "aclk_dbi", "pclk", "aux"; 333 device_type = "pci"; 334 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 341 #interrupt-cells = <1>; 342 interrupt-map-mask = <0 0 0 7>; 343 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 344 <0 0 0 2 &pcie2x1_intc 1>, 345 <0 0 0 3 &pcie2x1_intc 2>, 346 <0 0 0 4 &pcie2x1_intc 3>; 347 linux,pci-domain = <0>; 348 max-link-speed = <2>; 349 num-ib-windows = <8>; 350 num-viewport = <8>; 351 num-ob-windows = <2>; 352 num-lanes = <1>; 353 phys = <&combphy PHY_TYPE_PCIE>; 354 phy-names = "pcie-phy"; 355 power-domains = <&power RK3562_PD_PHP>; 356 ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 357 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 358 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; 359 resets = <&cru SRST_PCIE20_POWERUP>; 360 reset-names = "pipe"; 361 #address-cells = <3>; 362 #size-cells = <2>; 363 status = "disabled"; 364 365 pcie2x1_intc: legacy-interrupt-controller { 366 interrupt-controller; 367 #address-cells = <0>; 368 #interrupt-cells = <1>; 369 interrupt-parent = <&gic>; 370 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 371 }; 372 }; 373 374 gic: interrupt-controller@fe901000 { 375 compatible = "arm,gic-400"; 376 #interrupt-cells = <3>; 377 #address-cells = <0>; 378 interrupt-controller; 379 reg = <0x0 0xfe901000 0 0x1000>, 380 <0x0 0xfe902000 0 0x2000>, 381 <0x0 0xfe904000 0 0x2000>, 382 <0x0 0xfe906000 0 0x2000>; 383 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 384 }; 385 386 qos_dma2ddr: qos@fee03800 { 387 compatible = "rockchip,rk3562-qos", "syscon"; 388 reg = <0x0 0xfee03800 0x0 0x20>; 389 }; 390 391 qos_mcu: qos@fee10000 { 392 compatible = "rockchip,rk3562-qos", "syscon"; 393 reg = <0x0 0xfee10000 0x0 0x20>; 394 }; 395 396 qos_dft_apb: qos@fee10100 { 397 compatible = "rockchip,rk3562-qos", "syscon"; 398 reg = <0x0 0xfee10100 0x0 0x20>; 399 }; 400 401 qos_gmac: qos@fee10200 { 402 compatible = "rockchip,rk3562-qos", "syscon"; 403 reg = <0x0 0xfee10200 0x0 0x20>; 404 }; 405 406 qos_mac100: qos@fee10300 { 407 compatible = "rockchip,rk3562-qos", "syscon"; 408 reg = <0x0 0xfee10300 0x0 0x20>; 409 }; 410 411 qos_dcf: qos@fee10400 { 412 compatible = "rockchip,rk3562-qos", "syscon"; 413 reg = <0x0 0xfee10400 0x0 0x20>; 414 }; 415 416 qos_cpu: qos@fee20000 { 417 compatible = "rockchip,rk3562-qos", "syscon"; 418 reg = <0x0 0xfee20000 0x0 0x20>; 419 }; 420 421 qos_gpu: qos@fee30000 { 422 compatible = "rockchip,rk3562-qos", "syscon"; 423 reg = <0x0 0xfee30000 0x0 0x20>; 424 }; 425 426 qos_npu: qos@fee40000 { 427 compatible = "rockchip,rk3562-qos", "syscon"; 428 reg = <0x0 0xfee40000 0x0 0x20>; 429 }; 430 431 qos_rkvdec: qos@fee50000 { 432 compatible = "rockchip,rk3562-qos", "syscon"; 433 reg = <0x0 0xfee50000 0x0 0x20>; 434 }; 435 436 qos_vepu: qos@fee60000 { 437 compatible = "rockchip,rk3562-qos", "syscon"; 438 reg = <0x0 0xfee60000 0x0 0x20>; 439 }; 440 441 qos_isp: qos@fee70000 { 442 compatible = "rockchip,rk3562-qos", "syscon"; 443 reg = <0x0 0xfee70000 0x0 0x20>; 444 }; 445 446 qos_vicap: qos@fee70100 { 447 compatible = "rockchip,rk3562-qos", "syscon"; 448 reg = <0x0 0xfee70100 0x0 0x20>; 449 }; 450 451 qos_vop: qos@fee80000 { 452 compatible = "rockchip,rk3562-qos", "syscon"; 453 reg = <0x0 0xfee80000 0x0 0x20>; 454 }; 455 456 qos_jpeg: qos@fee90000 { 457 compatible = "rockchip,rk3562-qos", "syscon"; 458 reg = <0x0 0xfee90000 0x0 0x20>; 459 }; 460 461 qos_rga_rd: qos@fee90100 { 462 compatible = "rockchip,rk3562-qos", "syscon"; 463 reg = <0x0 0xfee90100 0x0 0x20>; 464 }; 465 466 qos_rga_wr: qos@fee90200 { 467 compatible = "rockchip,rk3562-qos", "syscon"; 468 reg = <0x0 0xfee90200 0x0 0x20>; 469 }; 470 471 qos_pcie: qos@feea0000 { 472 compatible = "rockchip,rk3562-qos", "syscon"; 473 reg = <0x0 0xfeea0000 0x0 0x20>; 474 }; 475 476 qos_usb3: qos@feea0100 { 477 compatible = "rockchip,rk3562-qos", "syscon"; 478 reg = <0x0 0xfeea0100 0x0 0x20>; 479 }; 480 481 qos_crypto_apb: qos@feeb0000 { 482 compatible = "rockchip,rk3562-qos", "syscon"; 483 reg = <0x0 0xfeeb0000 0x0 0x20>; 484 }; 485 486 qos_crypto: qos@feeb0100 { 487 compatible = "rockchip,rk3562-qos", "syscon"; 488 reg = <0x0 0xfeeb0100 0x0 0x20>; 489 }; 490 491 qos_dmac: qos@feeb0200 { 492 compatible = "rockchip,rk3562-qos", "syscon"; 493 reg = <0x0 0xfeeb0200 0x0 0x20>; 494 }; 495 496 qos_emmc: qos@feeb0300 { 497 compatible = "rockchip,rk3562-qos", "syscon"; 498 reg = <0x0 0xfeeb0300 0x0 0x20>; 499 }; 500 501 qos_fspi: qos@feeb0400 { 502 compatible = "rockchip,rk3562-qos", "syscon"; 503 reg = <0x0 0xfeeb0400 0x0 0x20>; 504 }; 505 506 qos_rkdma: qos@feeb0500 { 507 compatible = "rockchip,rk3562-qos", "syscon"; 508 reg = <0x0 0xfeeb0500 0x0 0x20>; 509 }; 510 511 qos_sdmmc0: qos@feeb0600 { 512 compatible = "rockchip,rk3562-qos", "syscon"; 513 reg = <0x0 0xfeeb0600 0x0 0x20>; 514 }; 515 516 qos_sdmmc1: qos@feeb0700 { 517 compatible = "rockchip,rk3562-qos", "syscon"; 518 reg = <0x0 0xfeeb0700 0x0 0x20>; 519 }; 520 521 qos_usb2: qos@feeb0800 { 522 compatible = "rockchip,rk3562-qos", "syscon"; 523 reg = <0x0 0xfeeb0800 0x0 0x20>; 524 }; 525 526 pmu_grf: syscon@ff010000 { 527 compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; 528 reg = <0x0 0xff010000 0x0 0x10000>; 529 530 reboot_mode: reboot-mode { 531 compatible = "syscon-reboot-mode"; 532 offset = <0x220>; 533 mode-normal = <BOOT_NORMAL>; 534 mode-loader = <BOOT_BL_DOWNLOAD>; 535 mode-recovery = <BOOT_RECOVERY>; 536 mode-bootloader = <BOOT_FASTBOOT>; 537 }; 538 }; 539 540 sys_grf: syscon@ff030000 { 541 compatible = "rockchip,rk3562-sys-grf", "syscon"; 542 reg = <0x0 0xff030000 0x0 0x10000>; 543 }; 544 545 peri_grf: syscon@ff040000 { 546 compatible = "rockchip,rk3562-peri-grf", "syscon"; 547 reg = <0x0 0xff040000 0x0 0x10000>; 548 }; 549 550 ioc_grf: syscon@ff060000 { 551 compatible = "rockchip,rk3562-ioc-grf", "syscon"; 552 reg = <0x0 0xff060000 0x0 0x30000>; 553 }; 554 555 usbphy_grf: syscon@ff090000 { 556 compatible = "rockchip,rk3562-usbphy-grf", "syscon"; 557 reg = <0x0 0xff090000 0x0 0x8000>; 558 }; 559 560 pipephy_grf: syscon@ff098000 { 561 compatible = "rockchip,rk3562-pipephy-grf", "syscon"; 562 reg = <0x0 0xff098000 0x0 0x8000>; 563 }; 564 565 cru: clock-controller@ff100000 { 566 compatible = "rockchip,rk3562-cru"; 567 reg = <0x0 0xff100000 0x0 0x40000>; 568 #clock-cells = <1>; 569 #reset-cells = <1>; 570 571 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 572 <&cru PLL_HPLL>; 573 assigned-clock-rates = <1188000000>, <1000000000>, 574 <983040000>; 575 }; 576 577 i2c0: i2c@ff200000 { 578 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 579 reg = <0x0 0xff200000 0x0 0x1000>; 580 clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; 581 clock-names = "i2c", "pclk"; 582 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&i2c0_xfer>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 uart0: serial@ff210000 { 591 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 592 reg = <0x0 0xff210000 0x0 0x100>; 593 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; 595 clock-names = "baudclk", "apb_pclk"; 596 reg-shift = <2>; 597 reg-io-width = <4>; 598 status = "disabled"; 599 }; 600 601 spi0: spi@ff220000 { 602 compatible = "rockchip,rk3562-spi", "rockchip,rk3066-spi"; 603 reg = <0x0 0xff220000 0x0 0x1000>; 604 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>; 606 clock-names = "spiclk", "apb_pclk"; 607 dmas = <&dmac 13>, <&dmac 12>; 608 dma-names = "tx", "rx"; 609 num-cs = <2>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 pwm0: pwm@ff230000 { 618 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 619 reg = <0x0 0xff230000 0x0 0x10>; 620 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 621 clock-names = "pwm", "pclk"; 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pwm0m0_pins>; 624 #pwm-cells = <3>; 625 status = "disabled"; 626 }; 627 628 pwm1: pwm@ff230010 { 629 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 630 reg = <0x0 0xff230010 0x0 0x10>; 631 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 632 clock-names = "pwm", "pclk"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&pwm1m0_pins>; 635 #pwm-cells = <3>; 636 status = "disabled"; 637 }; 638 639 pwm2: pwm@ff230020 { 640 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 641 reg = <0x0 0xff230020 0x0 0x10>; 642 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 643 clock-names = "pwm", "pclk"; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pwm2m0_pins>; 646 #pwm-cells = <3>; 647 status = "disabled"; 648 }; 649 650 pwm3: pwm@ff230030 { 651 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 652 reg = <0x0 0xff230030 0x0 0x10>; 653 clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; 654 clock-names = "pwm", "pclk"; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&pwm3m0_pins>; 657 #pwm-cells = <3>; 658 status = "disabled"; 659 }; 660 661 pmu: power-management@ff258000 { 662 compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; 663 reg = <0x0 0xff258000 0x0 0x1000>; 664 665 power: power-controller { 666 compatible = "rockchip,rk3562-power-controller"; 667 #power-domain-cells = <1>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 671 power-domain@RK3562_PD_GPU { 672 reg = <RK3562_PD_GPU>; 673 pm_qos = <&qos_gpu>; 674 #power-domain-cells = <0>; 675 }; 676 677 power-domain@RK3562_PD_NPU { 678 reg = <RK3562_PD_NPU>; 679 pm_qos = <&qos_npu>; 680 #power-domain-cells = <0>; 681 }; 682 683 power-domain@RK3562_PD_VDPU { 684 reg = <RK3562_PD_VDPU>; 685 pm_qos = <&qos_rkvdec>; 686 #power-domain-cells = <0>; 687 }; 688 689 power-domain@RK3562_PD_VI { 690 reg = <RK3562_PD_VI>; 691 pm_qos = <&qos_isp>, 692 <&qos_vicap>; 693 #power-domain-cells = <1>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 power-domain@RK3562_PD_VEPU { 698 reg = <RK3562_PD_VEPU>; 699 pm_qos = <&qos_vepu>; 700 #power-domain-cells = <0>; 701 }; 702 }; 703 704 power-domain@RK3562_PD_VO { 705 reg = <RK3562_PD_VO>; 706 pm_qos = <&qos_vop>; 707 #power-domain-cells = <1>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 711 power-domain@RK3562_PD_RGA { 712 reg = <RK3562_PD_RGA>; 713 pm_qos = <&qos_rga_rd>, 714 <&qos_rga_wr>, 715 <&qos_jpeg>; 716 #power-domain-cells = <0>; 717 }; 718 }; 719 720 power-domain@RK3562_PD_PHP { 721 reg = <RK3562_PD_PHP>; 722 pm_qos = <&qos_pcie>, 723 <&qos_usb3>; 724 #power-domain-cells = <0>; 725 }; 726 }; 727 }; 728 729 gpu: gpu@ff320000 { 730 compatible = "rockchip,rk3562-mali", "arm,mali-bifrost"; 731 reg = <0x0 0xff320000 0x0 0x4000>; 732 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>, 733 <&cru ACLK_GPU_PRE>; 734 clock-names = "clk_gpu", "clk_gpu_brg", "aclk_gpu"; 735 dynamic-power-coefficient = <820>; 736 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 739 interrupt-names = "job", "mmu", "gpu"; 740 operating-points-v2 = <&gpu_opp_table>; 741 power-domains = <&power RK3562_PD_GPU>; 742 #cooling-cells = <2>; 743 status = "disabled"; 744 }; 745 746 spi1: spi@ff640000 { 747 compatible = "rockchip,rk3066-spi"; 748 reg = <0x0 0xff640000 0x0 0x1000>; 749 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 751 clock-names = "spiclk", "apb_pclk"; 752 dmas = <&dmac 15>, <&dmac 14>; 753 dma-names = "tx", "rx"; 754 num-cs = <2>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 status = "disabled"; 760 }; 761 762 spi2: spi@ff650000 { 763 compatible = "rockchip,rk3066-spi"; 764 reg = <0x0 0xff650000 0x0 0x1000>; 765 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 767 clock-names = "spiclk", "apb_pclk"; 768 dmas = <&dmac 17>, <&dmac 16>; 769 dma-names = "tx", "rx"; 770 num-cs = <2>; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 uart1: serial@ff670000 { 779 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 780 reg = <0x0 0xff670000 0x0 0x100>; 781 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 783 clock-names = "baudclk", "apb_pclk"; 784 reg-shift = <2>; 785 reg-io-width = <4>; 786 status = "disabled"; 787 }; 788 789 uart2: serial@ff680000 { 790 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 791 reg = <0x0 0xff680000 0x0 0x100>; 792 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 794 clock-names = "baudclk", "apb_pclk"; 795 reg-shift = <2>; 796 reg-io-width = <4>; 797 status = "disabled"; 798 }; 799 800 uart3: serial@ff690000 { 801 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 802 reg = <0x0 0xff690000 0x0 0x100>; 803 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 805 clock-names = "baudclk", "apb_pclk"; 806 reg-shift = <2>; 807 reg-io-width = <4>; 808 status = "disabled"; 809 }; 810 811 uart4: serial@ff6a0000 { 812 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 813 reg = <0x0 0xff6a0000 0x0 0x100>; 814 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 816 clock-names = "baudclk", "apb_pclk"; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 status = "disabled"; 820 }; 821 822 uart5: serial@ff6b0000 { 823 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 824 reg = <0x0 0xff6b0000 0x0 0x100>; 825 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 827 clock-names = "baudclk", "apb_pclk"; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 status = "disabled"; 831 }; 832 833 uart6: serial@ff6c0000 { 834 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 835 reg = <0x0 0xff6c0000 0x0 0x100>; 836 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 838 clock-names = "baudclk", "apb_pclk"; 839 reg-shift = <2>; 840 reg-io-width = <4>; 841 status = "disabled"; 842 }; 843 844 uart7: serial@ff6d0000 { 845 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 846 reg = <0x0 0xff6d0000 0x0 0x100>; 847 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 849 clock-names = "baudclk", "apb_pclk"; 850 reg-shift = <2>; 851 reg-io-width = <4>; 852 status = "disabled"; 853 }; 854 855 uart8: serial@ff6e0000 { 856 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 857 reg = <0x0 0xff6e0000 0x0 0x100>; 858 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 860 clock-names = "baudclk", "apb_pclk"; 861 reg-shift = <2>; 862 reg-io-width = <4>; 863 status = "disabled"; 864 }; 865 866 uart9: serial@ff6f0000 { 867 compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; 868 reg = <0x0 0xff6f0000 0x0 0x100>; 869 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 871 clock-names = "baudclk", "apb_pclk"; 872 reg-shift = <2>; 873 reg-io-width = <4>; 874 status = "disabled"; 875 }; 876 877 pwm4: pwm@ff700000 { 878 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 879 reg = <0x0 0xff700000 0x0 0x10>; 880 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 881 clock-names = "pwm", "pclk"; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&pwm4m0_pins>; 884 #pwm-cells = <3>; 885 status = "disabled"; 886 }; 887 888 pwm5: pwm@ff700010 { 889 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 890 reg = <0x0 0xff700010 0x0 0x10>; 891 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 892 clock-names = "pwm", "pclk"; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&pwm5m0_pins>; 895 #pwm-cells = <3>; 896 status = "disabled"; 897 }; 898 899 pwm6: pwm@ff700020 { 900 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 901 reg = <0x0 0xff700020 0x0 0x10>; 902 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 903 clock-names = "pwm", "pclk"; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&pwm6m0_pins>; 906 #pwm-cells = <3>; 907 status = "disabled"; 908 }; 909 910 pwm7: pwm@ff700030 { 911 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 912 reg = <0x0 0xff700030 0x0 0x10>; 913 clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; 914 clock-names = "pwm", "pclk"; 915 pinctrl-names = "default"; 916 pinctrl-0 = <&pwm7m0_pins>; 917 #pwm-cells = <3>; 918 status = "disabled"; 919 }; 920 921 pwm8: pwm@ff710000 { 922 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 923 reg = <0x0 0xff710000 0x0 0x10>; 924 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 925 clock-names = "pwm", "pclk"; 926 pinctrl-names = "default"; 927 pinctrl-0 = <&pwm8m0_pins>; 928 #pwm-cells = <3>; 929 status = "disabled"; 930 }; 931 932 pwm9: pwm@ff710010 { 933 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 934 reg = <0x0 0xff710010 0x0 0x10>; 935 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 936 clock-names = "pwm", "pclk"; 937 pinctrl-names = "default"; 938 pinctrl-0 = <&pwm9m0_pins>; 939 #pwm-cells = <3>; 940 status = "disabled"; 941 }; 942 943 pwm10: pwm@ff710020 { 944 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 945 reg = <0x0 0xff710020 0x0 0x10>; 946 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 947 clock-names = "pwm", "pclk"; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&pwm10m0_pins>; 950 #pwm-cells = <3>; 951 status = "disabled"; 952 }; 953 954 pwm11: pwm@ff710030 { 955 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 956 reg = <0x0 0xff710030 0x0 0x10>; 957 clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; 958 clock-names = "pwm", "pclk"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&pwm11m0_pins>; 961 #pwm-cells = <3>; 962 status = "disabled"; 963 }; 964 965 pwm12: pwm@ff720000 { 966 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 967 reg = <0x0 0xff720000 0x0 0x10>; 968 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 969 clock-names = "pwm", "pclk"; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&pwm12m0_pins>; 972 #pwm-cells = <3>; 973 status = "disabled"; 974 }; 975 976 pwm13: pwm@ff720010 { 977 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 978 reg = <0x0 0xff720010 0x0 0x10>; 979 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 980 clock-names = "pwm", "pclk"; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&pwm13m0_pins>; 983 #pwm-cells = <3>; 984 status = "disabled"; 985 }; 986 987 pwm14: pwm@ff720020 { 988 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 989 reg = <0x0 0xff720020 0x0 0x10>; 990 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 991 clock-names = "pwm", "pclk"; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&pwm14m0_pins>; 994 #pwm-cells = <3>; 995 status = "disabled"; 996 }; 997 998 pwm15: pwm@ff720030 { 999 compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; 1000 reg = <0x0 0xff720030 0x0 0x10>; 1001 clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; 1002 clock-names = "pwm", "pclk"; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&pwm15m0_pins>; 1005 #pwm-cells = <3>; 1006 status = "disabled"; 1007 }; 1008 1009 saradc0: adc@ff730000 { 1010 compatible = "rockchip,rk3562-saradc"; 1011 reg = <0x0 0xff730000 0x0 0x100>; 1012 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1014 clock-names = "saradc", "apb_pclk"; 1015 resets = <&cru SRST_P_SARADC>; 1016 reset-names = "saradc-apb"; 1017 #io-channel-cells = <1>; 1018 status = "disabled"; 1019 }; 1020 1021 combphy: phy@ff750000 { 1022 compatible = "rockchip,rk3562-naneng-combphy"; 1023 reg = <0x0 0xff750000 0x0 0x100>; 1024 #phy-cells = <1>; 1025 clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, 1026 <&cru PCLK_PHP>; 1027 clock-names = "ref", "apb", "pipe"; 1028 assigned-clocks = <&cru CLK_PIPEPHY_REF>; 1029 assigned-clock-rates = <100000000>; 1030 resets = <&cru SRST_PIPEPHY>; 1031 reset-names = "phy"; 1032 rockchip,pipe-grf = <&peri_grf>; 1033 rockchip,pipe-phy-grf = <&pipephy_grf>; 1034 status = "disabled"; 1035 }; 1036 1037 sfc: spi@ff860000 { 1038 compatible = "rockchip,sfc"; 1039 reg = <0x0 0xff860000 0x0 0x10000>; 1040 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1042 clock-names = "clk_sfc", "hclk_sfc"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 sdhci: mmc@ff870000 { 1049 compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3588-dwcmshc"; 1050 reg = <0x0 0xff870000 0x0 0x10000>; 1051 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1052 assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; 1053 assigned-clock-rates = <200000000>, <200000000>; 1054 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1055 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1056 <&cru TMCLK_EMMC>; 1057 clock-names = "core", "bus", "axi", "block", "timer"; 1058 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1059 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1060 <&cru SRST_T_EMMC>; 1061 reset-names = "core", "bus", "axi", "block", "timer"; 1062 max-frequency = <200000000>; 1063 status = "disabled"; 1064 }; 1065 1066 sdmmc0: mmc@ff880000 { 1067 compatible = "rockchip,rk3562-dw-mshc", 1068 "rockchip,rk3288-dw-mshc"; 1069 reg = <0x0 0xff880000 0x0 0x10000>; 1070 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, 1072 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1073 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1074 fifo-depth = <0x100>; 1075 max-frequency = <200000000>; 1076 resets = <&cru SRST_H_SDMMC0>; 1077 reset-names = "reset"; 1078 status = "disabled"; 1079 }; 1080 1081 sdmmc1: mmc@ff890000 { 1082 compatible = "rockchip,rk3562-dw-mshc", 1083 "rockchip,rk3288-dw-mshc"; 1084 reg = <0x0 0xff890000 0x0 0x10000>; 1085 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, 1087 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1088 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1089 fifo-depth = <0x100>; 1090 max-frequency = <200000000>; 1091 resets = <&cru SRST_H_SDMMC1>; 1092 reset-names = "reset"; 1093 status = "disabled"; 1094 }; 1095 1096 dmac: dma-controller@ff990000 { 1097 compatible = "arm,pl330", "arm,primecell"; 1098 reg = <0x0 0xff990000 0x0 0x4000>; 1099 arm,pl330-periph-burst; 1100 clocks = <&cru ACLK_DMAC>; 1101 clock-names = "apb_pclk"; 1102 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1104 #dma-cells = <1>; 1105 }; 1106 1107 i2c1: i2c@ffa00000 { 1108 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1109 reg = <0x0 0xffa00000 0x0 0x1000>; 1110 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1111 clock-names = "i2c", "pclk"; 1112 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&i2c1m0_xfer>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 i2c2: i2c@ffa10000 { 1121 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1122 reg = <0x0 0xffa10000 0x0 0x1000>; 1123 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1124 clock-names = "i2c", "pclk"; 1125 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&i2c2m0_xfer>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 i2c3: i2c@ffa20000 { 1134 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1135 reg = <0x0 0xffa20000 0x0 0x1000>; 1136 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1137 clock-names = "i2c", "pclk"; 1138 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&i2c3m0_xfer>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c4: i2c@ffa30000 { 1147 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1148 reg = <0x0 0xffa30000 0x0 0x1000>; 1149 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1150 clock-names = "i2c", "pclk"; 1151 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&i2c4m0_xfer>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c5: i2c@ffa40000 { 1160 compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; 1161 reg = <0x0 0xffa40000 0x0 0x1000>; 1162 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1163 clock-names = "i2c", "pclk"; 1164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&i2c5m0_xfer>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 saradc1: adc@ffaa0000 { 1173 compatible = "rockchip,rk3562-saradc"; 1174 reg = <0x0 0xffaa0000 0x0 0x100>; 1175 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; 1177 clock-names = "saradc", "apb_pclk"; 1178 resets = <&cru SRST_P_SARADC_VCCIO156>; 1179 reset-names = "saradc-apb"; 1180 #io-channel-cells = <1>; 1181 status = "disabled"; 1182 }; 1183 }; 1184}; 1185 1186#include "rk3562-pinctrl.dtsi"
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