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rk3528.dtsi
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linux-6.19.14/arch/arm64/boot/dts/rockchip/rk3528.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/phy/phy.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/clock/rockchip,rk3528-cru.h> 13#include <dt-bindings/power/rockchip,rk3528-power.h> 14#include <dt-bindings/reset/rockchip,rk3528-cru.h> 15 16/ { 17 compatible = "rockchip,rk3528"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 gpio0 = &gpio0; 25 gpio1 = &gpio1; 26 gpio2 = &gpio2; 27 gpio3 = &gpio3; 28 gpio4 = &gpio4; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu-map { 36 cluster0 { 37 core0 { 38 cpu = <&cpu0>; 39 }; 40 core1 { 41 cpu = <&cpu1>; 42 }; 43 core2 { 44 cpu = <&cpu2>; 45 }; 46 core3 { 47 cpu = <&cpu3>; 48 }; 49 }; 50 }; 51 52 cpu0: cpu@0 { 53 compatible = "arm,cortex-a53"; 54 reg = <0x0>; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 clocks = <&scmi_clk SCMI_CLK_CPU>; 58 operating-points-v2 = <&cpu_opp_table>; 59 }; 60 61 cpu1: cpu@1 { 62 compatible = "arm,cortex-a53"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 enable-method = "psci"; 66 clocks = <&scmi_clk SCMI_CLK_CPU>; 67 operating-points-v2 = <&cpu_opp_table>; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53"; 72 reg = <0x2>; 73 device_type = "cpu"; 74 enable-method = "psci"; 75 clocks = <&scmi_clk SCMI_CLK_CPU>; 76 operating-points-v2 = <&cpu_opp_table>; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53"; 81 reg = <0x3>; 82 device_type = "cpu"; 83 enable-method = "psci"; 84 clocks = <&scmi_clk SCMI_CLK_CPU>; 85 operating-points-v2 = <&cpu_opp_table>; 86 }; 87 }; 88 89 firmware { 90 scmi: scmi { 91 compatible = "arm,scmi-smc"; 92 arm,smc-id = <0x82000010>; 93 shmem = <&scmi_shmem>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 scmi_clk: protocol@14 { 98 reg = <0x14>; 99 #clock-cells = <1>; 100 }; 101 }; 102 }; 103 104 cpu_opp_table: opp-table-cpu { 105 compatible = "operating-points-v2"; 106 opp-shared; 107 108 opp-1200000000 { 109 opp-hz = /bits/ 64 <1200000000>; 110 opp-microvolt = <875000 875000 1100000>; 111 clock-latency-ns = <40000>; 112 }; 113 114 opp-1416000000 { 115 opp-hz = /bits/ 64 <1416000000>; 116 opp-microvolt = <925000 925000 1100000>; 117 clock-latency-ns = <40000>; 118 }; 119 120 opp-1608000000 { 121 opp-hz = /bits/ 64 <1608000000>; 122 opp-microvolt = <975000 975000 1100000>; 123 clock-latency-ns = <40000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1037500 1037500 1100000>; 129 clock-latency-ns = <40000>; 130 }; 131 132 opp-2016000000 { 133 opp-hz = /bits/ 64 <2016000000>; 134 opp-microvolt = <1100000 1100000 1100000>; 135 clock-latency-ns = <40000>; 136 }; 137 }; 138 139 gpu_opp_table: opp-table-gpu { 140 compatible = "operating-points-v2"; 141 142 opp-300000000 { 143 opp-hz = /bits/ 64 <300000000>; 144 opp-microvolt = <875000 875000 1000000>; 145 opp-suspend; 146 }; 147 148 opp-500000000 { 149 opp-hz = /bits/ 64 <500000000>; 150 opp-microvolt = <875000 875000 1000000>; 151 }; 152 153 opp-600000000 { 154 opp-hz = /bits/ 64 <600000000>; 155 opp-microvolt = <875000 875000 1000000>; 156 }; 157 158 opp-700000000 { 159 opp-hz = /bits/ 64 <700000000>; 160 opp-microvolt = <900000 900000 1000000>; 161 }; 162 163 opp-800000000 { 164 opp-hz = /bits/ 64 <800000000>; 165 opp-microvolt = <950000 950000 1000000>; 166 }; 167 }; 168 169 pinctrl: pinctrl { 170 compatible = "rockchip,rk3528-pinctrl"; 171 rockchip,grf = <&ioc_grf>; 172 #address-cells = <2>; 173 #size-cells = <2>; 174 ranges; 175 176 gpio0: gpio@ff610000 { 177 compatible = "rockchip,gpio-bank"; 178 reg = <0x0 0xff610000 0x0 0x200>; 179 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 180 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 181 gpio-controller; 182 #gpio-cells = <2>; 183 gpio-ranges = <&pinctrl 0 0 32>; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 }; 187 188 gpio1: gpio@ffaf0000 { 189 compatible = "rockchip,gpio-bank"; 190 reg = <0x0 0xffaf0000 0x0 0x200>; 191 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 192 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 gpio-ranges = <&pinctrl 0 32 32>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 power-domains = <&power RK3528_PD_VPU>; 199 }; 200 201 gpio2: gpio@ffb00000 { 202 compatible = "rockchip,gpio-bank"; 203 reg = <0x0 0xffb00000 0x0 0x200>; 204 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 205 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 206 gpio-controller; 207 #gpio-cells = <2>; 208 gpio-ranges = <&pinctrl 0 64 32>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 power-domains = <&power RK3528_PD_VO>; 212 }; 213 214 gpio3: gpio@ffb10000 { 215 compatible = "rockchip,gpio-bank"; 216 reg = <0x0 0xffb10000 0x0 0x200>; 217 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 219 gpio-controller; 220 #gpio-cells = <2>; 221 gpio-ranges = <&pinctrl 0 96 32>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 power-domains = <&power RK3528_PD_VPU>; 225 }; 226 227 gpio4: gpio@ffb20000 { 228 compatible = "rockchip,gpio-bank"; 229 reg = <0x0 0xffb20000 0x0 0x200>; 230 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 231 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 gpio-ranges = <&pinctrl 0 128 32>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 power-domains = <&power RK3528_PD_RKVENC>; 238 }; 239 }; 240 241 psci { 242 compatible = "arm,psci-1.0", "arm,psci-0.2"; 243 method = "smc"; 244 }; 245 246 reserved-memory { 247 #address-cells = <2>; 248 #size-cells = <2>; 249 ranges; 250 251 scmi_shmem: shmem@10f000 { 252 compatible = "arm,scmi-shmem"; 253 reg = <0x0 0x0010f000 0x0 0x100>; 254 no-map; 255 }; 256 }; 257 258 timer { 259 compatible = "arm,armv8-timer"; 260 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 261 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 262 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 263 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 264 }; 265 266 xin24m: clock-xin24m { 267 compatible = "fixed-clock"; 268 clock-frequency = <24000000>; 269 clock-output-names = "xin24m"; 270 #clock-cells = <0>; 271 }; 272 273 gmac0_clk: clock-gmac50m { 274 compatible = "fixed-clock"; 275 clock-frequency = <50000000>; 276 clock-output-names = "gmac0"; 277 #clock-cells = <0>; 278 }; 279 280 soc { 281 compatible = "simple-bus"; 282 ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>; 283 #address-cells = <2>; 284 #size-cells = <2>; 285 286 pcie: pcie@fe000000 { 287 compatible = "rockchip,rk3528-pcie", 288 "rockchip,rk3568-pcie"; 289 reg = <0x0 0xfe000000 0x0 0x400000>, 290 <0x0 0xfe4f0000 0x0 0x010000>, 291 <0x0 0xfc000000 0x0 0x100000>; 292 reg-names = "dbi", "apb", "config"; 293 bus-range = <0x0 0xff>; 294 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, 295 <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, 296 <&cru CLK_PCIE_AUX>; 297 clock-names = "aclk_mst", "aclk_slv", 298 "aclk_dbi", "pclk", 299 "aux"; 300 device_type = "pci"; 301 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "sys", "pmc", "msg", "legacy", "err", 308 "msi"; 309 #interrupt-cells = <1>; 310 interrupt-map-mask = <0 0 0 7>; 311 interrupt-map = <0 0 0 1 &pcie_intc 0>, 312 <0 0 0 2 &pcie_intc 1>, 313 <0 0 0 3 &pcie_intc 2>, 314 <0 0 0 4 &pcie_intc 3>; 315 linux,pci-domain = <0>; 316 max-link-speed = <2>; 317 num-lanes = <1>; 318 phys = <&combphy PHY_TYPE_PCIE>; 319 phy-names = "pcie-phy"; 320 power-domains = <&power RK3528_PD_VPU>; 321 ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>, 322 <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>, 323 <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; 324 resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>; 325 reset-names = "pwr", "pipe"; 326 #address-cells = <3>; 327 #size-cells = <2>; 328 status = "disabled"; 329 330 pcie_intc: legacy-interrupt-controller { 331 interrupt-controller; 332 interrupt-parent = <&gic>; 333 interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>; 334 #address-cells = <0>; 335 #interrupt-cells = <1>; 336 }; 337 }; 338 339 gic: interrupt-controller@fed01000 { 340 compatible = "arm,gic-400"; 341 reg = <0x0 0xfed01000 0 0x1000>, 342 <0x0 0xfed02000 0 0x2000>, 343 <0x0 0xfed04000 0 0x2000>, 344 <0x0 0xfed06000 0 0x2000>; 345 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 346 IRQ_TYPE_LEVEL_LOW)>; 347 interrupt-controller; 348 #address-cells = <0>; 349 #interrupt-cells = <3>; 350 }; 351 352 qos_crypto_a: qos@ff200000 { 353 compatible = "rockchip,rk3528-qos", "syscon"; 354 reg = <0x0 0xff200000 0x0 0x20>; 355 }; 356 357 qos_crypto_p: qos@ff200080 { 358 compatible = "rockchip,rk3528-qos", "syscon"; 359 reg = <0x0 0xff200080 0x0 0x20>; 360 }; 361 362 qos_dcf: qos@ff200100 { 363 compatible = "rockchip,rk3528-qos", "syscon"; 364 reg = <0x0 0xff200100 0x0 0x20>; 365 }; 366 367 qos_dft2apb: qos@ff200200 { 368 compatible = "rockchip,rk3528-qos", "syscon"; 369 reg = <0x0 0xff200200 0x0 0x20>; 370 }; 371 372 qos_dma2ddr: qos@ff200280 { 373 compatible = "rockchip,rk3528-qos", "syscon"; 374 reg = <0x0 0xff200280 0x0 0x20>; 375 }; 376 377 qos_dmac: qos@ff200300 { 378 compatible = "rockchip,rk3528-qos", "syscon"; 379 reg = <0x0 0xff200300 0x0 0x20>; 380 }; 381 382 qos_keyreader: qos@ff200380 { 383 compatible = "rockchip,rk3528-qos", "syscon"; 384 reg = <0x0 0xff200380 0x0 0x20>; 385 }; 386 387 qos_cpu: qos@ff210000 { 388 compatible = "rockchip,rk3528-qos", "syscon"; 389 reg = <0x0 0xff210000 0x0 0x20>; 390 }; 391 392 qos_debug: qos@ff210080 { 393 compatible = "rockchip,rk3528-qos", "syscon"; 394 reg = <0x0 0xff210080 0x0 0x20>; 395 }; 396 397 qos_gpu_m0: qos@ff220000 { 398 compatible = "rockchip,rk3528-qos", "syscon"; 399 reg = <0x0 0xff220000 0x0 0x20>; 400 }; 401 402 qos_gpu_m1: qos@ff220080 { 403 compatible = "rockchip,rk3528-qos", "syscon"; 404 reg = <0x0 0xff220080 0x0 0x20>; 405 }; 406 407 qos_pmu_mcu: qos@ff240000 { 408 compatible = "rockchip,rk3528-qos", "syscon"; 409 reg = <0x0 0xff240000 0x0 0x20>; 410 }; 411 412 qos_rkvdec: qos@ff250000 { 413 compatible = "rockchip,rk3528-qos", "syscon"; 414 reg = <0x0 0xff250000 0x0 0x20>; 415 }; 416 417 qos_rkvenc: qos@ff260000 { 418 compatible = "rockchip,rk3528-qos", "syscon"; 419 reg = <0x0 0xff260000 0x0 0x20>; 420 }; 421 422 qos_gmac0: qos@ff270000 { 423 compatible = "rockchip,rk3528-qos", "syscon"; 424 reg = <0x0 0xff270000 0x0 0x20>; 425 }; 426 427 qos_hdcp: qos@ff270080 { 428 compatible = "rockchip,rk3528-qos", "syscon"; 429 reg = <0x0 0xff270080 0x0 0x20>; 430 }; 431 432 qos_jpegdec: qos@ff270100 { 433 compatible = "rockchip,rk3528-qos", "syscon"; 434 reg = <0x0 0xff270100 0x0 0x20>; 435 }; 436 437 qos_rga2_m0ro: qos@ff270200 { 438 compatible = "rockchip,rk3528-qos", "syscon"; 439 reg = <0x0 0xff270200 0x0 0x20>; 440 }; 441 442 qos_rga2_m0wo: qos@ff270280 { 443 compatible = "rockchip,rk3528-qos", "syscon"; 444 reg = <0x0 0xff270280 0x0 0x20>; 445 }; 446 447 qos_sdmmc0: qos@ff270300 { 448 compatible = "rockchip,rk3528-qos", "syscon"; 449 reg = <0x0 0xff270300 0x0 0x20>; 450 }; 451 452 qos_usb2host: qos@ff270380 { 453 compatible = "rockchip,rk3528-qos", "syscon"; 454 reg = <0x0 0xff270380 0x0 0x20>; 455 }; 456 457 qos_vdpp: qos@ff270480 { 458 compatible = "rockchip,rk3528-qos", "syscon"; 459 reg = <0x0 0xff270480 0x0 0x20>; 460 }; 461 462 qos_vop: qos@ff270500 { 463 compatible = "rockchip,rk3528-qos", "syscon"; 464 reg = <0x0 0xff270500 0x0 0x20>; 465 }; 466 467 qos_emmc: qos@ff280000 { 468 compatible = "rockchip,rk3528-qos", "syscon"; 469 reg = <0x0 0xff280000 0x0 0x20>; 470 }; 471 472 qos_fspi: qos@ff280080 { 473 compatible = "rockchip,rk3528-qos", "syscon"; 474 reg = <0x0 0xff280080 0x0 0x20>; 475 }; 476 477 qos_gmac1: qos@ff280100 { 478 compatible = "rockchip,rk3528-qos", "syscon"; 479 reg = <0x0 0xff280100 0x0 0x20>; 480 }; 481 482 qos_pcie: qos@ff280180 { 483 compatible = "rockchip,rk3528-qos", "syscon"; 484 reg = <0x0 0xff280180 0x0 0x20>; 485 }; 486 487 qos_sdio0: qos@ff280200 { 488 compatible = "rockchip,rk3528-qos", "syscon"; 489 reg = <0x0 0xff280200 0x0 0x20>; 490 }; 491 492 qos_sdio1: qos@ff280280 { 493 compatible = "rockchip,rk3528-qos", "syscon"; 494 reg = <0x0 0xff280280 0x0 0x20>; 495 }; 496 497 qos_tsp: qos@ff280300 { 498 compatible = "rockchip,rk3528-qos", "syscon"; 499 reg = <0x0 0xff280300 0x0 0x20>; 500 }; 501 502 qos_usb3otg: qos@ff280380 { 503 compatible = "rockchip,rk3528-qos", "syscon"; 504 reg = <0x0 0xff280380 0x0 0x20>; 505 }; 506 507 qos_vpu: qos@ff280400 { 508 compatible = "rockchip,rk3528-qos", "syscon"; 509 reg = <0x0 0xff280400 0x0 0x20>; 510 }; 511 512 vpu_grf: syscon@ff340000 { 513 compatible = "rockchip,rk3528-vpu-grf", "syscon"; 514 reg = <0x0 0xff340000 0x0 0x8000>; 515 }; 516 517 pipe_phy_grf: syscon@ff348000 { 518 compatible = "rockchip,rk3528-pipe-phy-grf", "syscon"; 519 reg = <0x0 0xff348000 0x0 0x8000>; 520 }; 521 522 vo_grf: syscon@ff360000 { 523 compatible = "rockchip,rk3528-vo-grf", "syscon"; 524 reg = <0x0 0xff360000 0x0 0x10000>; 525 }; 526 527 cru: clock-controller@ff4a0000 { 528 compatible = "rockchip,rk3528-cru"; 529 reg = <0x0 0xff4a0000 0x0 0x30000>; 530 assigned-clocks = 531 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, 532 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 533 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, 534 <&cru CLK_MATRIX_500M_SRC>, 535 <&cru CLK_MATRIX_50M_SRC>, 536 <&cru CLK_MATRIX_100M_SRC>, 537 <&cru CLK_MATRIX_150M_SRC>, 538 <&cru CLK_MATRIX_200M_SRC>, 539 <&cru CLK_MATRIX_300M_SRC>, 540 <&cru CLK_MATRIX_339M_SRC>, 541 <&cru CLK_MATRIX_400M_SRC>, 542 <&cru CLK_MATRIX_600M_SRC>, 543 <&cru CLK_PPLL_50M_MATRIX>, 544 <&cru CLK_PPLL_100M_MATRIX>, 545 <&cru CLK_PPLL_125M_MATRIX>, 546 <&cru ACLK_BUS_VOPGL_ROOT>; 547 assigned-clock-rates = 548 <32768>, <1188000000>, 549 <1000000000>, <996000000>, 550 <408000000>, <250000000>, 551 <500000000>, 552 <50000000>, 553 <100000000>, 554 <150000000>, 555 <200000000>, 556 <300000000>, 557 <340000000>, 558 <400000000>, 559 <600000000>, 560 <50000000>, 561 <100000000>, 562 <125000000>, 563 <500000000>; 564 clocks = <&xin24m>, <&gmac0_clk>; 565 clock-names = "xin24m", "gmac0"; 566 #clock-cells = <1>; 567 #reset-cells = <1>; 568 }; 569 570 ioc_grf: syscon@ff540000 { 571 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 572 reg = <0x0 0xff540000 0x0 0x40000>; 573 }; 574 575 pmu: power-management@ff600000 { 576 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 577 reg = <0x0 0xff600000 0x0 0x2000>; 578 579 power: power-controller { 580 compatible = "rockchip,rk3528-power-controller"; 581 #power-domain-cells = <1>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 585 /* These power domains are grouped by VD_GPU */ 586 power-domain@RK3528_PD_GPU { 587 reg = <RK3528_PD_GPU>; 588 clocks = <&cru ACLK_GPU_MALI>, 589 <&cru PCLK_GPU_ROOT>; 590 pm_qos = <&qos_gpu_m0>, 591 <&qos_gpu_m1>; 592 #power-domain-cells = <0>; 593 }; 594 595 /* These power domains are grouped by VD_LOGIC */ 596 power-domain@RK3528_PD_RKVDEC { 597 reg = <RK3528_PD_RKVDEC>; 598 pm_qos = <&qos_rkvdec>; 599 #power-domain-cells = <0>; 600 status = "disabled"; 601 }; 602 power-domain@RK3528_PD_RKVENC { 603 reg = <RK3528_PD_RKVENC>; 604 pm_qos = <&qos_rkvenc>; 605 #power-domain-cells = <0>; 606 }; 607 power-domain@RK3528_PD_VO { 608 reg = <RK3528_PD_VO>; 609 pm_qos = <&qos_gmac0>, 610 <&qos_hdcp>, 611 <&qos_jpegdec>, 612 <&qos_rga2_m0ro>, 613 <&qos_rga2_m0wo>, 614 <&qos_sdmmc0>, 615 <&qos_usb2host>, 616 <&qos_vdpp>, 617 <&qos_vop>; 618 #power-domain-cells = <0>; 619 }; 620 power-domain@RK3528_PD_VPU { 621 reg = <RK3528_PD_VPU>; 622 pm_qos = <&qos_emmc>, 623 <&qos_fspi>, 624 <&qos_gmac1>, 625 <&qos_pcie>, 626 <&qos_sdio0>, 627 <&qos_sdio1>, 628 <&qos_tsp>, 629 <&qos_usb3otg>, 630 <&qos_vpu>; 631 #power-domain-cells = <0>; 632 }; 633 }; 634 }; 635 636 gpu: gpu@ff700000 { 637 compatible = "rockchip,rk3528-mali", "arm,mali-450"; 638 reg = <0x0 0xff700000 0x0 0x40000>; 639 assigned-clocks = <&cru ACLK_GPU_MALI>, 640 <&scmi_clk SCMI_CLK_GPU>; 641 assigned-clock-rates = <297000000>, <300000000>; 642 clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>; 643 clock-names = "bus", "core"; 644 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "gp", 652 "gpmmu", 653 "pp", 654 "pp0", 655 "ppmmu0", 656 "pp1", 657 "ppmmu1"; 658 operating-points-v2 = <&gpu_opp_table>; 659 power-domains = <&power RK3528_PD_GPU>; 660 resets = <&cru SRST_A_GPU>; 661 status = "disabled"; 662 }; 663 664 spi0: spi@ff9c0000 { 665 compatible = "rockchip,rk3528-spi", 666 "rockchip,rk3066-spi"; 667 reg = <0x0 0xff9c0000 0x0 0x1000>; 668 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 669 clock-names = "spiclk", "apb_pclk"; 670 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 671 dmas = <&dmac 25>, <&dmac 24>; 672 dma-names = "tx", "rx"; 673 power-domains = <&power RK3528_PD_RKVENC>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 spi1: spi@ff9d0000 { 680 compatible = "rockchip,rk3528-spi", 681 "rockchip,rk3066-spi"; 682 reg = <0x0 0xff9d0000 0x0 0x1000>; 683 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 684 clock-names = "spiclk", "apb_pclk"; 685 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 686 dmas = <&dmac 31>, <&dmac 30>; 687 dma-names = "tx", "rx"; 688 power-domains = <&power RK3528_PD_VPU>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 uart0: serial@ff9f0000 { 695 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 696 reg = <0x0 0xff9f0000 0x0 0x100>; 697 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 698 clock-names = "baudclk", "apb_pclk"; 699 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 700 dmas = <&dmac 9>, <&dmac 8>; 701 reg-io-width = <4>; 702 reg-shift = <2>; 703 status = "disabled"; 704 }; 705 706 uart1: serial@ff9f8000 { 707 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 708 reg = <0x0 0xff9f8000 0x0 0x100>; 709 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 710 clock-names = "baudclk", "apb_pclk"; 711 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 712 dmas = <&dmac 11>, <&dmac 10>; 713 power-domains = <&power RK3528_PD_RKVENC>; 714 reg-io-width = <4>; 715 reg-shift = <2>; 716 status = "disabled"; 717 }; 718 719 uart2: serial@ffa00000 { 720 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 721 reg = <0x0 0xffa00000 0x0 0x100>; 722 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 723 clock-names = "baudclk", "apb_pclk"; 724 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 725 dmas = <&dmac 13>, <&dmac 12>; 726 power-domains = <&power RK3528_PD_VPU>; 727 reg-io-width = <4>; 728 reg-shift = <2>; 729 status = "disabled"; 730 }; 731 732 uart3: serial@ffa08000 { 733 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 734 reg = <0x0 0xffa08000 0x0 0x100>; 735 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 736 clock-names = "baudclk", "apb_pclk"; 737 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 738 dmas = <&dmac 15>, <&dmac 14>; 739 power-domains = <&power RK3528_PD_RKVENC>; 740 reg-io-width = <4>; 741 reg-shift = <2>; 742 status = "disabled"; 743 }; 744 745 uart4: serial@ffa10000 { 746 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 747 reg = <0x0 0xffa10000 0x0 0x100>; 748 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 749 clock-names = "baudclk", "apb_pclk"; 750 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 751 dmas = <&dmac 17>, <&dmac 16>; 752 power-domains = <&power RK3528_PD_VO>; 753 reg-io-width = <4>; 754 reg-shift = <2>; 755 status = "disabled"; 756 }; 757 758 uart5: serial@ffa18000 { 759 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 760 reg = <0x0 0xffa18000 0x0 0x100>; 761 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 762 clock-names = "baudclk", "apb_pclk"; 763 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 764 dmas = <&dmac 19>, <&dmac 18>; 765 power-domains = <&power RK3528_PD_VPU>; 766 reg-io-width = <4>; 767 reg-shift = <2>; 768 status = "disabled"; 769 }; 770 771 uart6: serial@ffa20000 { 772 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 773 reg = <0x0 0xffa20000 0x0 0x100>; 774 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 775 clock-names = "baudclk", "apb_pclk"; 776 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 777 dmas = <&dmac 21>, <&dmac 20>; 778 power-domains = <&power RK3528_PD_VPU>; 779 reg-io-width = <4>; 780 reg-shift = <2>; 781 status = "disabled"; 782 }; 783 784 uart7: serial@ffa28000 { 785 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 786 reg = <0x0 0xffa28000 0x0 0x100>; 787 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 788 clock-names = "baudclk", "apb_pclk"; 789 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 790 dmas = <&dmac 23>, <&dmac 22>; 791 power-domains = <&power RK3528_PD_VPU>; 792 reg-io-width = <4>; 793 reg-shift = <2>; 794 status = "disabled"; 795 }; 796 797 i2c0: i2c@ffa50000 { 798 compatible = "rockchip,rk3528-i2c", 799 "rockchip,rk3399-i2c"; 800 reg = <0x0 0xffa50000 0x0 0x1000>; 801 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 802 clock-names = "i2c", "pclk"; 803 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 804 power-domains = <&power RK3528_PD_RKVENC>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c1: i2c@ffa58000 { 811 compatible = "rockchip,rk3528-i2c", 812 "rockchip,rk3399-i2c"; 813 reg = <0x0 0xffa58000 0x0 0x1000>; 814 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 815 clock-names = "i2c", "pclk"; 816 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 817 power-domains = <&power RK3528_PD_RKVENC>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 i2c2: i2c@ffa60000 { 824 compatible = "rockchip,rk3528-i2c", 825 "rockchip,rk3399-i2c"; 826 reg = <0x0 0xffa60000 0x0 0x1000>; 827 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 828 clock-names = "i2c", "pclk"; 829 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&i2c2m1_xfer>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 i2c3: i2c@ffa68000 { 838 compatible = "rockchip,rk3528-i2c", 839 "rockchip,rk3399-i2c"; 840 reg = <0x0 0xffa68000 0x0 0x1000>; 841 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 842 clock-names = "i2c", "pclk"; 843 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 844 power-domains = <&power RK3528_PD_VPU>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 i2c4: i2c@ffa70000 { 851 compatible = "rockchip,rk3528-i2c", 852 "rockchip,rk3399-i2c"; 853 reg = <0x0 0xffa70000 0x0 0x1000>; 854 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 855 clock-names = "i2c", "pclk"; 856 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&i2c4_xfer>; 859 power-domains = <&power RK3528_PD_VO>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 status = "disabled"; 863 }; 864 865 i2c5: i2c@ffa78000 { 866 compatible = "rockchip,rk3528-i2c", 867 "rockchip,rk3399-i2c"; 868 reg = <0x0 0xffa78000 0x0 0x1000>; 869 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 870 clock-names = "i2c", "pclk"; 871 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 872 power-domains = <&power RK3528_PD_VPU>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 i2c6: i2c@ffa80000 { 879 compatible = "rockchip,rk3528-i2c", 880 "rockchip,rk3399-i2c"; 881 reg = <0x0 0xffa80000 0x0 0x1000>; 882 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 883 clock-names = "i2c", "pclk"; 884 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&power RK3528_PD_VPU>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 status = "disabled"; 889 }; 890 891 i2c7: i2c@ffa88000 { 892 compatible = "rockchip,rk3528-i2c", 893 "rockchip,rk3399-i2c"; 894 reg = <0x0 0xffa88000 0x0 0x1000>; 895 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 896 clock-names = "i2c", "pclk"; 897 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&i2c7_xfer>; 900 power-domains = <&power RK3528_PD_VO>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 pwm0: pwm@ffa90000 { 907 compatible = "rockchip,rk3528-pwm", 908 "rockchip,rk3328-pwm"; 909 reg = <0x0 0xffa90000 0x0 0x10>; 910 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 911 clock-names = "pwm", "pclk"; 912 #pwm-cells = <3>; 913 status = "disabled"; 914 }; 915 916 pwm1: pwm@ffa90010 { 917 compatible = "rockchip,rk3528-pwm", 918 "rockchip,rk3328-pwm"; 919 reg = <0x0 0xffa90010 0x0 0x10>; 920 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 921 clock-names = "pwm", "pclk"; 922 #pwm-cells = <3>; 923 status = "disabled"; 924 }; 925 926 pwm2: pwm@ffa90020 { 927 compatible = "rockchip,rk3528-pwm", 928 "rockchip,rk3328-pwm"; 929 reg = <0x0 0xffa90020 0x0 0x10>; 930 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 931 clock-names = "pwm", "pclk"; 932 #pwm-cells = <3>; 933 status = "disabled"; 934 }; 935 936 pwm3: pwm@ffa90030 { 937 compatible = "rockchip,rk3528-pwm", 938 "rockchip,rk3328-pwm"; 939 reg = <0x0 0xffa90030 0x0 0x10>; 940 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 941 clock-names = "pwm", "pclk"; 942 #pwm-cells = <3>; 943 status = "disabled"; 944 }; 945 946 pwm4: pwm@ffa98000 { 947 compatible = "rockchip,rk3528-pwm", 948 "rockchip,rk3328-pwm"; 949 reg = <0x0 0xffa98000 0x0 0x10>; 950 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 951 clock-names = "pwm", "pclk"; 952 #pwm-cells = <3>; 953 status = "disabled"; 954 }; 955 956 pwm5: pwm@ffa98010 { 957 compatible = "rockchip,rk3528-pwm", 958 "rockchip,rk3328-pwm"; 959 reg = <0x0 0xffa98010 0x0 0x10>; 960 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 961 clock-names = "pwm", "pclk"; 962 #pwm-cells = <3>; 963 status = "disabled"; 964 }; 965 966 pwm6: pwm@ffa98020 { 967 compatible = "rockchip,rk3528-pwm", 968 "rockchip,rk3328-pwm"; 969 reg = <0x0 0xffa98020 0x0 0x10>; 970 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 971 clock-names = "pwm", "pclk"; 972 #pwm-cells = <3>; 973 status = "disabled"; 974 }; 975 976 pwm7: pwm@ffa98030 { 977 compatible = "rockchip,rk3528-pwm", 978 "rockchip,rk3328-pwm"; 979 reg = <0x0 0xffa98030 0x0 0x10>; 980 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 981 clock-names = "pwm", "pclk"; 982 #pwm-cells = <3>; 983 status = "disabled"; 984 }; 985 986 saradc: adc@ffae0000 { 987 compatible = "rockchip,rk3528-saradc"; 988 reg = <0x0 0xffae0000 0x0 0x10000>; 989 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 990 clock-names = "saradc", "apb_pclk"; 991 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 992 power-domains = <&power RK3528_PD_VPU>; 993 resets = <&cru SRST_P_SARADC>; 994 reset-names = "saradc-apb"; 995 #io-channel-cells = <1>; 996 status = "disabled"; 997 }; 998 999 gmac0: ethernet@ffbd0000 { 1000 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1001 reg = <0x0 0xffbd0000 0x0 0x10000>; 1002 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 1003 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 1004 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 1005 clock-names = "stmmaceth", "clk_mac_ref", 1006 "mac_clk_rx", "mac_clk_tx", 1007 "pclk_mac", "aclk_mac"; 1008 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1010 interrupt-names = "macirq", "eth_wake_irq"; 1011 phy-handle = <&rmii0_phy>; 1012 phy-mode = "rmii"; 1013 power-domains = <&power RK3528_PD_VO>; 1014 resets = <&cru SRST_A_MAC_VO>; 1015 reset-names = "stmmaceth"; 1016 rockchip,grf = <&vo_grf>; 1017 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1018 snps,mixed-burst; 1019 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1020 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1021 snps,tso; 1022 status = "disabled"; 1023 1024 mdio0: mdio { 1025 compatible = "snps,dwmac-mdio"; 1026 #address-cells = <0x1>; 1027 #size-cells = <0x0>; 1028 1029 rmii0_phy: ethernet-phy@2 { 1030 compatible = "ethernet-phy-ieee802.3-c22"; 1031 reg = <0x2>; 1032 clocks = <&cru CLK_MACPHY>; 1033 phy-is-integrated; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&fephym0_led_link>, 1036 <&fephym0_led_spd>; 1037 resets = <&cru SRST_MACPHY>; 1038 }; 1039 }; 1040 1041 gmac0_stmmac_axi_setup: stmmac-axi-config { 1042 snps,blen = <0 0 0 0 16 8 4>; 1043 snps,rd_osr_lmt = <8>; 1044 snps,wr_osr_lmt = <4>; 1045 }; 1046 1047 gmac0_mtl_rx_setup: rx-queues-config { 1048 snps,rx-queues-to-use = <1>; 1049 queue0 {}; 1050 }; 1051 1052 gmac0_mtl_tx_setup: tx-queues-config { 1053 snps,tx-queues-to-use = <1>; 1054 queue0 {}; 1055 }; 1056 }; 1057 1058 gmac1: ethernet@ffbe0000 { 1059 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1060 reg = <0x0 0xffbe0000 0x0 0x10000>; 1061 clocks = <&cru CLK_GMAC1_SRC_VPU>, 1062 <&cru CLK_GMAC1_RMII_VPU>, 1063 <&cru PCLK_MAC_VPU>, 1064 <&cru ACLK_MAC_VPU>; 1065 clock-names = "stmmaceth", 1066 "clk_mac_ref", 1067 "pclk_mac", 1068 "aclk_mac"; 1069 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1071 interrupt-names = "macirq", "eth_wake_irq"; 1072 power-domains = <&power RK3528_PD_VPU>; 1073 resets = <&cru SRST_A_MAC>; 1074 reset-names = "stmmaceth"; 1075 rockchip,grf = <&vpu_grf>; 1076 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1077 snps,mixed-burst; 1078 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1079 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1080 snps,tso; 1081 status = "disabled"; 1082 1083 mdio1: mdio { 1084 compatible = "snps,dwmac-mdio"; 1085 #address-cells = <0x1>; 1086 #size-cells = <0x0>; 1087 }; 1088 1089 gmac1_stmmac_axi_setup: stmmac-axi-config { 1090 snps,blen = <0 0 0 0 16 8 4>; 1091 snps,rd_osr_lmt = <8>; 1092 snps,wr_osr_lmt = <4>; 1093 }; 1094 1095 gmac1_mtl_rx_setup: rx-queues-config { 1096 snps,rx-queues-to-use = <1>; 1097 queue0 {}; 1098 }; 1099 1100 gmac1_mtl_tx_setup: tx-queues-config { 1101 snps,tx-queues-to-use = <1>; 1102 queue0 {}; 1103 }; 1104 }; 1105 1106 sdhci: mmc@ffbf0000 { 1107 compatible = "rockchip,rk3528-dwcmshc", 1108 "rockchip,rk3588-dwcmshc"; 1109 reg = <0x0 0xffbf0000 0x0 0x10000>; 1110 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 1111 <&cru CCLK_SRC_EMMC>; 1112 assigned-clock-rates = <200000000>, <24000000>, 1113 <200000000>; 1114 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1115 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1116 <&cru TCLK_EMMC>; 1117 clock-names = "core", "bus", "axi", "block", "timer"; 1118 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1119 max-frequency = <200000000>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, 1122 <&emmc_strb>; 1123 power-domains = <&power RK3528_PD_VPU>; 1124 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1125 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1126 <&cru SRST_T_EMMC>; 1127 reset-names = "core", "bus", "axi", "block", "timer"; 1128 status = "disabled"; 1129 }; 1130 1131 sdio0: mmc@ffc10000 { 1132 compatible = "rockchip,rk3528-dw-mshc", 1133 "rockchip,rk3288-dw-mshc"; 1134 reg = <0x0 0xffc10000 0x0 0x4000>; 1135 clocks = <&cru HCLK_SDIO0>, 1136 <&cru CCLK_SRC_SDIO0>, 1137 <&cru SCLK_SDIO0_DRV>, 1138 <&cru SCLK_SDIO0_SAMPLE>; 1139 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1140 fifo-depth = <0x100>; 1141 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1142 max-frequency = <200000000>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; 1145 power-domains = <&power RK3528_PD_VPU>; 1146 resets = <&cru SRST_H_SDIO0>; 1147 reset-names = "reset"; 1148 status = "disabled"; 1149 }; 1150 1151 sdio1: mmc@ffc20000 { 1152 compatible = "rockchip,rk3528-dw-mshc", 1153 "rockchip,rk3288-dw-mshc"; 1154 reg = <0x0 0xffc20000 0x0 0x4000>; 1155 clocks = <&cru HCLK_SDIO1>, 1156 <&cru CCLK_SRC_SDIO1>, 1157 <&cru SCLK_SDIO1_DRV>, 1158 <&cru SCLK_SDIO1_SAMPLE>; 1159 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1160 fifo-depth = <0x100>; 1161 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1162 max-frequency = <200000000>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; 1165 power-domains = <&power RK3528_PD_VPU>; 1166 resets = <&cru SRST_H_SDIO1>; 1167 reset-names = "reset"; 1168 status = "disabled"; 1169 }; 1170 1171 sdmmc: mmc@ffc30000 { 1172 compatible = "rockchip,rk3528-dw-mshc", 1173 "rockchip,rk3288-dw-mshc"; 1174 reg = <0x0 0xffc30000 0x0 0x4000>; 1175 clocks = <&cru HCLK_SDMMC0>, 1176 <&cru CCLK_SRC_SDMMC0>, 1177 <&cru SCLK_SDMMC_DRV>, 1178 <&cru SCLK_SDMMC_SAMPLE>; 1179 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1180 fifo-depth = <0x100>; 1181 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1182 max-frequency = <150000000>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, 1185 <&sdmmc_det>; 1186 power-domains = <&power RK3528_PD_VO>; 1187 resets = <&cru SRST_H_SDMMC0>; 1188 reset-names = "reset"; 1189 rockchip,default-sample-phase = <90>; 1190 status = "disabled"; 1191 }; 1192 1193 dmac: dma-controller@ffd60000 { 1194 compatible = "arm,pl330", "arm,primecell"; 1195 reg = <0x0 0xffd60000 0x0 0x4000>; 1196 clocks = <&cru ACLK_DMAC>; 1197 clock-names = "apb_pclk"; 1198 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1207 #dma-cells = <1>; 1208 arm,pl330-periph-burst; 1209 }; 1210 1211 combphy: phy@ffdc0000 { 1212 compatible = "rockchip,rk3528-naneng-combphy"; 1213 reg = <0x0 0xffdc0000 0x0 0x10000>; 1214 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; 1215 assigned-clock-rates = <100000000>; 1216 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, 1217 <&cru PCLK_PCIE_PHY>, 1218 <&cru PCLK_PIPE_GRF>; 1219 clock-names = "ref", "apb", "pipe"; 1220 power-domains = <&power RK3528_PD_VPU>; 1221 resets = <&cru SRST_PCIE_PIPE_PHY>, 1222 <&cru SRST_P_PCIE_PHY>; 1223 reset-names = "phy", "apb"; 1224 #phy-cells = <1>; 1225 rockchip,pipe-grf = <&vpu_grf>; 1226 rockchip,pipe-phy-grf = <&pipe_phy_grf>; 1227 status = "disabled"; 1228 }; 1229 }; 1230}; 1231 1232#include "rk3528-pinctrl.dtsi"
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