rk3399-op1.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
  4 */
  5
  6#include "rk3399-base.dtsi"
  7
  8/ {
  9	cluster0_opp: opp-table-0 {
 10		compatible = "operating-points-v2";
 11		opp-shared;
 12
 13		opp00 {
 14			opp-hz = /bits/ 64 <408000000>;
 15			opp-microvolt = <800000 800000 1150000>;
 16			clock-latency-ns = <40000>;
 17		};
 18		opp01 {
 19			opp-hz = /bits/ 64 <600000000>;
 20			opp-microvolt = <825000 825000 1150000>;
 21		};
 22		opp02 {
 23			opp-hz = /bits/ 64 <816000000>;
 24			opp-microvolt = <850000 850000 1150000>;
 25		};
 26		opp03 {
 27			opp-hz = /bits/ 64 <1008000000>;
 28			opp-microvolt = <900000 900000 1150000>;
 29		};
 30		opp04 {
 31			opp-hz = /bits/ 64 <1200000000>;
 32			opp-microvolt = <975000 975000 1150000>;
 33		};
 34		opp05 {
 35			opp-hz = /bits/ 64 <1416000000>;
 36			opp-microvolt = <1100000 1100000 1150000>;
 37		};
 38		opp06 {
 39			opp-hz = /bits/ 64 <1512000000>;
 40			opp-microvolt = <1150000 1150000 1150000>;
 41		};
 42	};
 43
 44	cluster1_opp: opp-table-1 {
 45		compatible = "operating-points-v2";
 46		opp-shared;
 47
 48		opp00 {
 49			opp-hz = /bits/ 64 <408000000>;
 50			opp-microvolt = <800000 800000 1250000>;
 51			clock-latency-ns = <40000>;
 52		};
 53		opp01 {
 54			opp-hz = /bits/ 64 <600000000>;
 55			opp-microvolt = <800000 800000 1250000>;
 56		};
 57		opp02 {
 58			opp-hz = /bits/ 64 <816000000>;
 59			opp-microvolt = <825000 825000 1250000>;
 60		};
 61		opp03 {
 62			opp-hz = /bits/ 64 <1008000000>;
 63			opp-microvolt = <850000 850000 1250000>;
 64		};
 65		opp04 {
 66			opp-hz = /bits/ 64 <1200000000>;
 67			opp-microvolt = <900000 900000 1250000>;
 68		};
 69		opp05 {
 70			opp-hz = /bits/ 64 <1416000000>;
 71			opp-microvolt = <975000 975000 1250000>;
 72		};
 73		opp06 {
 74			opp-hz = /bits/ 64 <1608000000>;
 75			opp-microvolt = <1050000 1050000 1250000>;
 76		};
 77		opp07 {
 78			opp-hz = /bits/ 64 <1800000000>;
 79			opp-microvolt = <1150000 1150000 1250000>;
 80		};
 81		opp08 {
 82			opp-hz = /bits/ 64 <2016000000>;
 83			opp-microvolt = <1250000 1250000 1250000>;
 84		};
 85	};
 86
 87	gpu_opp_table: opp-table-2 {
 88		compatible = "operating-points-v2";
 89
 90		opp00 {
 91			opp-hz = /bits/ 64 <200000000>;
 92			opp-microvolt = <800000 800000 1075000>;
 93		};
 94		opp01 {
 95			opp-hz = /bits/ 64 <297000000>;
 96			opp-microvolt = <800000 800000 1075000>;
 97		};
 98		opp02 {
 99			opp-hz = /bits/ 64 <400000000>;
100			opp-microvolt = <825000 825000 1075000>;
101		};
102		opp03 {
103			opp-hz = /bits/ 64 <500000000>;
104			opp-microvolt = <850000 850000 1075000>;
105		};
106		opp04 {
107			opp-hz = /bits/ 64 <600000000>;
108			opp-microvolt = <925000 925000 1075000>;
109		};
110		opp05 {
111			opp-hz = /bits/ 64 <800000000>;
112			opp-microvolt = <1075000 1075000 1075000>;
113		};
114	};
115
116	dmc_opp_table: opp-table-3 {
117		compatible = "operating-points-v2";
118
119		opp00 {
120			opp-hz = /bits/ 64 <400000000>;
121			opp-microvolt = <900000 900000 925000>;
122		};
123		opp01 {
124			opp-hz = /bits/ 64 <666000000>;
125			opp-microvolt = <900000 900000 925000>;
126		};
127		opp02 {
128			opp-hz = /bits/ 64 <800000000>;
129			opp-microvolt = <900000 900000 925000>;
130		};
131		opp03 {
132			opp-hz = /bits/ 64 <928000000>;
133			opp-microvolt = <925000 925000 925000>;
134		};
135	};
136};
137
138&cpu_l0 {
139	operating-points-v2 = <&cluster0_opp>;
140};
141
142&cpu_l1 {
143	operating-points-v2 = <&cluster0_opp>;
144};
145
146&cpu_l2 {
147	operating-points-v2 = <&cluster0_opp>;
148};
149
150&cpu_l3 {
151	operating-points-v2 = <&cluster0_opp>;
152};
153
154&cpu_b0 {
155	operating-points-v2 = <&cluster1_opp>;
156};
157
158&cpu_b1 {
159	operating-points-v2 = <&cluster1_opp>;
160};
161
162&dmc {
163	operating-points-v2 = <&dmc_opp_table>;
164};
165
166&gpu {
167	operating-points-v2 = <&gpu_opp_table>;
168};