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rk3368.dtsi
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linux-6.19.14/arch/arm64/boot/dts/rockchip/rk3368.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6#include <dt-bindings/clock/rk3368-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3368-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3368"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 spi0 = &spi0; 38 spi1 = &spi1; 39 spi2 = &spi2; 40 }; 41 42 cpus { 43 #address-cells = <0x2>; 44 #size-cells = <0x0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu_b0>; 50 }; 51 core1 { 52 cpu = <&cpu_b1>; 53 }; 54 core2 { 55 cpu = <&cpu_b2>; 56 }; 57 core3 { 58 cpu = <&cpu_b3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu_l0>; 65 }; 66 core1 { 67 cpu = <&cpu_l1>; 68 }; 69 core2 { 70 cpu = <&cpu_l2>; 71 }; 72 core3 { 73 cpu = <&cpu_l3>; 74 }; 75 }; 76 }; 77 78 cpu_l0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 #cooling-cells = <2>; /* min followed by max */ 84 }; 85 86 cpu_l1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x1>; 90 enable-method = "psci"; 91 #cooling-cells = <2>; /* min followed by max */ 92 }; 93 94 cpu_l2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x0 0x2>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; /* min followed by max */ 100 }; 101 102 cpu_l3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x0 0x3>; 106 enable-method = "psci"; 107 #cooling-cells = <2>; /* min followed by max */ 108 }; 109 110 cpu_b0: cpu@100 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a53"; 113 reg = <0x0 0x100>; 114 enable-method = "psci"; 115 #cooling-cells = <2>; /* min followed by max */ 116 }; 117 118 cpu_b1: cpu@101 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a53"; 121 reg = <0x0 0x101>; 122 enable-method = "psci"; 123 #cooling-cells = <2>; /* min followed by max */ 124 }; 125 126 cpu_b2: cpu@102 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a53"; 129 reg = <0x0 0x102>; 130 enable-method = "psci"; 131 #cooling-cells = <2>; /* min followed by max */ 132 }; 133 134 cpu_b3: cpu@103 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 reg = <0x0 0x103>; 138 enable-method = "psci"; 139 #cooling-cells = <2>; /* min followed by max */ 140 }; 141 }; 142 143 display_subsystem: display-subsystem { 144 compatible = "rockchip,display-subsystem"; 145 ports = <&vop_out>; 146 status = "disabled"; 147 }; 148 149 arm-pmu { 150 compatible = "arm,cortex-a53-pmu"; 151 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 159 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 160 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 161 <&cpu_b2>, <&cpu_b3>; 162 }; 163 164 psci { 165 compatible = "arm,psci-0.2"; 166 method = "smc"; 167 }; 168 169 timer { 170 compatible = "arm,armv8-timer"; 171 interrupts = <GIC_PPI 13 172 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 173 <GIC_PPI 14 174 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 11 176 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 178 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 179 }; 180 181 xin24m: oscillator { 182 compatible = "fixed-clock"; 183 clock-frequency = <24000000>; 184 clock-output-names = "xin24m"; 185 #clock-cells = <0>; 186 }; 187 188 sdmmc: mmc@ff0c0000 { 189 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 190 reg = <0x0 0xff0c0000 0x0 0x4000>; 191 max-frequency = <150000000>; 192 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 193 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 194 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 195 fifo-depth = <0x100>; 196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 197 resets = <&cru SRST_MMC0>; 198 reset-names = "reset"; 199 status = "disabled"; 200 }; 201 202 sdio0: mmc@ff0d0000 { 203 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 204 reg = <0x0 0xff0d0000 0x0 0x4000>; 205 max-frequency = <150000000>; 206 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 207 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 208 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 209 fifo-depth = <0x100>; 210 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 211 resets = <&cru SRST_SDIO0>; 212 reset-names = "reset"; 213 status = "disabled"; 214 }; 215 216 emmc: mmc@ff0f0000 { 217 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 218 reg = <0x0 0xff0f0000 0x0 0x4000>; 219 max-frequency = <150000000>; 220 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 221 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 223 fifo-depth = <0x100>; 224 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 225 resets = <&cru SRST_EMMC>; 226 reset-names = "reset"; 227 status = "disabled"; 228 }; 229 230 saradc: saradc@ff100000 { 231 compatible = "rockchip,saradc"; 232 reg = <0x0 0xff100000 0x0 0x100>; 233 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 234 #io-channel-cells = <1>; 235 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 236 clock-names = "saradc", "apb_pclk"; 237 resets = <&cru SRST_SARADC>; 238 reset-names = "saradc-apb"; 239 status = "disabled"; 240 }; 241 242 spi0: spi@ff110000 { 243 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 244 reg = <0x0 0xff110000 0x0 0x1000>; 245 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 246 clock-names = "spiclk", "apb_pclk"; 247 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 status = "disabled"; 253 }; 254 255 spi1: spi@ff120000 { 256 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 257 reg = <0x0 0xff120000 0x0 0x1000>; 258 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 259 clock-names = "spiclk", "apb_pclk"; 260 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 status = "disabled"; 266 }; 267 268 spi2: spi@ff130000 { 269 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 270 reg = <0x0 0xff130000 0x0 0x1000>; 271 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 272 clock-names = "spiclk", "apb_pclk"; 273 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 i2c2: i2c@ff140000 { 282 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 283 reg = <0x0 0xff140000 0x0 0x1000>; 284 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 clock-names = "i2c"; 288 clocks = <&cru PCLK_I2C2>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&i2c2_xfer>; 291 status = "disabled"; 292 }; 293 294 i2c3: i2c@ff150000 { 295 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 296 reg = <0x0 0xff150000 0x0 0x1000>; 297 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clock-names = "i2c"; 301 clocks = <&cru PCLK_I2C3>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c3_xfer>; 304 status = "disabled"; 305 }; 306 307 i2c4: i2c@ff160000 { 308 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 309 reg = <0x0 0xff160000 0x0 0x1000>; 310 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clock-names = "i2c"; 314 clocks = <&cru PCLK_I2C4>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&i2c4_xfer>; 317 status = "disabled"; 318 }; 319 320 i2c5: i2c@ff170000 { 321 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 322 reg = <0x0 0xff170000 0x0 0x1000>; 323 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clock-names = "i2c"; 327 clocks = <&cru PCLK_I2C5>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c5_xfer>; 330 status = "disabled"; 331 }; 332 333 uart0: serial@ff180000 { 334 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 335 reg = <0x0 0xff180000 0x0 0x100>; 336 clock-frequency = <24000000>; 337 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 338 clock-names = "baudclk", "apb_pclk"; 339 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 340 reg-shift = <2>; 341 reg-io-width = <4>; 342 status = "disabled"; 343 }; 344 345 uart1: serial@ff190000 { 346 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff190000 0x0 0x100>; 348 clock-frequency = <24000000>; 349 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 350 clock-names = "baudclk", "apb_pclk"; 351 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 352 reg-shift = <2>; 353 reg-io-width = <4>; 354 status = "disabled"; 355 }; 356 357 uart3: serial@ff1b0000 { 358 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 359 reg = <0x0 0xff1b0000 0x0 0x100>; 360 clock-frequency = <24000000>; 361 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 362 clock-names = "baudclk", "apb_pclk"; 363 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 364 reg-shift = <2>; 365 reg-io-width = <4>; 366 status = "disabled"; 367 }; 368 369 uart4: serial@ff1c0000 { 370 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 371 reg = <0x0 0xff1c0000 0x0 0x100>; 372 clock-frequency = <24000000>; 373 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 374 clock-names = "baudclk", "apb_pclk"; 375 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 376 reg-shift = <2>; 377 reg-io-width = <4>; 378 status = "disabled"; 379 }; 380 381 dmac_peri: dma-controller@ff250000 { 382 compatible = "arm,pl330", "arm,primecell"; 383 reg = <0x0 0xff250000 0x0 0x4000>; 384 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 386 #dma-cells = <1>; 387 arm,pl330-broken-no-flushp; 388 arm,pl330-periph-burst; 389 clocks = <&cru ACLK_DMAC_PERI>; 390 clock-names = "apb_pclk"; 391 }; 392 393 thermal-zones { 394 cpu_thermal: cpu-thermal { 395 polling-delay-passive = <100>; /* milliseconds */ 396 polling-delay = <5000>; /* milliseconds */ 397 398 thermal-sensors = <&tsadc 0>; 399 400 trips { 401 cpu_alert0: cpu_alert0 { 402 temperature = <75000>; /* millicelsius */ 403 hysteresis = <2000>; /* millicelsius */ 404 type = "passive"; 405 }; 406 cpu_alert1: cpu_alert1 { 407 temperature = <80000>; /* millicelsius */ 408 hysteresis = <2000>; /* millicelsius */ 409 type = "passive"; 410 }; 411 cpu_crit: cpu_crit { 412 temperature = <95000>; /* millicelsius */ 413 hysteresis = <2000>; /* millicelsius */ 414 type = "critical"; 415 }; 416 }; 417 418 cooling-maps { 419 map0 { 420 trip = <&cpu_alert0>; 421 cooling-device = 422 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 423 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 424 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 425 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 426 }; 427 map1 { 428 trip = <&cpu_alert1>; 429 cooling-device = 430 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 431 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 432 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 433 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 434 }; 435 }; 436 }; 437 438 gpu_thermal: gpu-thermal { 439 polling-delay-passive = <100>; /* milliseconds */ 440 polling-delay = <5000>; /* milliseconds */ 441 442 thermal-sensors = <&tsadc 1>; 443 444 trips { 445 gpu_alert0: gpu_alert0 { 446 temperature = <80000>; /* millicelsius */ 447 hysteresis = <2000>; /* millicelsius */ 448 type = "passive"; 449 }; 450 gpu_crit: gpu_crit { 451 temperature = <115000>; /* millicelsius */ 452 hysteresis = <2000>; /* millicelsius */ 453 type = "critical"; 454 }; 455 }; 456 457 cooling-maps { 458 map0 { 459 trip = <&gpu_alert0>; 460 cooling-device = 461 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 462 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 463 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 464 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 465 }; 466 }; 467 }; 468 }; 469 470 tsadc: tsadc@ff280000 { 471 compatible = "rockchip,rk3368-tsadc"; 472 reg = <0x0 0xff280000 0x0 0x100>; 473 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 475 clock-names = "tsadc", "apb_pclk"; 476 resets = <&cru SRST_TSADC>; 477 reset-names = "tsadc-apb"; 478 pinctrl-names = "init", "default", "sleep"; 479 pinctrl-0 = <&otp_pin>; 480 pinctrl-1 = <&otp_out>; 481 pinctrl-2 = <&otp_pin>; 482 #thermal-sensor-cells = <1>; 483 rockchip,hw-tshut-temp = <95000>; 484 status = "disabled"; 485 }; 486 487 gmac: ethernet@ff290000 { 488 compatible = "rockchip,rk3368-gmac"; 489 reg = <0x0 0xff290000 0x0 0x10000>; 490 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "macirq"; 492 rockchip,grf = <&grf>; 493 clocks = <&cru SCLK_MAC>, 494 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 495 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 496 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 497 clock-names = "stmmaceth", 498 "mac_clk_rx", "mac_clk_tx", 499 "clk_mac_ref", "clk_mac_refout", 500 "aclk_mac", "pclk_mac"; 501 status = "disabled"; 502 }; 503 504 usb_host0_ehci: usb@ff500000 { 505 compatible = "generic-ehci"; 506 reg = <0x0 0xff500000 0x0 0x100>; 507 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&cru HCLK_HOST0>; 509 status = "disabled"; 510 }; 511 512 usb_otg: usb@ff580000 { 513 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 514 "snps,dwc2"; 515 reg = <0x0 0xff580000 0x0 0x40000>; 516 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru HCLK_OTG0>; 518 clock-names = "otg"; 519 dr_mode = "otg"; 520 g-np-tx-fifo-size = <16>; 521 g-rx-fifo-size = <275>; 522 g-tx-fifo-size = <256 128 128 64 64 32>; 523 status = "disabled"; 524 }; 525 526 dmac_bus: dma-controller@ff600000 { 527 compatible = "arm,pl330", "arm,primecell"; 528 reg = <0x0 0xff600000 0x0 0x4000>; 529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 531 #dma-cells = <1>; 532 arm,pl330-broken-no-flushp; 533 arm,pl330-periph-burst; 534 clocks = <&cru ACLK_DMAC_BUS>; 535 clock-names = "apb_pclk"; 536 }; 537 538 i2c0: i2c@ff650000 { 539 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 540 reg = <0x0 0xff650000 0x0 0x1000>; 541 clocks = <&cru PCLK_I2C0>; 542 clock-names = "i2c"; 543 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&i2c0_xfer>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 i2c1: i2c@ff660000 { 552 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 553 reg = <0x0 0xff660000 0x0 0x1000>; 554 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clock-names = "i2c"; 558 clocks = <&cru PCLK_I2C1>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c1_xfer>; 561 status = "disabled"; 562 }; 563 564 pwm0: pwm@ff680000 { 565 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 566 reg = <0x0 0xff680000 0x0 0x10>; 567 #pwm-cells = <3>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pwm0_pin>; 570 clocks = <&cru PCLK_PWM1>; 571 status = "disabled"; 572 }; 573 574 pwm1: pwm@ff680010 { 575 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 576 reg = <0x0 0xff680010 0x0 0x10>; 577 #pwm-cells = <3>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pwm1_pin>; 580 clocks = <&cru PCLK_PWM1>; 581 status = "disabled"; 582 }; 583 584 pwm2: pwm@ff680020 { 585 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 586 reg = <0x0 0xff680020 0x0 0x10>; 587 #pwm-cells = <3>; 588 clocks = <&cru PCLK_PWM1>; 589 status = "disabled"; 590 }; 591 592 pwm3: pwm@ff680030 { 593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 594 reg = <0x0 0xff680030 0x0 0x10>; 595 #pwm-cells = <3>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pwm3_pin>; 598 clocks = <&cru PCLK_PWM1>; 599 status = "disabled"; 600 }; 601 602 uart2: serial@ff690000 { 603 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 604 reg = <0x0 0xff690000 0x0 0x100>; 605 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 606 clock-names = "baudclk", "apb_pclk"; 607 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&uart2_xfer>; 610 reg-shift = <2>; 611 reg-io-width = <4>; 612 status = "disabled"; 613 }; 614 615 mbox: mbox@ff6b0000 { 616 compatible = "rockchip,rk3368-mailbox"; 617 reg = <0x0 0xff6b0000 0x0 0x1000>; 618 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cru PCLK_MAILBOX>; 623 clock-names = "pclk_mailbox"; 624 #mbox-cells = <1>; 625 status = "disabled"; 626 }; 627 628 pmu: power-management@ff730000 { 629 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd"; 630 reg = <0x0 0xff730000 0x0 0x1000>; 631 632 power: power-controller { 633 compatible = "rockchip,rk3368-power-controller"; 634 #power-domain-cells = <1>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 638 /* 639 * Note: Although SCLK_* are the working clocks 640 * of device without including on the NOC, needed for 641 * synchronous reset. 642 * 643 * The clocks on the which NOC: 644 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 645 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 646 * ACLK_RGA is on ACLK_RGA_NIU. 647 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 648 * 649 * Which clock are device clocks: 650 * clocks devices 651 * *_IEP IEP:Image Enhancement Processor 652 * *_ISP ISP:Image Signal Processing 653 * *_VIP VIP:Video Input Processor 654 * *_VOP* VOP:Visual Output Processor 655 * *_RGA RGA 656 * *_EDP* EDP 657 * *_DPHY* LVDS 658 * *_HDMI HDMI 659 * *_MIPI_* MIPI 660 */ 661 power-domain@RK3368_PD_VIO { 662 reg = <RK3368_PD_VIO>; 663 clocks = <&cru ACLK_IEP>, 664 <&cru ACLK_ISP>, 665 <&cru ACLK_VIP>, 666 <&cru ACLK_RGA>, 667 <&cru ACLK_VOP>, 668 <&cru ACLK_VOP_IEP>, 669 <&cru DCLK_VOP>, 670 <&cru HCLK_IEP>, 671 <&cru HCLK_ISP>, 672 <&cru HCLK_RGA>, 673 <&cru HCLK_VIP>, 674 <&cru HCLK_VOP>, 675 <&cru HCLK_VIO_HDCPMMU>, 676 <&cru PCLK_EDP_CTRL>, 677 <&cru PCLK_HDMI_CTRL>, 678 <&cru PCLK_HDCP>, 679 <&cru PCLK_ISP>, 680 <&cru PCLK_VIP>, 681 <&cru PCLK_DPHYRX>, 682 <&cru PCLK_DPHYTX0>, 683 <&cru PCLK_MIPI_CSI>, 684 <&cru PCLK_MIPI_DSI0>, 685 <&cru SCLK_VOP0_PWM>, 686 <&cru SCLK_EDP_24M>, 687 <&cru SCLK_EDP>, 688 <&cru SCLK_HDCP>, 689 <&cru SCLK_ISP>, 690 <&cru SCLK_RGA>, 691 <&cru SCLK_HDMI_CEC>, 692 <&cru SCLK_HDMI_HDCP>; 693 pm_qos = <&qos_iep>, 694 <&qos_isp_r0>, 695 <&qos_isp_r1>, 696 <&qos_isp_w0>, 697 <&qos_isp_w1>, 698 <&qos_vip>, 699 <&qos_vop>, 700 <&qos_rga_r>, 701 <&qos_rga_w>; 702 #power-domain-cells = <0>; 703 }; 704 705 /* 706 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 707 * (video endecoder & decoder) clocks that on the 708 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 709 */ 710 power-domain@RK3368_PD_VIDEO { 711 reg = <RK3368_PD_VIDEO>; 712 clocks = <&cru ACLK_VIDEO>, 713 <&cru HCLK_VIDEO>, 714 <&cru SCLK_HEVC_CABAC>, 715 <&cru SCLK_HEVC_CORE>; 716 pm_qos = <&qos_hevc_r>, 717 <&qos_vpu_r>, 718 <&qos_vpu_w>; 719 #power-domain-cells = <0>; 720 }; 721 722 /* 723 * Note: ACLK_GPU is the GPU clock, 724 * and on the ACLK_GPU_NIU (NOC). 725 */ 726 power-domain@RK3368_PD_GPU_1 { 727 reg = <RK3368_PD_GPU_1>; 728 clocks = <&cru ACLK_GPU_CFG>, 729 <&cru ACLK_GPU_MEM>, 730 <&cru SCLK_GPU_CORE>; 731 pm_qos = <&qos_gpu>; 732 #power-domain-cells = <0>; 733 }; 734 }; 735 }; 736 737 pmugrf: syscon@ff738000 { 738 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; 739 reg = <0x0 0xff738000 0x0 0x1000>; 740 741 pmu_io_domains: io-domains { 742 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 743 status = "disabled"; 744 }; 745 746 reboot-mode { 747 compatible = "syscon-reboot-mode"; 748 offset = <0x200>; 749 mode-normal = <BOOT_NORMAL>; 750 mode-recovery = <BOOT_RECOVERY>; 751 mode-bootloader = <BOOT_FASTBOOT>; 752 mode-loader = <BOOT_BL_DOWNLOAD>; 753 }; 754 }; 755 756 cru: clock-controller@ff760000 { 757 compatible = "rockchip,rk3368-cru"; 758 reg = <0x0 0xff760000 0x0 0x1000>; 759 clocks = <&xin24m>; 760 clock-names = "xin24m"; 761 rockchip,grf = <&grf>; 762 #clock-cells = <1>; 763 #reset-cells = <1>; 764 }; 765 766 grf: syscon@ff770000 { 767 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; 768 reg = <0x0 0xff770000 0x0 0x1000>; 769 770 io_domains: io-domains { 771 compatible = "rockchip,rk3368-io-voltage-domain"; 772 status = "disabled"; 773 }; 774 }; 775 776 wdt: watchdog@ff800000 { 777 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 778 reg = <0x0 0xff800000 0x0 0x100>; 779 clocks = <&cru PCLK_WDT>; 780 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 781 status = "disabled"; 782 }; 783 784 timer0: timer@ff810000 { 785 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 786 reg = <0x0 0xff810000 0x0 0x20>; 787 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 789 clock-names = "pclk", "timer"; 790 }; 791 792 spdif: spdif@ff880000 { 793 compatible = "rockchip,rk3368-spdif"; 794 reg = <0x0 0xff880000 0x0 0x1000>; 795 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 797 clock-names = "mclk", "hclk"; 798 dmas = <&dmac_bus 3>; 799 dma-names = "tx"; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&spdif_tx>; 802 #sound-dai-cells = <0>; 803 status = "disabled"; 804 }; 805 806 i2s_2ch: i2s-2ch@ff890000 { 807 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 808 reg = <0x0 0xff890000 0x0 0x1000>; 809 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 810 clock-names = "i2s_clk", "i2s_hclk"; 811 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; 812 dmas = <&dmac_bus 6>, <&dmac_bus 7>; 813 dma-names = "tx", "rx"; 814 #sound-dai-cells = <0>; 815 status = "disabled"; 816 }; 817 818 i2s_8ch: i2s-8ch@ff898000 { 819 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 820 reg = <0x0 0xff898000 0x0 0x1000>; 821 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 822 clock-names = "i2s_clk", "i2s_hclk"; 823 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; 824 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 825 dma-names = "tx", "rx"; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&i2s_8ch_bus>; 828 #sound-dai-cells = <0>; 829 status = "disabled"; 830 }; 831 832 iep_mmu: iommu@ff900800 { 833 compatible = "rockchip,iommu"; 834 reg = <0x0 0xff900800 0x0 0x100>; 835 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 837 clock-names = "aclk", "iface"; 838 power-domains = <&power RK3368_PD_VIO>; 839 #iommu-cells = <0>; 840 status = "disabled"; 841 }; 842 843 isp_mmu: iommu@ff914000 { 844 compatible = "rockchip,iommu"; 845 reg = <0x0 0xff914000 0x0 0x100>, 846 <0x0 0xff915000 0x0 0x100>; 847 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 849 clock-names = "aclk", "iface"; 850 #iommu-cells = <0>; 851 power-domains = <&power RK3368_PD_VIO>; 852 rockchip,disable-mmu-reset; 853 status = "disabled"; 854 }; 855 856 vop: vop@ff930000 { 857 compatible = "rockchip,rk3368-vop"; 858 reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>; 859 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 860 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 861 assigned-clock-rates = <400000000>, <200000000>; 862 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 863 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 864 iommus = <&vop_mmu>; 865 power-domains = <&power RK3368_PD_VIO>; 866 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 867 reset-names = "axi", "ahb", "dclk"; 868 status = "disabled"; 869 870 vop_out: port { 871 #address-cells = <1>; 872 #size-cells = <0>; 873 874 vop_out_dsi: endpoint@0 { 875 reg = <0>; 876 remote-endpoint = <&dsi_in_vop>; 877 }; 878 }; 879 }; 880 881 vop_mmu: iommu@ff930300 { 882 compatible = "rockchip,iommu"; 883 reg = <0x0 0xff930300 0x0 0x100>; 884 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 886 clock-names = "aclk", "iface"; 887 power-domains = <&power RK3368_PD_VIO>; 888 #iommu-cells = <0>; 889 status = "disabled"; 890 }; 891 892 mipi_dsi: dsi@ff960000 { 893 compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi"; 894 reg = <0x0 0xff960000 0x0 0x4000>; 895 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cru PCLK_MIPI_DSI0>; 897 clock-names = "pclk"; 898 phys = <&dphy>; 899 phy-names = "dphy"; 900 power-domains = <&power RK3368_PD_VIO>; 901 resets = <&cru SRST_MIPIDSI0>; 902 reset-names = "apb"; 903 rockchip,grf = <&grf>; 904 status = "disabled"; 905 906 ports { 907 #address-cells = <1>; 908 #size-cells = <0>; 909 910 mipi_in: port@0 { 911 reg = <0>; 912 913 dsi_in_vop: endpoint { 914 remote-endpoint = <&vop_out_dsi>; 915 }; 916 }; 917 918 mipi_out: port@1 { 919 reg = <1>; 920 }; 921 922 }; 923 }; 924 925 dphy: phy@ff968000 { 926 compatible = "rockchip,rk3368-dsi-dphy"; 927 reg = <0x0 0xff968000 0x0 0x4000>; 928 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; 929 clock-names = "ref", "pclk"; 930 #phy-cells = <0>; 931 resets = <&cru SRST_MIPIDPHYTX>; 932 reset-names = "apb"; 933 status = "disabled"; 934 }; 935 936 hevc_mmu: iommu@ff9a0440 { 937 compatible = "rockchip,iommu"; 938 reg = <0x0 0xff9a0440 0x0 0x40>, 939 <0x0 0xff9a0480 0x0 0x40>; 940 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 942 clock-names = "aclk", "iface"; 943 #iommu-cells = <0>; 944 status = "disabled"; 945 }; 946 947 vpu_mmu: iommu@ff9a0800 { 948 compatible = "rockchip,iommu"; 949 reg = <0x0 0xff9a0800 0x0 0x100>; 950 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 953 clock-names = "aclk", "iface"; 954 #iommu-cells = <0>; 955 status = "disabled"; 956 }; 957 958 qos_iep: qos@ffad0000 { 959 compatible = "rockchip,rk3368-qos", "syscon"; 960 reg = <0x0 0xffad0000 0x0 0x20>; 961 }; 962 963 qos_isp_r0: qos@ffad0080 { 964 compatible = "rockchip,rk3368-qos", "syscon"; 965 reg = <0x0 0xffad0080 0x0 0x20>; 966 }; 967 968 qos_isp_r1: qos@ffad0100 { 969 compatible = "rockchip,rk3368-qos", "syscon"; 970 reg = <0x0 0xffad0100 0x0 0x20>; 971 }; 972 973 qos_isp_w0: qos@ffad0180 { 974 compatible = "rockchip,rk3368-qos", "syscon"; 975 reg = <0x0 0xffad0180 0x0 0x20>; 976 }; 977 978 qos_isp_w1: qos@ffad0200 { 979 compatible = "rockchip,rk3368-qos", "syscon"; 980 reg = <0x0 0xffad0200 0x0 0x20>; 981 }; 982 983 qos_vip: qos@ffad0280 { 984 compatible = "rockchip,rk3368-qos", "syscon"; 985 reg = <0x0 0xffad0280 0x0 0x20>; 986 }; 987 988 qos_vop: qos@ffad0300 { 989 compatible = "rockchip,rk3368-qos", "syscon"; 990 reg = <0x0 0xffad0300 0x0 0x20>; 991 }; 992 993 qos_rga_r: qos@ffad0380 { 994 compatible = "rockchip,rk3368-qos", "syscon"; 995 reg = <0x0 0xffad0380 0x0 0x20>; 996 }; 997 998 qos_rga_w: qos@ffad0400 { 999 compatible = "rockchip,rk3368-qos", "syscon"; 1000 reg = <0x0 0xffad0400 0x0 0x20>; 1001 }; 1002 1003 qos_hevc_r: qos@ffae0000 { 1004 compatible = "rockchip,rk3368-qos", "syscon"; 1005 reg = <0x0 0xffae0000 0x0 0x20>; 1006 }; 1007 1008 qos_vpu_r: qos@ffae0100 { 1009 compatible = "rockchip,rk3368-qos", "syscon"; 1010 reg = <0x0 0xffae0100 0x0 0x20>; 1011 }; 1012 1013 qos_vpu_w: qos@ffae0180 { 1014 compatible = "rockchip,rk3368-qos", "syscon"; 1015 reg = <0x0 0xffae0180 0x0 0x20>; 1016 }; 1017 1018 qos_gpu: qos@ffaf0000 { 1019 compatible = "rockchip,rk3368-qos", "syscon"; 1020 reg = <0x0 0xffaf0000 0x0 0x20>; 1021 }; 1022 1023 efuse256: efuse@ffb00000 { 1024 compatible = "rockchip,rk3368-efuse"; 1025 reg = <0x0 0xffb00000 0x0 0x20>; 1026 #address-cells = <1>; 1027 #size-cells = <1>; 1028 clocks = <&cru PCLK_EFUSE256>; 1029 clock-names = "pclk_efuse"; 1030 1031 cpu_leakage: cpu-leakage@17 { 1032 reg = <0x17 0x1>; 1033 }; 1034 temp_adjust: temp-adjust@1f { 1035 reg = <0x1f 0x1>; 1036 }; 1037 }; 1038 1039 gic: interrupt-controller@ffb71000 { 1040 compatible = "arm,gic-400"; 1041 interrupt-controller; 1042 #interrupt-cells = <3>; 1043 #address-cells = <0>; 1044 1045 reg = <0x0 0xffb71000 0x0 0x1000>, 1046 <0x0 0xffb72000 0x0 0x2000>, 1047 <0x0 0xffb74000 0x0 0x2000>, 1048 <0x0 0xffb76000 0x0 0x2000>; 1049 interrupts = <GIC_PPI 9 1050 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1051 }; 1052 1053 pinctrl: pinctrl { 1054 compatible = "rockchip,rk3368-pinctrl"; 1055 rockchip,grf = <&grf>; 1056 rockchip,pmu = <&pmugrf>; 1057 #address-cells = <0x2>; 1058 #size-cells = <0x2>; 1059 ranges; 1060 1061 gpio0: gpio@ff750000 { 1062 compatible = "rockchip,gpio-bank"; 1063 reg = <0x0 0xff750000 0x0 0x100>; 1064 clocks = <&cru PCLK_GPIO0>; 1065 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 1066 1067 gpio-controller; 1068 #gpio-cells = <0x2>; 1069 1070 interrupt-controller; 1071 #interrupt-cells = <0x2>; 1072 }; 1073 1074 gpio1: gpio@ff780000 { 1075 compatible = "rockchip,gpio-bank"; 1076 reg = <0x0 0xff780000 0x0 0x100>; 1077 clocks = <&cru PCLK_GPIO1>; 1078 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 1079 1080 gpio-controller; 1081 #gpio-cells = <0x2>; 1082 1083 interrupt-controller; 1084 #interrupt-cells = <0x2>; 1085 }; 1086 1087 gpio2: gpio@ff790000 { 1088 compatible = "rockchip,gpio-bank"; 1089 reg = <0x0 0xff790000 0x0 0x100>; 1090 clocks = <&cru PCLK_GPIO2>; 1091 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 1092 1093 gpio-controller; 1094 #gpio-cells = <0x2>; 1095 1096 interrupt-controller; 1097 #interrupt-cells = <0x2>; 1098 }; 1099 1100 gpio3: gpio@ff7a0000 { 1101 compatible = "rockchip,gpio-bank"; 1102 reg = <0x0 0xff7a0000 0x0 0x100>; 1103 clocks = <&cru PCLK_GPIO3>; 1104 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 1105 1106 gpio-controller; 1107 #gpio-cells = <0x2>; 1108 1109 interrupt-controller; 1110 #interrupt-cells = <0x2>; 1111 }; 1112 1113 pcfg_pull_up: pcfg-pull-up { 1114 bias-pull-up; 1115 }; 1116 1117 pcfg_pull_down: pcfg-pull-down { 1118 bias-pull-down; 1119 }; 1120 1121 pcfg_pull_none: pcfg-pull-none { 1122 bias-disable; 1123 }; 1124 1125 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1126 bias-disable; 1127 drive-strength = <12>; 1128 }; 1129 1130 emmc { 1131 emmc_clk: emmc-clk { 1132 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 1133 }; 1134 1135 emmc_cmd: emmc-cmd { 1136 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 1137 }; 1138 1139 emmc_pwr: emmc-pwr { 1140 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 1141 }; 1142 1143 emmc_bus1: emmc-bus1 { 1144 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; 1145 }; 1146 1147 emmc_bus4: emmc-bus4 { 1148 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1149 <1 RK_PC3 2 &pcfg_pull_up>, 1150 <1 RK_PC4 2 &pcfg_pull_up>, 1151 <1 RK_PC5 2 &pcfg_pull_up>; 1152 }; 1153 1154 emmc_bus8: emmc-bus8 { 1155 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1156 <1 RK_PC3 2 &pcfg_pull_up>, 1157 <1 RK_PC4 2 &pcfg_pull_up>, 1158 <1 RK_PC5 2 &pcfg_pull_up>, 1159 <1 RK_PC6 2 &pcfg_pull_up>, 1160 <1 RK_PC7 2 &pcfg_pull_up>, 1161 <1 RK_PD0 2 &pcfg_pull_up>, 1162 <1 RK_PD1 2 &pcfg_pull_up>; 1163 }; 1164 }; 1165 1166 gmac { 1167 rgmii_pins: rgmii-pins { 1168 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 1169 <3 RK_PD0 1 &pcfg_pull_none>, 1170 <3 RK_PC3 1 &pcfg_pull_none>, 1171 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 1172 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 1173 <3 RK_PB2 1 &pcfg_pull_none_12ma>, 1174 <3 RK_PB6 1 &pcfg_pull_none_12ma>, 1175 <3 RK_PD4 1 &pcfg_pull_none_12ma>, 1176 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 1177 <3 RK_PB7 1 &pcfg_pull_none>, 1178 <3 RK_PC0 1 &pcfg_pull_none>, 1179 <3 RK_PC1 1 &pcfg_pull_none>, 1180 <3 RK_PC2 1 &pcfg_pull_none>, 1181 <3 RK_PD1 1 &pcfg_pull_none>, 1182 <3 RK_PC4 1 &pcfg_pull_none>; 1183 }; 1184 1185 rmii_pins: rmii-pins { 1186 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 1187 <3 RK_PD0 1 &pcfg_pull_none>, 1188 <3 RK_PC3 1 &pcfg_pull_none>, 1189 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 1190 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 1191 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 1192 <3 RK_PB7 1 &pcfg_pull_none>, 1193 <3 RK_PC0 1 &pcfg_pull_none>, 1194 <3 RK_PC4 1 &pcfg_pull_none>, 1195 <3 RK_PC5 1 &pcfg_pull_none>; 1196 }; 1197 }; 1198 1199 i2c0 { 1200 i2c0_xfer: i2c0-xfer { 1201 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1202 <0 RK_PA7 1 &pcfg_pull_none>; 1203 }; 1204 }; 1205 1206 i2c1 { 1207 i2c1_xfer: i2c1-xfer { 1208 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, 1209 <2 RK_PC6 1 &pcfg_pull_none>; 1210 }; 1211 }; 1212 1213 i2c2 { 1214 i2c2_xfer: i2c2-xfer { 1215 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, 1216 <3 RK_PD7 2 &pcfg_pull_none>; 1217 }; 1218 }; 1219 1220 i2c3 { 1221 i2c3_xfer: i2c3-xfer { 1222 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 1223 <1 RK_PC1 1 &pcfg_pull_none>; 1224 }; 1225 }; 1226 1227 i2c4 { 1228 i2c4_xfer: i2c4-xfer { 1229 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 1230 <3 RK_PD1 2 &pcfg_pull_none>; 1231 }; 1232 }; 1233 1234 i2c5 { 1235 i2c5_xfer: i2c5-xfer { 1236 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, 1237 <3 RK_PD3 2 &pcfg_pull_none>; 1238 }; 1239 }; 1240 1241 i2s { 1242 i2s_8ch_bus: i2s-8ch-bus { 1243 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1244 <2 RK_PB5 1 &pcfg_pull_none>, 1245 <2 RK_PB6 1 &pcfg_pull_none>, 1246 <2 RK_PB7 1 &pcfg_pull_none>, 1247 <2 RK_PC0 1 &pcfg_pull_none>, 1248 <2 RK_PC1 1 &pcfg_pull_none>, 1249 <2 RK_PC2 1 &pcfg_pull_none>, 1250 <2 RK_PC3 1 &pcfg_pull_none>, 1251 <2 RK_PC4 1 &pcfg_pull_none>; 1252 }; 1253 }; 1254 1255 pwm0 { 1256 pwm0_pin: pwm0-pin { 1257 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; 1258 }; 1259 }; 1260 1261 pwm1 { 1262 pwm1_pin: pwm1-pin { 1263 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; 1264 }; 1265 }; 1266 1267 pwm3 { 1268 pwm3_pin: pwm3-pin { 1269 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; 1270 }; 1271 }; 1272 1273 sdio0 { 1274 sdio0_bus1: sdio0-bus1 { 1275 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; 1276 }; 1277 1278 sdio0_bus4: sdio0-bus4 { 1279 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, 1280 <2 RK_PD5 1 &pcfg_pull_up>, 1281 <2 RK_PD6 1 &pcfg_pull_up>, 1282 <2 RK_PD7 1 &pcfg_pull_up>; 1283 }; 1284 1285 sdio0_cmd: sdio0-cmd { 1286 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; 1287 }; 1288 1289 sdio0_clk: sdio0-clk { 1290 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 1291 }; 1292 1293 sdio0_cd: sdio0-cd { 1294 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; 1295 }; 1296 1297 sdio0_wp: sdio0-wp { 1298 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; 1299 }; 1300 1301 sdio0_pwr: sdio0-pwr { 1302 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; 1303 }; 1304 1305 sdio0_bkpwr: sdio0-bkpwr { 1306 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; 1307 }; 1308 1309 sdio0_int: sdio0-int { 1310 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; 1311 }; 1312 }; 1313 1314 sdmmc { 1315 sdmmc_clk: sdmmc-clk { 1316 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1317 }; 1318 1319 sdmmc_cmd: sdmmc-cmd { 1320 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1321 }; 1322 1323 sdmmc_cd: sdmmc-cd { 1324 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1325 }; 1326 1327 sdmmc_bus1: sdmmc-bus1 { 1328 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; 1329 }; 1330 1331 sdmmc_bus4: sdmmc-bus4 { 1332 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, 1333 <2 RK_PA6 1 &pcfg_pull_up>, 1334 <2 RK_PA7 1 &pcfg_pull_up>, 1335 <2 RK_PB0 1 &pcfg_pull_up>; 1336 }; 1337 }; 1338 1339 spdif { 1340 spdif_tx: spdif-tx { 1341 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1342 }; 1343 }; 1344 1345 spi0 { 1346 spi0_clk: spi0-clk { 1347 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; 1348 }; 1349 spi0_cs0: spi0-cs0 { 1350 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; 1351 }; 1352 spi0_cs1: spi0-cs1 { 1353 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; 1354 }; 1355 spi0_tx: spi0-tx { 1356 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; 1357 }; 1358 spi0_rx: spi0-rx { 1359 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; 1360 }; 1361 }; 1362 1363 spi1 { 1364 spi1_clk: spi1-clk { 1365 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 1366 }; 1367 spi1_cs0: spi1-cs0 { 1368 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; 1369 }; 1370 spi1_cs1: spi1-cs1 { 1371 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; 1372 }; 1373 spi1_rx: spi1-rx { 1374 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; 1375 }; 1376 spi1_tx: spi1-tx { 1377 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; 1378 }; 1379 }; 1380 1381 spi2 { 1382 spi2_clk: spi2-clk { 1383 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; 1384 }; 1385 spi2_cs0: spi2-cs0 { 1386 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1387 }; 1388 spi2_rx: spi2-rx { 1389 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; 1390 }; 1391 spi2_tx: spi2-tx { 1392 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1393 }; 1394 }; 1395 1396 tsadc { 1397 otp_pin: otp-pin { 1398 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1399 }; 1400 1401 otp_out: otp-out { 1402 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1403 }; 1404 }; 1405 1406 uart0 { 1407 uart0_xfer: uart0-xfer { 1408 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, 1409 <2 RK_PD1 1 &pcfg_pull_none>; 1410 }; 1411 1412 uart0_cts: uart0-cts { 1413 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 1414 }; 1415 1416 uart0_rts: uart0-rts { 1417 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 1418 }; 1419 }; 1420 1421 uart1 { 1422 uart1_xfer: uart1-xfer { 1423 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, 1424 <0 RK_PC5 3 &pcfg_pull_none>; 1425 }; 1426 1427 uart1_cts: uart1-cts { 1428 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; 1429 }; 1430 1431 uart1_rts: uart1-rts { 1432 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; 1433 }; 1434 }; 1435 1436 uart2 { 1437 uart2_xfer: uart2-xfer { 1438 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, 1439 <2 RK_PA5 2 &pcfg_pull_none>; 1440 }; 1441 /* no rts / cts for uart2 */ 1442 }; 1443 1444 uart3 { 1445 uart3_xfer: uart3-xfer { 1446 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, 1447 <3 RK_PD6 3 &pcfg_pull_none>; 1448 }; 1449 1450 uart3_cts: uart3-cts { 1451 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; 1452 }; 1453 1454 uart3_rts: uart3-rts { 1455 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; 1456 }; 1457 }; 1458 1459 uart4 { 1460 uart4_xfer: uart4-xfer { 1461 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, 1462 <0 RK_PD2 3 &pcfg_pull_none>; 1463 }; 1464 1465 uart4_cts: uart4-cts { 1466 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; 1467 }; 1468 1469 uart4_rts: uart4-rts { 1470 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; 1471 }; 1472 }; 1473 }; 1474};
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