rk3328.dtsi

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4 */
   5
   6#include <dt-bindings/clock/rk3328-cru.h>
   7#include <dt-bindings/gpio/gpio.h>
   8#include <dt-bindings/interrupt-controller/arm-gic.h>
   9#include <dt-bindings/interrupt-controller/irq.h>
  10#include <dt-bindings/pinctrl/rockchip.h>
  11#include <dt-bindings/power/rk3328-power.h>
  12#include <dt-bindings/soc/rockchip,boot-mode.h>
  13#include <dt-bindings/thermal/thermal.h>
  14
  15/ {
  16	compatible = "rockchip,rk3328";
  17
  18	interrupt-parent = <&gic>;
  19	#address-cells = <2>;
  20	#size-cells = <2>;
  21
  22	aliases {
  23		gpio0 = &gpio0;
  24		gpio1 = &gpio1;
  25		gpio2 = &gpio2;
  26		gpio3 = &gpio3;
  27		serial0 = &uart0;
  28		serial1 = &uart1;
  29		serial2 = &uart2;
  30		i2c0 = &i2c0;
  31		i2c1 = &i2c1;
  32		i2c2 = &i2c2;
  33		i2c3 = &i2c3;
  34	};
  35
  36	cpus {
  37		#address-cells = <2>;
  38		#size-cells = <0>;
  39
  40		cpu0: cpu@0 {
  41			device_type = "cpu";
  42			compatible = "arm,cortex-a53";
  43			reg = <0x0 0x0>;
  44			clocks = <&cru ARMCLK>;
  45			#cooling-cells = <2>;
  46			cpu-idle-states = <&CPU_SLEEP>;
  47			dynamic-power-coefficient = <120>;
  48			enable-method = "psci";
  49			operating-points-v2 = <&cpu0_opp_table>;
  50			i-cache-size = <0x8000>;
  51			i-cache-line-size = <64>;
  52			i-cache-sets = <256>;
  53			d-cache-size = <0x8000>;
  54			d-cache-line-size = <64>;
  55			d-cache-sets = <128>;
  56			next-level-cache = <&l2_cache>;
  57		};
  58
  59		cpu1: cpu@1 {
  60			device_type = "cpu";
  61			compatible = "arm,cortex-a53";
  62			reg = <0x0 0x1>;
  63			clocks = <&cru ARMCLK>;
  64			#cooling-cells = <2>;
  65			cpu-idle-states = <&CPU_SLEEP>;
  66			dynamic-power-coefficient = <120>;
  67			enable-method = "psci";
  68			operating-points-v2 = <&cpu0_opp_table>;
  69			i-cache-size = <0x8000>;
  70			i-cache-line-size = <64>;
  71			i-cache-sets = <256>;
  72			d-cache-size = <0x8000>;
  73			d-cache-line-size = <64>;
  74			d-cache-sets = <128>;
  75			next-level-cache = <&l2_cache>;
  76		};
  77
  78		cpu2: cpu@2 {
  79			device_type = "cpu";
  80			compatible = "arm,cortex-a53";
  81			reg = <0x0 0x2>;
  82			clocks = <&cru ARMCLK>;
  83			#cooling-cells = <2>;
  84			cpu-idle-states = <&CPU_SLEEP>;
  85			dynamic-power-coefficient = <120>;
  86			enable-method = "psci";
  87			operating-points-v2 = <&cpu0_opp_table>;
  88			i-cache-size = <0x8000>;
  89			i-cache-line-size = <64>;
  90			i-cache-sets = <256>;
  91			d-cache-size = <0x8000>;
  92			d-cache-line-size = <64>;
  93			d-cache-sets = <128>;
  94			next-level-cache = <&l2_cache>;
  95		};
  96
  97		cpu3: cpu@3 {
  98			device_type = "cpu";
  99			compatible = "arm,cortex-a53";
 100			reg = <0x0 0x3>;
 101			clocks = <&cru ARMCLK>;
 102			#cooling-cells = <2>;
 103			cpu-idle-states = <&CPU_SLEEP>;
 104			dynamic-power-coefficient = <120>;
 105			enable-method = "psci";
 106			operating-points-v2 = <&cpu0_opp_table>;
 107			i-cache-size = <0x8000>;
 108			i-cache-line-size = <64>;
 109			i-cache-sets = <256>;
 110			d-cache-size = <0x8000>;
 111			d-cache-line-size = <64>;
 112			d-cache-sets = <128>;
 113			next-level-cache = <&l2_cache>;
 114		};
 115
 116		idle-states {
 117			entry-method = "psci";
 118
 119			CPU_SLEEP: cpu-sleep {
 120				compatible = "arm,idle-state";
 121				local-timer-stop;
 122				arm,psci-suspend-param = <0x0010000>;
 123				entry-latency-us = <120>;
 124				exit-latency-us = <250>;
 125				min-residency-us = <900>;
 126			};
 127		};
 128
 129		l2_cache: l2-cache {
 130			compatible = "cache";
 131			cache-level = <2>;
 132			cache-unified;
 133			cache-size = <0x40000>;
 134			cache-line-size = <64>;
 135			cache-sets = <256>;
 136		};
 137	};
 138
 139	cpu0_opp_table: opp-table-0 {
 140		compatible = "operating-points-v2";
 141		opp-shared;
 142
 143		opp-408000000 {
 144			opp-hz = /bits/ 64 <408000000>;
 145			opp-microvolt = <950000>;
 146			clock-latency-ns = <40000>;
 147			opp-suspend;
 148		};
 149		opp-600000000 {
 150			opp-hz = /bits/ 64 <600000000>;
 151			opp-microvolt = <950000>;
 152			clock-latency-ns = <40000>;
 153		};
 154		opp-816000000 {
 155			opp-hz = /bits/ 64 <816000000>;
 156			opp-microvolt = <1000000>;
 157			clock-latency-ns = <40000>;
 158		};
 159		opp-1008000000 {
 160			opp-hz = /bits/ 64 <1008000000>;
 161			opp-microvolt = <1100000>;
 162			clock-latency-ns = <40000>;
 163		};
 164		opp-1200000000 {
 165			opp-hz = /bits/ 64 <1200000000>;
 166			opp-microvolt = <1225000>;
 167			clock-latency-ns = <40000>;
 168		};
 169		opp-1296000000 {
 170			opp-hz = /bits/ 64 <1296000000>;
 171			opp-microvolt = <1300000>;
 172			clock-latency-ns = <40000>;
 173		};
 174	};
 175
 176	analog_sound: analog-sound {
 177		compatible = "simple-audio-card";
 178		simple-audio-card,format = "i2s";
 179		simple-audio-card,mclk-fs = <256>;
 180		simple-audio-card,name = "Analog";
 181		status = "disabled";
 182
 183		simple-audio-card,cpu {
 184			sound-dai = <&i2s1>;
 185		};
 186
 187		simple-audio-card,codec {
 188			sound-dai = <&codec>;
 189		};
 190	};
 191
 192	arm-pmu {
 193		compatible = "arm,cortex-a53-pmu";
 194		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 195			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 196			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 197			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 198		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 199	};
 200
 201	display_subsystem: display-subsystem {
 202		compatible = "rockchip,display-subsystem";
 203		ports = <&vop_out>;
 204	};
 205
 206	hdmi_sound: hdmi-sound {
 207		compatible = "simple-audio-card";
 208		simple-audio-card,format = "i2s";
 209		simple-audio-card,mclk-fs = <128>;
 210		simple-audio-card,name = "HDMI";
 211		status = "disabled";
 212
 213		simple-audio-card,cpu {
 214			sound-dai = <&i2s0>;
 215		};
 216
 217		simple-audio-card,codec {
 218			sound-dai = <&hdmi>;
 219		};
 220	};
 221
 222	psci {
 223		compatible = "arm,psci-1.0", "arm,psci-0.2";
 224		method = "smc";
 225	};
 226
 227	timer {
 228		compatible = "arm,armv8-timer";
 229		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 230			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 231			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 232			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 233	};
 234
 235	xin24m: xin24m {
 236		compatible = "fixed-clock";
 237		#clock-cells = <0>;
 238		clock-frequency = <24000000>;
 239		clock-output-names = "xin24m";
 240	};
 241
 242	i2s0: i2s@ff000000 {
 243		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 244		reg = <0x0 0xff000000 0x0 0x1000>;
 245		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 246		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 247		clock-names = "i2s_clk", "i2s_hclk";
 248		dmas = <&dmac 11>, <&dmac 12>;
 249		dma-names = "tx", "rx";
 250		#sound-dai-cells = <0>;
 251		status = "disabled";
 252	};
 253
 254	i2s1: i2s@ff010000 {
 255		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 256		reg = <0x0 0xff010000 0x0 0x1000>;
 257		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 258		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 259		clock-names = "i2s_clk", "i2s_hclk";
 260		dmas = <&dmac 14>, <&dmac 15>;
 261		dma-names = "tx", "rx";
 262		#sound-dai-cells = <0>;
 263		status = "disabled";
 264	};
 265
 266	i2s2: i2s@ff020000 {
 267		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 268		reg = <0x0 0xff020000 0x0 0x1000>;
 269		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 270		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 271		clock-names = "i2s_clk", "i2s_hclk";
 272		dmas = <&dmac 0>, <&dmac 1>;
 273		dma-names = "tx", "rx";
 274		#sound-dai-cells = <0>;
 275		status = "disabled";
 276	};
 277
 278	spdif: spdif@ff030000 {
 279		compatible = "rockchip,rk3328-spdif";
 280		reg = <0x0 0xff030000 0x0 0x1000>;
 281		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 282		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 283		clock-names = "mclk", "hclk";
 284		dmas = <&dmac 10>;
 285		dma-names = "tx";
 286		pinctrl-names = "default";
 287		pinctrl-0 = <&spdifm2_tx>;
 288		#sound-dai-cells = <0>;
 289		status = "disabled";
 290	};
 291
 292	pdm: pdm@ff040000 {
 293		compatible = "rockchip,pdm";
 294		reg = <0x0 0xff040000 0x0 0x1000>;
 295		clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 296		clock-names = "pdm_clk", "pdm_hclk";
 297		dmas = <&dmac 16>;
 298		dma-names = "rx";
 299		pinctrl-names = "default", "sleep";
 300		pinctrl-0 = <&pdmm0_clk
 301			     &pdmm0_sdi0
 302			     &pdmm0_sdi1
 303			     &pdmm0_sdi2
 304			     &pdmm0_sdi3>;
 305		pinctrl-1 = <&pdmm0_clk_sleep
 306			     &pdmm0_sdi0_sleep
 307			     &pdmm0_sdi1_sleep
 308			     &pdmm0_sdi2_sleep
 309			     &pdmm0_sdi3_sleep>;
 310		status = "disabled";
 311	};
 312
 313	grf: syscon@ff100000 {
 314		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 315		reg = <0x0 0xff100000 0x0 0x1000>;
 316
 317		io_domains: io-domains {
 318			compatible = "rockchip,rk3328-io-voltage-domain";
 319			status = "disabled";
 320		};
 321
 322		grf_gpio: gpio {
 323			compatible = "rockchip,rk3328-grf-gpio";
 324			gpio-controller;
 325			#gpio-cells = <2>;
 326		};
 327
 328		power: power-controller {
 329			compatible = "rockchip,rk3328-power-controller";
 330			#power-domain-cells = <1>;
 331			#address-cells = <1>;
 332			#size-cells = <0>;
 333
 334			power-domain@RK3328_PD_GPU {
 335				reg = <RK3328_PD_GPU>;
 336				clocks = <&cru ACLK_GPU>;
 337				#power-domain-cells = <0>;
 338			};
 339			power-domain@RK3328_PD_HEVC {
 340				reg = <RK3328_PD_HEVC>;
 341				clocks = <&cru SCLK_VENC_CORE>;
 342				#power-domain-cells = <0>;
 343			};
 344			power-domain@RK3328_PD_VIDEO {
 345				reg = <RK3328_PD_VIDEO>;
 346				clocks = <&cru ACLK_RKVDEC>,
 347					 <&cru HCLK_RKVDEC>,
 348					 <&cru SCLK_VDEC_CABAC>,
 349					 <&cru SCLK_VDEC_CORE>;
 350				#power-domain-cells = <0>;
 351			};
 352			power-domain@RK3328_PD_VPU {
 353				reg = <RK3328_PD_VPU>;
 354				clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 355				#power-domain-cells = <0>;
 356			};
 357		};
 358
 359		reboot-mode {
 360			compatible = "syscon-reboot-mode";
 361			offset = <0x5c8>;
 362			mode-normal = <BOOT_NORMAL>;
 363			mode-recovery = <BOOT_RECOVERY>;
 364			mode-bootloader = <BOOT_FASTBOOT>;
 365			mode-loader = <BOOT_BL_DOWNLOAD>;
 366		};
 367	};
 368
 369	uart0: serial@ff110000 {
 370		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 371		reg = <0x0 0xff110000 0x0 0x100>;
 372		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 373		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 374		clock-names = "baudclk", "apb_pclk";
 375		dmas = <&dmac 2>, <&dmac 3>;
 376		dma-names = "tx", "rx";
 377		pinctrl-names = "default";
 378		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 379		reg-io-width = <4>;
 380		reg-shift = <2>;
 381		status = "disabled";
 382	};
 383
 384	uart1: serial@ff120000 {
 385		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 386		reg = <0x0 0xff120000 0x0 0x100>;
 387		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 388		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 389		clock-names = "baudclk", "apb_pclk";
 390		dmas = <&dmac 4>, <&dmac 5>;
 391		dma-names = "tx", "rx";
 392		pinctrl-names = "default";
 393		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 394		reg-io-width = <4>;
 395		reg-shift = <2>;
 396		status = "disabled";
 397	};
 398
 399	uart2: serial@ff130000 {
 400		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 401		reg = <0x0 0xff130000 0x0 0x100>;
 402		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 403		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 404		clock-names = "baudclk", "apb_pclk";
 405		dmas = <&dmac 6>, <&dmac 7>;
 406		dma-names = "tx", "rx";
 407		pinctrl-names = "default";
 408		pinctrl-0 = <&uart2m1_xfer>;
 409		reg-io-width = <4>;
 410		reg-shift = <2>;
 411		status = "disabled";
 412	};
 413
 414	i2c0: i2c@ff150000 {
 415		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 416		reg = <0x0 0xff150000 0x0 0x1000>;
 417		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 418		#address-cells = <1>;
 419		#size-cells = <0>;
 420		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 421		clock-names = "i2c", "pclk";
 422		pinctrl-names = "default";
 423		pinctrl-0 = <&i2c0_xfer>;
 424		status = "disabled";
 425	};
 426
 427	i2c1: i2c@ff160000 {
 428		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 429		reg = <0x0 0xff160000 0x0 0x1000>;
 430		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 431		#address-cells = <1>;
 432		#size-cells = <0>;
 433		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 434		clock-names = "i2c", "pclk";
 435		pinctrl-names = "default";
 436		pinctrl-0 = <&i2c1_xfer>;
 437		status = "disabled";
 438	};
 439
 440	i2c2: i2c@ff170000 {
 441		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 442		reg = <0x0 0xff170000 0x0 0x1000>;
 443		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 444		#address-cells = <1>;
 445		#size-cells = <0>;
 446		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 447		clock-names = "i2c", "pclk";
 448		pinctrl-names = "default";
 449		pinctrl-0 = <&i2c2_xfer>;
 450		status = "disabled";
 451	};
 452
 453	i2c3: i2c@ff180000 {
 454		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 455		reg = <0x0 0xff180000 0x0 0x1000>;
 456		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 457		#address-cells = <1>;
 458		#size-cells = <0>;
 459		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 460		clock-names = "i2c", "pclk";
 461		pinctrl-names = "default";
 462		pinctrl-0 = <&i2c3_xfer>;
 463		status = "disabled";
 464	};
 465
 466	spi0: spi@ff190000 {
 467		compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 468		reg = <0x0 0xff190000 0x0 0x1000>;
 469		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 470		#address-cells = <1>;
 471		#size-cells = <0>;
 472		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 473		clock-names = "spiclk", "apb_pclk";
 474		dmas = <&dmac 8>, <&dmac 9>;
 475		dma-names = "tx", "rx";
 476		pinctrl-names = "default";
 477		pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 478		status = "disabled";
 479	};
 480
 481	wdt: watchdog@ff1a0000 {
 482		compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
 483		reg = <0x0 0xff1a0000 0x0 0x100>;
 484		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 485		clocks = <&cru PCLK_WDT>;
 486	};
 487
 488	pwm0: pwm@ff1b0000 {
 489		compatible = "rockchip,rk3328-pwm";
 490		reg = <0x0 0xff1b0000 0x0 0x10>;
 491		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 492		clock-names = "pwm", "pclk";
 493		pinctrl-names = "default";
 494		pinctrl-0 = <&pwm0_pin>;
 495		#pwm-cells = <3>;
 496		status = "disabled";
 497	};
 498
 499	pwm1: pwm@ff1b0010 {
 500		compatible = "rockchip,rk3328-pwm";
 501		reg = <0x0 0xff1b0010 0x0 0x10>;
 502		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 503		clock-names = "pwm", "pclk";
 504		pinctrl-names = "default";
 505		pinctrl-0 = <&pwm1_pin>;
 506		#pwm-cells = <3>;
 507		status = "disabled";
 508	};
 509
 510	pwm2: pwm@ff1b0020 {
 511		compatible = "rockchip,rk3328-pwm";
 512		reg = <0x0 0xff1b0020 0x0 0x10>;
 513		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 514		clock-names = "pwm", "pclk";
 515		pinctrl-names = "default";
 516		pinctrl-0 = <&pwm2_pin>;
 517		#pwm-cells = <3>;
 518		status = "disabled";
 519	};
 520
 521	pwm3: pwm@ff1b0030 {
 522		compatible = "rockchip,rk3328-pwm";
 523		reg = <0x0 0xff1b0030 0x0 0x10>;
 524		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 525		clock-names = "pwm", "pclk";
 526		pinctrl-names = "default";
 527		pinctrl-0 = <&pwmir_pin>;
 528		#pwm-cells = <3>;
 529		status = "disabled";
 530	};
 531
 532	dmac: dma-controller@ff1f0000 {
 533		compatible = "arm,pl330", "arm,primecell";
 534		reg = <0x0 0xff1f0000 0x0 0x4000>;
 535		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 536			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 537		arm,pl330-periph-burst;
 538		clocks = <&cru ACLK_DMAC>;
 539		clock-names = "apb_pclk";
 540		#dma-cells = <1>;
 541	};
 542
 543	thermal-zones {
 544		soc_thermal: soc-thermal {
 545			polling-delay-passive = <20>;
 546			polling-delay = <1000>;
 547			sustainable-power = <1000>;
 548
 549			thermal-sensors = <&tsadc 0>;
 550
 551			trips {
 552				threshold: trip-point0 {
 553					temperature = <70000>;
 554					hysteresis = <2000>;
 555					type = "passive";
 556				};
 557				target: trip-point1 {
 558					temperature = <85000>;
 559					hysteresis = <2000>;
 560					type = "passive";
 561				};
 562				soc_crit: soc-crit {
 563					temperature = <95000>;
 564					hysteresis = <2000>;
 565					type = "critical";
 566				};
 567			};
 568
 569			cooling-maps {
 570				map0 {
 571					trip = <&target>;
 572					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 573							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 574							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 575							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 576					contribution = <4096>;
 577				};
 578				map1 {
 579					trip = <&target>;
 580					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 581					contribution = <4096>;
 582				};
 583			};
 584		};
 585	};
 586
 587	tsadc: tsadc@ff250000 {
 588		compatible = "rockchip,rk3328-tsadc";
 589		reg = <0x0 0xff250000 0x0 0x100>;
 590		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 591		assigned-clocks = <&cru SCLK_TSADC>;
 592		assigned-clock-rates = <50000>;
 593		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 594		clock-names = "tsadc", "apb_pclk";
 595		pinctrl-names = "init", "default", "sleep";
 596		pinctrl-0 = <&otp_pin>;
 597		pinctrl-1 = <&otp_out>;
 598		pinctrl-2 = <&otp_pin>;
 599		resets = <&cru SRST_TSADC>;
 600		reset-names = "tsadc-apb";
 601		rockchip,hw-tshut-temp = <100000>;
 602		#thermal-sensor-cells = <1>;
 603		status = "disabled";
 604	};
 605
 606	efuse: efuse@ff260000 {
 607		compatible = "rockchip,rk3328-efuse";
 608		reg = <0x0 0xff260000 0x0 0x50>;
 609		#address-cells = <1>;
 610		#size-cells = <1>;
 611		clocks = <&cru SCLK_EFUSE>;
 612		clock-names = "pclk_efuse";
 613		rockchip,efuse-size = <0x20>;
 614
 615		/* Data cells */
 616		efuse_id: id@7 {
 617			reg = <0x07 0x10>;
 618		};
 619		cpu_leakage: cpu-leakage@17 {
 620			reg = <0x17 0x1>;
 621		};
 622		logic_leakage: logic-leakage@19 {
 623			reg = <0x19 0x1>;
 624		};
 625		efuse_cpu_version: cpu-version@1a {
 626			reg = <0x1a 0x1>;
 627			bits = <3 3>;
 628		};
 629	};
 630
 631	saradc: adc@ff280000 {
 632		compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 633		reg = <0x0 0xff280000 0x0 0x100>;
 634		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 635		#io-channel-cells = <1>;
 636		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 637		clock-names = "saradc", "apb_pclk";
 638		resets = <&cru SRST_SARADC_P>;
 639		reset-names = "saradc-apb";
 640		status = "disabled";
 641	};
 642
 643	gpu: gpu@ff300000 {
 644		compatible = "rockchip,rk3328-mali", "arm,mali-450";
 645		reg = <0x0 0xff300000 0x0 0x30000>;
 646		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 647			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 648			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 649			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 650			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 651			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 652			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 653		interrupt-names = "gp",
 654				  "gpmmu",
 655				  "pp",
 656				  "pp0",
 657				  "ppmmu0",
 658				  "pp1",
 659				  "ppmmu1";
 660		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 661		clock-names = "bus", "core";
 662		operating-points-v2 = <&gpu_opp_table>;
 663		power-domains = <&power RK3328_PD_GPU>;
 664		resets = <&cru SRST_GPU_A>;
 665		#cooling-cells = <2>;
 666	};
 667
 668	gpu_opp_table: opp-table-gpu {
 669		compatible = "operating-points-v2";
 670
 671		opp-200000000 {
 672			opp-hz = /bits/ 64 <200000000>;
 673			opp-microvolt = <1075000>;
 674		};
 675
 676		opp-300000000 {
 677			opp-hz = /bits/ 64 <300000000>;
 678			opp-microvolt = <1075000>;
 679		};
 680
 681		opp-400000000 {
 682			opp-hz = /bits/ 64 <400000000>;
 683			opp-microvolt = <1075000>;
 684		};
 685
 686		opp-500000000 {
 687			/* causes stability issues */
 688			opp-hz = /bits/ 64 <500000000>;
 689			opp-microvolt = <1150000>;
 690			status = "disabled";
 691		};
 692	};
 693
 694	h265e_mmu: iommu@ff330200 {
 695		compatible = "rockchip,iommu";
 696		reg = <0x0 0xff330200 0 0x100>;
 697		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 698		clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 699		clock-names = "aclk", "iface";
 700		#iommu-cells = <0>;
 701		status = "disabled";
 702	};
 703
 704	vepu_mmu: iommu@ff340800 {
 705		compatible = "rockchip,iommu";
 706		reg = <0x0 0xff340800 0x0 0x40>;
 707		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 708		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 709		clock-names = "aclk", "iface";
 710		#iommu-cells = <0>;
 711		status = "disabled";
 712	};
 713
 714	vpu: video-codec@ff350000 {
 715		compatible = "rockchip,rk3328-vpu";
 716		reg = <0x0 0xff350000 0x0 0x800>;
 717		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 718		interrupt-names = "vdpu";
 719		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 720		clock-names = "aclk", "hclk";
 721		iommus = <&vpu_mmu>;
 722		power-domains = <&power RK3328_PD_VPU>;
 723	};
 724
 725	vpu_mmu: iommu@ff350800 {
 726		compatible = "rockchip,iommu";
 727		reg = <0x0 0xff350800 0x0 0x40>;
 728		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 729		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 730		clock-names = "aclk", "iface";
 731		#iommu-cells = <0>;
 732		power-domains = <&power RK3328_PD_VPU>;
 733	};
 734
 735	vdec: video-codec@ff360000 {
 736		compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
 737		reg = <0x0 0xff360000 0x0 0x480>;
 738		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 739		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
 740			 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
 741		clock-names = "axi", "ahb", "cabac", "core";
 742		assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
 743				  <&cru SCLK_VDEC_CORE>;
 744		assigned-clock-rates = <400000000>, <400000000>, <300000000>;
 745		iommus = <&vdec_mmu>;
 746		power-domains = <&power RK3328_PD_VIDEO>;
 747	};
 748
 749	vdec_mmu: iommu@ff360480 {
 750		compatible = "rockchip,iommu";
 751		reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 752		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 753		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 754		clock-names = "aclk", "iface";
 755		#iommu-cells = <0>;
 756		power-domains = <&power RK3328_PD_VIDEO>;
 757	};
 758
 759	vop: vop@ff370000 {
 760		compatible = "rockchip,rk3328-vop";
 761		reg = <0x0 0xff370000 0x0 0x3efc>;
 762		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 763		clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 764		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 765		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 766		reset-names = "axi", "ahb", "dclk";
 767		iommus = <&vop_mmu>;
 768		status = "disabled";
 769
 770		vop_out: port {
 771			vop_out_hdmi: endpoint {
 772				remote-endpoint = <&hdmi_in_vop>;
 773			};
 774		};
 775	};
 776
 777	vop_mmu: iommu@ff373f00 {
 778		compatible = "rockchip,iommu";
 779		reg = <0x0 0xff373f00 0x0 0x100>;
 780		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 781		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 782		clock-names = "aclk", "iface";
 783		#iommu-cells = <0>;
 784		status = "disabled";
 785	};
 786
 787	hdmi: hdmi@ff3c0000 {
 788		compatible = "rockchip,rk3328-dw-hdmi";
 789		reg = <0x0 0xff3c0000 0x0 0x20000>;
 790		reg-io-width = <4>;
 791		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 792		clocks = <&cru PCLK_HDMI>,
 793			 <&cru SCLK_HDMI_SFC>,
 794			 <&cru SCLK_RTC32K>;
 795		clock-names = "iahb",
 796			      "isfr",
 797			      "cec";
 798		phys = <&hdmiphy>;
 799		phy-names = "hdmi";
 800		pinctrl-names = "default";
 801		pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 802		rockchip,grf = <&grf>;
 803		#sound-dai-cells = <0>;
 804		status = "disabled";
 805
 806		ports {
 807			#address-cells = <1>;
 808			#size-cells = <0>;
 809
 810			hdmi_in: port@0 {
 811				reg = <0>;
 812
 813				hdmi_in_vop: endpoint {
 814					remote-endpoint = <&vop_out_hdmi>;
 815				};
 816			};
 817
 818			hdmi_out: port@1 {
 819				reg = <1>;
 820			};
 821		};
 822	};
 823
 824	codec: codec@ff410000 {
 825		compatible = "rockchip,rk3328-codec";
 826		reg = <0x0 0xff410000 0x0 0x1000>;
 827		clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
 828		clock-names = "pclk", "mclk";
 829		rockchip,grf = <&grf>;
 830		#sound-dai-cells = <0>;
 831		status = "disabled";
 832	};
 833
 834	hdmiphy: phy@ff430000 {
 835		compatible = "rockchip,rk3328-hdmi-phy";
 836		reg = <0x0 0xff430000 0x0 0x10000>;
 837		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 838		clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 839		clock-names = "sysclk", "refoclk", "refpclk";
 840		clock-output-names = "hdmi_phy";
 841		#clock-cells = <0>;
 842		nvmem-cells = <&efuse_cpu_version>;
 843		nvmem-cell-names = "cpu-version";
 844		#phy-cells = <0>;
 845		status = "disabled";
 846	};
 847
 848	cru: clock-controller@ff440000 {
 849		compatible = "rockchip,rk3328-cru";
 850		reg = <0x0 0xff440000 0x0 0x1000>;
 851		clocks = <&xin24m>;
 852		clock-names = "xin24m";
 853		rockchip,grf = <&grf>;
 854		#clock-cells = <1>;
 855		#reset-cells = <1>;
 856		assigned-clocks =
 857			/*
 858			 * CPLL should run at 1200, but that is to high for
 859			 * the initial dividers of most of its children.
 860			 * We need set cpll child clk div first,
 861			 * and then set the cpll frequency.
 862			 */
 863			<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 864			<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 865			<&cru SCLK_UART1>, <&cru SCLK_UART2>,
 866			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 867			<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 868			<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 869			<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 870			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 871			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 872			<&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 873			<&cru SCLK_WIFI>, <&cru ARMCLK>,
 874			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
 875			<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 876			<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 877			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
 878			<&cru SCLK_RTC32K>;
 879		assigned-clock-parents =
 880			<&cru HDMIPHY>, <&cru PLL_APLL>,
 881			<&cru PLL_GPLL>, <&xin24m>,
 882			<&xin24m>, <&xin24m>;
 883		assigned-clock-rates =
 884			<0>, <61440000>,
 885			<0>, <24000000>,
 886			<24000000>, <24000000>,
 887			<15000000>, <15000000>,
 888			<300000000>, <100000000>,
 889			<400000000>, <100000000>,
 890			<50000000>, <100000000>,
 891			<100000000>, <100000000>,
 892			<50000000>, <50000000>,
 893			<50000000>, <50000000>,
 894			<24000000>, <600000000>,
 895			<491520000>, <1200000000>,
 896			<150000000>, <75000000>,
 897			<75000000>, <150000000>,
 898			<75000000>, <75000000>,
 899			<32768>;
 900	};
 901
 902	usb2phy_grf: syscon@ff450000 {
 903		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 904			     "simple-mfd";
 905		reg = <0x0 0xff450000 0x0 0x10000>;
 906		#address-cells = <1>;
 907		#size-cells = <1>;
 908
 909		u2phy: usb2phy@100 {
 910			compatible = "rockchip,rk3328-usb2phy";
 911			reg = <0x100 0x10>;
 912			clocks = <&xin24m>;
 913			clock-names = "phyclk";
 914			clock-output-names = "usb480m_phy";
 915			#clock-cells = <0>;
 916			assigned-clocks = <&cru USB480M>;
 917			assigned-clock-parents = <&u2phy>;
 918			status = "disabled";
 919
 920			u2phy_otg: otg-port {
 921				#phy-cells = <0>;
 922				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 923					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 924					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 925				interrupt-names = "otg-bvalid", "otg-id",
 926						  "linestate";
 927				status = "disabled";
 928			};
 929
 930			u2phy_host: host-port {
 931				#phy-cells = <0>;
 932				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 933				interrupt-names = "linestate";
 934				status = "disabled";
 935			};
 936		};
 937	};
 938
 939	sdmmc: mmc@ff500000 {
 940		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 941		reg = <0x0 0xff500000 0x0 0x4000>;
 942		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 943		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 944			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 945		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 946		fifo-depth = <0x100>;
 947		max-frequency = <150000000>;
 948		resets = <&cru SRST_MMC0>;
 949		reset-names = "reset";
 950		status = "disabled";
 951	};
 952
 953	sdio: mmc@ff510000 {
 954		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 955		reg = <0x0 0xff510000 0x0 0x4000>;
 956		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 957		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 958			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 959		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 960		fifo-depth = <0x100>;
 961		max-frequency = <150000000>;
 962		resets = <&cru SRST_SDIO>;
 963		reset-names = "reset";
 964		status = "disabled";
 965	};
 966
 967	emmc: mmc@ff520000 {
 968		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 969		reg = <0x0 0xff520000 0x0 0x4000>;
 970		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 971		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 972			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 973		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 974		fifo-depth = <0x100>;
 975		max-frequency = <150000000>;
 976		resets = <&cru SRST_EMMC>;
 977		reset-names = "reset";
 978		status = "disabled";
 979	};
 980
 981	gmac2io: ethernet@ff540000 {
 982		compatible = "rockchip,rk3328-gmac";
 983		reg = <0x0 0xff540000 0x0 0x10000>;
 984		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 985		interrupt-names = "macirq";
 986		clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 987			 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 988			 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 989			 <&cru PCLK_MAC2IO>;
 990		clock-names = "stmmaceth", "mac_clk_rx",
 991			      "mac_clk_tx", "clk_mac_ref",
 992			      "clk_mac_refout", "aclk_mac",
 993			      "pclk_mac";
 994		resets = <&cru SRST_GMAC2IO_A>;
 995		reset-names = "stmmaceth";
 996		rockchip,grf = <&grf>;
 997		tx-fifo-depth = <2048>;
 998		rx-fifo-depth = <4096>;
 999		snps,txpbl = <0x4>;
1000		status = "disabled";
1001	};
1002
1003	gmac2phy: ethernet@ff550000 {
1004		compatible = "rockchip,rk3328-gmac";
1005		reg = <0x0 0xff550000 0x0 0x10000>;
1006		rockchip,grf = <&grf>;
1007		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1008		interrupt-names = "macirq";
1009		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
1010			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
1011			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
1012			 <&cru SCLK_MAC2PHY_OUT>;
1013		clock-names = "stmmaceth", "mac_clk_rx",
1014			      "mac_clk_tx", "clk_mac_ref",
1015			      "aclk_mac", "pclk_mac",
1016			      "clk_macphy";
1017		resets = <&cru SRST_GMAC2PHY_A>;
1018		reset-names = "stmmaceth";
1019		phy-mode = "rmii";
1020		phy-handle = <&phy>;
1021		tx-fifo-depth = <2048>;
1022		rx-fifo-depth = <4096>;
1023		snps,txpbl = <0x4>;
1024		clock_in_out = "output";
1025		status = "disabled";
1026
1027		mdio {
1028			compatible = "snps,dwmac-mdio";
1029			#address-cells = <1>;
1030			#size-cells = <0>;
1031
1032			phy: ethernet-phy@0 {
1033				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1034				reg = <0>;
1035				clocks = <&cru SCLK_MAC2PHY_OUT>;
1036				resets = <&cru SRST_MACPHY>;
1037				pinctrl-names = "default";
1038				pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
1039				phy-is-integrated;
1040			};
1041		};
1042	};
1043
1044	usb20_otg: usb@ff580000 {
1045		compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
1046			     "snps,dwc2";
1047		reg = <0x0 0xff580000 0x0 0x40000>;
1048		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1049		clocks = <&cru HCLK_OTG>;
1050		clock-names = "otg";
1051		dr_mode = "otg";
1052		g-np-tx-fifo-size = <16>;
1053		g-rx-fifo-size = <280>;
1054		g-tx-fifo-size = <256 128 128 64 32 16>;
1055		phys = <&u2phy_otg>;
1056		phy-names = "usb2-phy";
1057		status = "disabled";
1058	};
1059
1060	usb_host0_ehci: usb@ff5c0000 {
1061		compatible = "generic-ehci";
1062		reg = <0x0 0xff5c0000 0x0 0x10000>;
1063		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1064		clocks = <&cru HCLK_HOST0>, <&u2phy>;
1065		phys = <&u2phy_host>;
1066		phy-names = "usb";
1067		status = "disabled";
1068	};
1069
1070	usb_host0_ohci: usb@ff5d0000 {
1071		compatible = "generic-ohci";
1072		reg = <0x0 0xff5d0000 0x0 0x10000>;
1073		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1074		clocks = <&cru HCLK_HOST0>, <&u2phy>;
1075		phys = <&u2phy_host>;
1076		phy-names = "usb";
1077		status = "disabled";
1078	};
1079
1080	sdmmc_ext: mmc@ff5f0000 {
1081		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1082		reg = <0x0 0xff5f0000 0x0 0x4000>;
1083		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1084		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
1085			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
1086		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1087		fifo-depth = <0x100>;
1088		max-frequency = <150000000>;
1089		resets = <&cru SRST_SDMMCEXT>;
1090		reset-names = "reset";
1091		status = "disabled";
1092	};
1093
1094	usbdrd3: usb@ff600000 {
1095		compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1096		reg = <0x0 0xff600000 0x0 0x100000>;
1097		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1098		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1099			 <&cru ACLK_USB3OTG>;
1100		clock-names = "ref_clk", "suspend_clk",
1101			      "bus_clk";
1102		dr_mode = "otg";
1103		phy_type = "utmi_wide";
1104		snps,dis-del-phy-power-chg-quirk;
1105		snps,dis_enblslpm_quirk;
1106		snps,dis-tx-ipgap-linecheck-quirk;
1107		snps,dis-u2-freeclk-exists-quirk;
1108		snps,dis_u2_susphy_quirk;
1109		snps,dis_u3_susphy_quirk;
1110		status = "disabled";
1111	};
1112
1113	gic: interrupt-controller@ff811000 {
1114		compatible = "arm,gic-400";
1115		#interrupt-cells = <3>;
1116		#address-cells = <0>;
1117		interrupt-controller;
1118		reg = <0x0 0xff811000 0 0x1000>,
1119		      <0x0 0xff812000 0 0x2000>,
1120		      <0x0 0xff814000 0 0x2000>,
1121		      <0x0 0xff816000 0 0x2000>;
1122		interrupts = <GIC_PPI 9
1123		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1124	};
1125
1126	crypto: crypto@ff060000 {
1127		compatible = "rockchip,rk3328-crypto";
1128		reg = <0x0 0xff060000 0x0 0x4000>;
1129		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1130		clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1131			 <&cru SCLK_CRYPTO>;
1132		clock-names = "hclk_master", "hclk_slave", "sclk";
1133		resets = <&cru SRST_CRYPTO>;
1134		reset-names = "crypto-rst";
1135	};
1136
1137	pinctrl: pinctrl {
1138		compatible = "rockchip,rk3328-pinctrl";
1139		rockchip,grf = <&grf>;
1140		#address-cells = <2>;
1141		#size-cells = <2>;
1142		ranges;
1143
1144		gpio0: gpio@ff210000 {
1145			compatible = "rockchip,gpio-bank";
1146			reg = <0x0 0xff210000 0x0 0x100>;
1147			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1148			clocks = <&cru PCLK_GPIO0>;
1149
1150			gpio-controller;
1151			#gpio-cells = <2>;
1152
1153			interrupt-controller;
1154			#interrupt-cells = <2>;
1155		};
1156
1157		gpio1: gpio@ff220000 {
1158			compatible = "rockchip,gpio-bank";
1159			reg = <0x0 0xff220000 0x0 0x100>;
1160			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1161			clocks = <&cru PCLK_GPIO1>;
1162
1163			gpio-controller;
1164			#gpio-cells = <2>;
1165
1166			interrupt-controller;
1167			#interrupt-cells = <2>;
1168		};
1169
1170		gpio2: gpio@ff230000 {
1171			compatible = "rockchip,gpio-bank";
1172			reg = <0x0 0xff230000 0x0 0x100>;
1173			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1174			clocks = <&cru PCLK_GPIO2>;
1175
1176			gpio-controller;
1177			#gpio-cells = <2>;
1178
1179			interrupt-controller;
1180			#interrupt-cells = <2>;
1181		};
1182
1183		gpio3: gpio@ff240000 {
1184			compatible = "rockchip,gpio-bank";
1185			reg = <0x0 0xff240000 0x0 0x100>;
1186			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1187			clocks = <&cru PCLK_GPIO3>;
1188
1189			gpio-controller;
1190			#gpio-cells = <2>;
1191
1192			interrupt-controller;
1193			#interrupt-cells = <2>;
1194		};
1195
1196		pcfg_pull_up: pcfg-pull-up {
1197			bias-pull-up;
1198		};
1199
1200		pcfg_pull_down: pcfg-pull-down {
1201			bias-pull-down;
1202		};
1203
1204		pcfg_pull_none: pcfg-pull-none {
1205			bias-disable;
1206		};
1207
1208		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1209			bias-disable;
1210			drive-strength = <2>;
1211		};
1212
1213		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1214			bias-pull-up;
1215			drive-strength = <2>;
1216		};
1217
1218		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1219			bias-pull-up;
1220			drive-strength = <4>;
1221		};
1222
1223		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1224			bias-disable;
1225			drive-strength = <4>;
1226		};
1227
1228		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1229			bias-pull-down;
1230			drive-strength = <4>;
1231		};
1232
1233		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1234			bias-disable;
1235			drive-strength = <8>;
1236		};
1237
1238		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1239			bias-pull-up;
1240			drive-strength = <8>;
1241		};
1242
1243		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1244			bias-disable;
1245			drive-strength = <12>;
1246		};
1247
1248		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1249			bias-pull-up;
1250			drive-strength = <12>;
1251		};
1252
1253		pcfg_output_high: pcfg-output-high {
1254			output-high;
1255		};
1256
1257		pcfg_output_low: pcfg-output-low {
1258			output-low;
1259		};
1260
1261		pcfg_input_high: pcfg-input-high {
1262			bias-pull-up;
1263			input-enable;
1264		};
1265
1266		pcfg_input: pcfg-input {
1267			input-enable;
1268		};
1269
1270		i2c0 {
1271			i2c0_xfer: i2c0-xfer {
1272				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1273						<2 RK_PD1 1 &pcfg_pull_none>;
1274			};
1275		};
1276
1277		i2c1 {
1278			i2c1_xfer: i2c1-xfer {
1279				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1280						<2 RK_PA5 2 &pcfg_pull_none>;
1281			};
1282		};
1283
1284		i2c2 {
1285			i2c2_xfer: i2c2-xfer {
1286				rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1287						<2 RK_PB6 1 &pcfg_pull_none>;
1288			};
1289		};
1290
1291		i2c3 {
1292			i2c3_xfer: i2c3-xfer {
1293				rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1294						<0 RK_PA6 2 &pcfg_pull_none>;
1295			};
1296			i2c3_pins: i2c3-pins {
1297				rockchip,pins =
1298					<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1299					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1300			};
1301		};
1302
1303		hdmi_i2c {
1304			hdmii2c_xfer: hdmii2c-xfer {
1305				rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1306						<0 RK_PA6 1 &pcfg_pull_none>;
1307			};
1308		};
1309
1310		pdm-0 {
1311			pdmm0_clk: pdmm0-clk {
1312				rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1313			};
1314
1315			pdmm0_fsync: pdmm0-fsync {
1316				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1317			};
1318
1319			pdmm0_sdi0: pdmm0-sdi0 {
1320				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1321			};
1322
1323			pdmm0_sdi1: pdmm0-sdi1 {
1324				rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1325			};
1326
1327			pdmm0_sdi2: pdmm0-sdi2 {
1328				rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1329			};
1330
1331			pdmm0_sdi3: pdmm0-sdi3 {
1332				rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1333			};
1334
1335			pdmm0_clk_sleep: pdmm0-clk-sleep {
1336				rockchip,pins =
1337					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1338			};
1339
1340			pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1341				rockchip,pins =
1342					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1343			};
1344
1345			pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1346				rockchip,pins =
1347					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1348			};
1349
1350			pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1351				rockchip,pins =
1352					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1353			};
1354
1355			pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1356				rockchip,pins =
1357					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1358			};
1359
1360			pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1361				rockchip,pins =
1362					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1363			};
1364		};
1365
1366		tsadc {
1367			otp_pin: otp-pin {
1368				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1369			};
1370
1371			otp_out: otp-out {
1372				rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1373			};
1374		};
1375
1376		uart0 {
1377			uart0_xfer: uart0-xfer {
1378				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1379						<1 RK_PB0 1 &pcfg_pull_up>;
1380			};
1381
1382			uart0_cts: uart0-cts {
1383				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1384			};
1385
1386			uart0_rts: uart0-rts {
1387				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1388			};
1389
1390			uart0_rts_pin: uart0-rts-pin {
1391				rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1392			};
1393		};
1394
1395		uart1 {
1396			uart1_xfer: uart1-xfer {
1397				rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1398						<3 RK_PA6 4 &pcfg_pull_up>;
1399			};
1400
1401			uart1_cts: uart1-cts {
1402				rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1403			};
1404
1405			uart1_rts: uart1-rts {
1406				rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1407			};
1408
1409			uart1_rts_pin: uart1-rts-pin {
1410				rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1411			};
1412		};
1413
1414		uart2-0 {
1415			uart2m0_xfer: uart2m0-xfer {
1416				rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1417						<1 RK_PA1 2 &pcfg_pull_up>;
1418			};
1419		};
1420
1421		uart2-1 {
1422			uart2m1_xfer: uart2m1-xfer {
1423				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1424						<2 RK_PA1 1 &pcfg_pull_up>;
1425			};
1426		};
1427
1428		spi0-0 {
1429			spi0m0_clk: spi0m0-clk {
1430				rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1431			};
1432
1433			spi0m0_cs0: spi0m0-cs0 {
1434				rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1435			};
1436
1437			spi0m0_tx: spi0m0-tx {
1438				rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1439			};
1440
1441			spi0m0_rx: spi0m0-rx {
1442				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1443			};
1444
1445			spi0m0_cs1: spi0m0-cs1 {
1446				rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1447			};
1448		};
1449
1450		spi0-1 {
1451			spi0m1_clk: spi0m1-clk {
1452				rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1453			};
1454
1455			spi0m1_cs0: spi0m1-cs0 {
1456				rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1457			};
1458
1459			spi0m1_tx: spi0m1-tx {
1460				rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1461			};
1462
1463			spi0m1_rx: spi0m1-rx {
1464				rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1465			};
1466
1467			spi0m1_cs1: spi0m1-cs1 {
1468				rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1469			};
1470		};
1471
1472		spi0-2 {
1473			spi0m2_clk: spi0m2-clk {
1474				rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1475			};
1476
1477			spi0m2_cs0: spi0m2-cs0 {
1478				rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1479			};
1480
1481			spi0m2_tx: spi0m2-tx {
1482				rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1483			};
1484
1485			spi0m2_rx: spi0m2-rx {
1486				rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1487			};
1488		};
1489
1490		i2s1 {
1491			i2s1_mclk: i2s1-mclk {
1492				rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1493			};
1494
1495			i2s1_sclk: i2s1-sclk {
1496				rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1497			};
1498
1499			i2s1_lrckrx: i2s1-lrckrx {
1500				rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1501			};
1502
1503			i2s1_lrcktx: i2s1-lrcktx {
1504				rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1505			};
1506
1507			i2s1_sdi: i2s1-sdi {
1508				rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1509			};
1510
1511			i2s1_sdo: i2s1-sdo {
1512				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1513			};
1514
1515			i2s1_sdio1: i2s1-sdio1 {
1516				rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1517			};
1518
1519			i2s1_sdio2: i2s1-sdio2 {
1520				rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1521			};
1522
1523			i2s1_sdio3: i2s1-sdio3 {
1524				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1525			};
1526
1527			i2s1_sleep: i2s1-sleep {
1528				rockchip,pins =
1529					<2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1530					<2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1531					<2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1532					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1533					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1534					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1535					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1536					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1537					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1538			};
1539		};
1540
1541		i2s2-0 {
1542			i2s2m0_mclk: i2s2m0-mclk {
1543				rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1544			};
1545
1546			i2s2m0_sclk: i2s2m0-sclk {
1547				rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1548			};
1549
1550			i2s2m0_lrckrx: i2s2m0-lrckrx {
1551				rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1552			};
1553
1554			i2s2m0_lrcktx: i2s2m0-lrcktx {
1555				rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1556			};
1557
1558			i2s2m0_sdi: i2s2m0-sdi {
1559				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1560			};
1561
1562			i2s2m0_sdo: i2s2m0-sdo {
1563				rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1564			};
1565
1566			i2s2m0_sleep: i2s2m0-sleep {
1567				rockchip,pins =
1568					<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1569					<1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1570					<1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1571					<1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1572					<1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1573					<1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1574			};
1575		};
1576
1577		i2s2-1 {
1578			i2s2m1_mclk: i2s2m1-mclk {
1579				rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1580			};
1581
1582			i2s2m1_sclk: i2s2m1-sclk {
1583				rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1584			};
1585
1586			i2s2m1_lrckrx: i2sm1-lrckrx {
1587				rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1588			};
1589
1590			i2s2m1_lrcktx: i2s2m1-lrcktx {
1591				rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1592			};
1593
1594			i2s2m1_sdi: i2s2m1-sdi {
1595				rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1596			};
1597
1598			i2s2m1_sdo: i2s2m1-sdo {
1599				rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1600			};
1601
1602			i2s2m1_sleep: i2s2m1-sleep {
1603				rockchip,pins =
1604					<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1605					<3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1606					<3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1607					<3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1608					<3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1609			};
1610		};
1611
1612		spdif-0 {
1613			spdifm0_tx: spdifm0-tx {
1614				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1615			};
1616		};
1617
1618		spdif-1 {
1619			spdifm1_tx: spdifm1-tx {
1620				rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1621			};
1622		};
1623
1624		spdif-2 {
1625			spdifm2_tx: spdifm2-tx {
1626				rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1627			};
1628		};
1629
1630		sdmmc0-0 {
1631			sdmmc0m0_pwren: sdmmc0m0-pwren {
1632				rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1633			};
1634
1635			sdmmc0m0_pin: sdmmc0m0-pin {
1636				rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1637			};
1638		};
1639
1640		sdmmc0-1 {
1641			sdmmc0m1_pwren: sdmmc0m1-pwren {
1642				rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1643			};
1644
1645			sdmmc0m1_pin: sdmmc0m1-pin {
1646				rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1647			};
1648		};
1649
1650		sdmmc0 {
1651			sdmmc0_clk: sdmmc0-clk {
1652				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1653			};
1654
1655			sdmmc0_cmd: sdmmc0-cmd {
1656				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1657			};
1658
1659			sdmmc0_dectn: sdmmc0-dectn {
1660				rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1661			};
1662
1663			sdmmc0_wrprt: sdmmc0-wrprt {
1664				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1665			};
1666
1667			sdmmc0_bus1: sdmmc0-bus1 {
1668				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1669			};
1670
1671			sdmmc0_bus4: sdmmc0-bus4 {
1672				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1673						<1 RK_PA1 1 &pcfg_pull_up_8ma>,
1674						<1 RK_PA2 1 &pcfg_pull_up_8ma>,
1675						<1 RK_PA3 1 &pcfg_pull_up_8ma>;
1676			};
1677
1678			sdmmc0_pins: sdmmc0-pins {
1679				rockchip,pins =
1680					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1681					<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1682					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1683					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1684					<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1685					<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1686					<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1687					<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1688			};
1689		};
1690
1691		sdmmc0ext {
1692			sdmmc0ext_clk: sdmmc0ext-clk {
1693				rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1694			};
1695
1696			sdmmc0ext_cmd: sdmmc0ext-cmd {
1697				rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1698			};
1699
1700			sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1701				rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1702			};
1703
1704			sdmmc0ext_dectn: sdmmc0ext-dectn {
1705				rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1706			};
1707
1708			sdmmc0ext_bus1: sdmmc0ext-bus1 {
1709				rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1710			};
1711
1712			sdmmc0ext_bus4: sdmmc0ext-bus4 {
1713				rockchip,pins =
1714					<3 RK_PA4 3 &pcfg_pull_up_4ma>,
1715					<3 RK_PA5 3 &pcfg_pull_up_4ma>,
1716					<3 RK_PA6 3 &pcfg_pull_up_4ma>,
1717					<3 RK_PA7 3 &pcfg_pull_up_4ma>;
1718			};
1719
1720			sdmmc0ext_pins: sdmmc0ext-pins {
1721				rockchip,pins =
1722					<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1723					<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1724					<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1725					<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1726					<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1727					<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1728					<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1729					<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1730			};
1731		};
1732
1733		sdmmc1 {
1734			sdmmc1_clk: sdmmc1-clk {
1735				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1736			};
1737
1738			sdmmc1_cmd: sdmmc1-cmd {
1739				rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1740			};
1741
1742			sdmmc1_pwren: sdmmc1-pwren {
1743				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1744			};
1745
1746			sdmmc1_wrprt: sdmmc1-wrprt {
1747				rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1748			};
1749
1750			sdmmc1_dectn: sdmmc1-dectn {
1751				rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1752			};
1753
1754			sdmmc1_bus1: sdmmc1-bus1 {
1755				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1756			};
1757
1758			sdmmc1_bus4: sdmmc1-bus4 {
1759				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1760						<1 RK_PB7 1 &pcfg_pull_up_8ma>,
1761						<1 RK_PC0 1 &pcfg_pull_up_8ma>,
1762						<1 RK_PC1 1 &pcfg_pull_up_8ma>;
1763			};
1764
1765			sdmmc1_pins: sdmmc1-pins {
1766				rockchip,pins =
1767					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1768					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1769					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1770					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1771					<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1772					<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1773					<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1774					<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1775					<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1776			};
1777		};
1778
1779		emmc {
1780			emmc_clk: emmc-clk {
1781				rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1782			};
1783
1784			emmc_cmd: emmc-cmd {
1785				rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1786			};
1787
1788			emmc_pwren: emmc-pwren {
1789				rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1790			};
1791
1792			emmc_rstnout: emmc-rstnout {
1793				rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1794			};
1795
1796			emmc_bus1: emmc-bus1 {
1797				rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1798			};
1799
1800			emmc_bus4: emmc-bus4 {
1801				rockchip,pins =
1802					<0 RK_PA7 2 &pcfg_pull_up_12ma>,
1803					<2 RK_PD4 2 &pcfg_pull_up_12ma>,
1804					<2 RK_PD5 2 &pcfg_pull_up_12ma>,
1805					<2 RK_PD6 2 &pcfg_pull_up_12ma>;
1806			};
1807
1808			emmc_bus8: emmc-bus8 {
1809				rockchip,pins =
1810					<0 RK_PA7 2 &pcfg_pull_up_12ma>,
1811					<2 RK_PD4 2 &pcfg_pull_up_12ma>,
1812					<2 RK_PD5 2 &pcfg_pull_up_12ma>,
1813					<2 RK_PD6 2 &pcfg_pull_up_12ma>,
1814					<2 RK_PD7 2 &pcfg_pull_up_12ma>,
1815					<3 RK_PC0 2 &pcfg_pull_up_12ma>,
1816					<3 RK_PC1 2 &pcfg_pull_up_12ma>,
1817					<3 RK_PC2 2 &pcfg_pull_up_12ma>;
1818			};
1819		};
1820
1821		pwm0 {
1822			pwm0_pin: pwm0-pin {
1823				rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1824			};
1825		};
1826
1827		pwm1 {
1828			pwm1_pin: pwm1-pin {
1829				rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1830			};
1831		};
1832
1833		pwm2 {
1834			pwm2_pin: pwm2-pin {
1835				rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1836			};
1837		};
1838
1839		pwmir {
1840			pwmir_pin: pwmir-pin {
1841				rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1842			};
1843		};
1844
1845		gmac-1 {
1846			rgmiim1_pins: rgmiim1-pins {
1847				rockchip,pins =
1848					/* mac_txclk */
1849					<1 RK_PB4 2 &pcfg_pull_none_8ma>,
1850					/* mac_rxclk */
1851					<1 RK_PB5 2 &pcfg_pull_none_4ma>,
1852					/* mac_mdio */
1853					<1 RK_PC3 2 &pcfg_pull_none_4ma>,
1854					/* mac_txen */
1855					<1 RK_PD1 2 &pcfg_pull_none_8ma>,
1856					/* mac_clk */
1857					<1 RK_PC5 2 &pcfg_pull_none_4ma>,
1858					/* mac_rxdv */
1859					<1 RK_PC6 2 &pcfg_pull_none_4ma>,
1860					/* mac_mdc */
1861					<1 RK_PC7 2 &pcfg_pull_none_4ma>,
1862					/* mac_rxd1 */
1863					<1 RK_PB2 2 &pcfg_pull_none_4ma>,
1864					/* mac_rxd0 */
1865					<1 RK_PB3 2 &pcfg_pull_none_4ma>,
1866					/* mac_txd1 */
1867					<1 RK_PB0 2 &pcfg_pull_none_8ma>,
1868					/* mac_txd0 */
1869					<1 RK_PB1 2 &pcfg_pull_none_8ma>,
1870					/* mac_rxd3 */
1871					<1 RK_PB6 2 &pcfg_pull_none_4ma>,
1872					/* mac_rxd2 */
1873					<1 RK_PB7 2 &pcfg_pull_none_4ma>,
1874					/* mac_txd3 */
1875					<1 RK_PC0 2 &pcfg_pull_none_8ma>,
1876					/* mac_txd2 */
1877					<1 RK_PC1 2 &pcfg_pull_none_8ma>,
1878
1879					/* mac_txclk */
1880					<0 RK_PB0 1 &pcfg_pull_none_8ma>,
1881					/* mac_txen */
1882					<0 RK_PB4 1 &pcfg_pull_none_8ma>,
1883					/* mac_clk */
1884					<0 RK_PD0 1 &pcfg_pull_none_4ma>,
1885					/* mac_txd1 */
1886					<0 RK_PC0 1 &pcfg_pull_none_8ma>,
1887					/* mac_txd0 */
1888					<0 RK_PC1 1 &pcfg_pull_none_8ma>,
1889					/* mac_txd3 */
1890					<0 RK_PC7 1 &pcfg_pull_none_8ma>,
1891					/* mac_txd2 */
1892					<0 RK_PC6 1 &pcfg_pull_none_8ma>;
1893			};
1894
1895			rmiim1_pins: rmiim1-pins {
1896				rockchip,pins =
1897					/* mac_mdio */
1898					<1 RK_PC3 2 &pcfg_pull_none_2ma>,
1899					/* mac_txen */
1900					<1 RK_PD1 2 &pcfg_pull_none_12ma>,
1901					/* mac_clk */
1902					<1 RK_PC5 2 &pcfg_pull_none_2ma>,
1903					/* mac_rxer */
1904					<1 RK_PD0 2 &pcfg_pull_none_2ma>,
1905					/* mac_rxdv */
1906					<1 RK_PC6 2 &pcfg_pull_none_2ma>,
1907					/* mac_mdc */
1908					<1 RK_PC7 2 &pcfg_pull_none_2ma>,
1909					/* mac_rxd1 */
1910					<1 RK_PB2 2 &pcfg_pull_none_2ma>,
1911					/* mac_rxd0 */
1912					<1 RK_PB3 2 &pcfg_pull_none_2ma>,
1913					/* mac_txd1 */
1914					<1 RK_PB0 2 &pcfg_pull_none_12ma>,
1915					/* mac_txd0 */
1916					<1 RK_PB1 2 &pcfg_pull_none_12ma>,
1917
1918					/* mac_mdio */
1919					<0 RK_PB3 1 &pcfg_pull_none>,
1920					/* mac_txen */
1921					<0 RK_PB4 1 &pcfg_pull_none>,
1922					/* mac_clk */
1923					<0 RK_PD0 1 &pcfg_pull_none>,
1924					/* mac_mdc */
1925					<0 RK_PC3 1 &pcfg_pull_none>,
1926					/* mac_txd1 */
1927					<0 RK_PC0 1 &pcfg_pull_none>,
1928					/* mac_txd0 */
1929					<0 RK_PC1 1 &pcfg_pull_none>;
1930			};
1931		};
1932
1933		gmac2phy {
1934			fephyled_speed10: fephyled-speed10 {
1935				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1936			};
1937
1938			fephyled_duplex: fephyled-duplex {
1939				rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1940			};
1941
1942			fephyled_rxm1: fephyled-rxm1 {
1943				rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1944			};
1945
1946			fephyled_txm1: fephyled-txm1 {
1947				rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1948			};
1949
1950			fephyled_linkm1: fephyled-linkm1 {
1951				rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1952			};
1953		};
1954
1955		tsadc_pin {
1956			tsadc_int: tsadc-int {
1957				rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1958			};
1959			tsadc_pin: tsadc-pin {
1960				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1961			};
1962		};
1963
1964		hdmi_pin {
1965			hdmi_cec: hdmi-cec {
1966				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1967			};
1968
1969			hdmi_hpd: hdmi-hpd {
1970				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1971			};
1972		};
1973
1974		cif-0 {
1975			dvp_d2d9_m0:dvp-d2d9-m0 {
1976				rockchip,pins =
1977					/* cif_d0 */
1978					<3 RK_PA4 2 &pcfg_pull_none>,
1979					/* cif_d1 */
1980					<3 RK_PA5 2 &pcfg_pull_none>,
1981					/* cif_d2 */
1982					<3 RK_PA6 2 &pcfg_pull_none>,
1983					/* cif_d3 */
1984					<3 RK_PA7 2 &pcfg_pull_none>,
1985					/* cif_d4 */
1986					<3 RK_PB0 2 &pcfg_pull_none>,
1987					/* cif_d5m0 */
1988					<3 RK_PB1 2 &pcfg_pull_none>,
1989					/* cif_d6m0 */
1990					<3 RK_PB2 2 &pcfg_pull_none>,
1991					/* cif_d7m0 */
1992					<3 RK_PB3 2 &pcfg_pull_none>,
1993					/* cif_href */
1994					<3 RK_PA1 2 &pcfg_pull_none>,
1995					/* cif_vsync */
1996					<3 RK_PA0 2 &pcfg_pull_none>,
1997					/* cif_clkoutm0 */
1998					<3 RK_PA3 2 &pcfg_pull_none>,
1999					/* cif_clkin */
2000					<3 RK_PA2 2 &pcfg_pull_none>;
2001			};
2002		};
2003
2004		cif-1 {
2005			dvp_d2d9_m1:dvp-d2d9-m1 {
2006				rockchip,pins =
2007					/* cif_d0 */
2008					<3 RK_PA4 2 &pcfg_pull_none>,
2009					/* cif_d1 */
2010					<3 RK_PA5 2 &pcfg_pull_none>,
2011					/* cif_d2 */
2012					<3 RK_PA6 2 &pcfg_pull_none>,
2013					/* cif_d3 */
2014					<3 RK_PA7 2 &pcfg_pull_none>,
2015					/* cif_d4 */
2016					<3 RK_PB0 2 &pcfg_pull_none>,
2017					/* cif_d5m1 */
2018					<2 RK_PC0 4 &pcfg_pull_none>,
2019					/* cif_d6m1 */
2020					<2 RK_PC1 4 &pcfg_pull_none>,
2021					/* cif_d7m1 */
2022					<2 RK_PC2 4 &pcfg_pull_none>,
2023					/* cif_href */
2024					<3 RK_PA1 2 &pcfg_pull_none>,
2025					/* cif_vsync */
2026					<3 RK_PA0 2 &pcfg_pull_none>,
2027					/* cif_clkoutm1 */
2028					<2 RK_PB7 4 &pcfg_pull_none>,
2029					/* cif_clkin */
2030					<3 RK_PA2 2 &pcfg_pull_none>;
2031			};
2032		};
2033	};
2034};