px30.dtsi

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4 */
   5
   6#include <dt-bindings/clock/px30-cru.h>
   7#include <dt-bindings/gpio/gpio.h>
   8#include <dt-bindings/interrupt-controller/arm-gic.h>
   9#include <dt-bindings/interrupt-controller/irq.h>
  10#include <dt-bindings/pinctrl/rockchip.h>
  11#include <dt-bindings/power/px30-power.h>
  12#include <dt-bindings/soc/rockchip,boot-mode.h>
  13#include <dt-bindings/thermal/thermal.h>
  14
  15/ {
  16	compatible = "rockchip,px30";
  17
  18	interrupt-parent = <&gic>;
  19	#address-cells = <2>;
  20	#size-cells = <2>;
  21
  22	aliases {
  23		i2c0 = &i2c0;
  24		i2c1 = &i2c1;
  25		i2c2 = &i2c2;
  26		i2c3 = &i2c3;
  27		serial0 = &uart0;
  28		serial1 = &uart1;
  29		serial2 = &uart2;
  30		serial3 = &uart3;
  31		serial4 = &uart4;
  32		serial5 = &uart5;
  33		spi0 = &spi0;
  34		spi1 = &spi1;
  35	};
  36
  37	cpus {
  38		#address-cells = <2>;
  39		#size-cells = <0>;
  40
  41		cpu0: cpu@0 {
  42			device_type = "cpu";
  43			compatible = "arm,cortex-a35";
  44			reg = <0x0 0x0>;
  45			enable-method = "psci";
  46			clocks = <&cru ARMCLK>;
  47			#cooling-cells = <2>;
  48			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  49			dynamic-power-coefficient = <90>;
  50			operating-points-v2 = <&cpu0_opp_table>;
  51		};
  52
  53		cpu1: cpu@1 {
  54			device_type = "cpu";
  55			compatible = "arm,cortex-a35";
  56			reg = <0x0 0x1>;
  57			enable-method = "psci";
  58			clocks = <&cru ARMCLK>;
  59			#cooling-cells = <2>;
  60			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  61			dynamic-power-coefficient = <90>;
  62			operating-points-v2 = <&cpu0_opp_table>;
  63		};
  64
  65		cpu2: cpu@2 {
  66			device_type = "cpu";
  67			compatible = "arm,cortex-a35";
  68			reg = <0x0 0x2>;
  69			enable-method = "psci";
  70			clocks = <&cru ARMCLK>;
  71			#cooling-cells = <2>;
  72			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  73			dynamic-power-coefficient = <90>;
  74			operating-points-v2 = <&cpu0_opp_table>;
  75		};
  76
  77		cpu3: cpu@3 {
  78			device_type = "cpu";
  79			compatible = "arm,cortex-a35";
  80			reg = <0x0 0x3>;
  81			enable-method = "psci";
  82			clocks = <&cru ARMCLK>;
  83			#cooling-cells = <2>;
  84			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  85			dynamic-power-coefficient = <90>;
  86			operating-points-v2 = <&cpu0_opp_table>;
  87		};
  88
  89		idle-states {
  90			entry-method = "psci";
  91
  92			CPU_SLEEP: cpu-sleep {
  93				compatible = "arm,idle-state";
  94				local-timer-stop;
  95				arm,psci-suspend-param = <0x0010000>;
  96				entry-latency-us = <120>;
  97				exit-latency-us = <250>;
  98				min-residency-us = <900>;
  99			};
 100
 101			CLUSTER_SLEEP: cluster-sleep {
 102				compatible = "arm,idle-state";
 103				local-timer-stop;
 104				arm,psci-suspend-param = <0x1010000>;
 105				entry-latency-us = <400>;
 106				exit-latency-us = <500>;
 107				min-residency-us = <2000>;
 108			};
 109		};
 110	};
 111
 112	cpu0_opp_table: opp-table-0 {
 113		compatible = "operating-points-v2";
 114		opp-shared;
 115
 116		opp-600000000 {
 117			opp-hz = /bits/ 64 <600000000>;
 118			opp-microvolt = <950000 950000 1350000>;
 119			clock-latency-ns = <40000>;
 120			opp-suspend;
 121		};
 122		opp-816000000 {
 123			opp-hz = /bits/ 64 <816000000>;
 124			opp-microvolt = <1050000 1050000 1350000>;
 125			clock-latency-ns = <40000>;
 126		};
 127		opp-1008000000 {
 128			opp-hz = /bits/ 64 <1008000000>;
 129			opp-microvolt = <1175000 1175000 1350000>;
 130			clock-latency-ns = <40000>;
 131		};
 132		opp-1200000000 {
 133			opp-hz = /bits/ 64 <1200000000>;
 134			opp-microvolt = <1300000 1300000 1350000>;
 135			clock-latency-ns = <40000>;
 136		};
 137		opp-1296000000 {
 138			opp-hz = /bits/ 64 <1296000000>;
 139			opp-microvolt = <1350000 1350000 1350000>;
 140			clock-latency-ns = <40000>;
 141		};
 142	};
 143
 144	arm-pmu {
 145		compatible = "arm,cortex-a35-pmu";
 146		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 147			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 148			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 149			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 150		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 151	};
 152
 153	display_subsystem: display-subsystem {
 154		compatible = "rockchip,display-subsystem";
 155		ports = <&vopb_out>, <&vopl_out>;
 156		status = "disabled";
 157	};
 158
 159	gmac_clkin: external-gmac-clock {
 160		compatible = "fixed-clock";
 161		clock-frequency = <50000000>;
 162		clock-output-names = "gmac_clkin";
 163		#clock-cells = <0>;
 164	};
 165
 166	psci {
 167		compatible = "arm,psci-1.0";
 168		method = "smc";
 169	};
 170
 171	timer {
 172		compatible = "arm,armv8-timer";
 173		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 174			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177	};
 178
 179	thermal_zones: thermal-zones {
 180		soc_thermal: soc-thermal {
 181			polling-delay-passive = <20>;
 182			polling-delay = <1000>;
 183			sustainable-power = <750>;
 184			thermal-sensors = <&tsadc 0>;
 185
 186			trips {
 187				threshold: trip-point-0 {
 188					temperature = <70000>;
 189					hysteresis = <2000>;
 190					type = "passive";
 191				};
 192
 193				target: trip-point-1 {
 194					temperature = <85000>;
 195					hysteresis = <2000>;
 196					type = "passive";
 197				};
 198
 199				soc_crit: soc-crit {
 200					temperature = <115000>;
 201					hysteresis = <2000>;
 202					type = "critical";
 203				};
 204			};
 205
 206			cooling-maps {
 207				map0 {
 208					trip = <&target>;
 209					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 210					contribution = <4096>;
 211				};
 212			};
 213		};
 214
 215		gpu_thermal: gpu-thermal {
 216			polling-delay-passive = <100>; /* milliseconds */
 217			polling-delay = <1000>; /* milliseconds */
 218			thermal-sensors = <&tsadc 1>;
 219
 220			trips {
 221				gpu_threshold: gpu-threshold {
 222					temperature = <70000>;
 223					hysteresis = <2000>;
 224					type = "passive";
 225				};
 226
 227				gpu_target: gpu-target {
 228					temperature = <85000>;
 229					hysteresis = <2000>;
 230					type = "passive";
 231				};
 232
 233				gpu_crit: gpu-crit {
 234					temperature = <115000>;
 235					hysteresis = <2000>;
 236					type = "critical";
 237				};
 238			};
 239
 240			cooling-maps {
 241				map0 {
 242					trip = <&gpu_target>;
 243					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 244				};
 245			};
 246		};
 247	};
 248
 249	xin24m: xin24m {
 250		compatible = "fixed-clock";
 251		#clock-cells = <0>;
 252		clock-frequency = <24000000>;
 253		clock-output-names = "xin24m";
 254	};
 255
 256	pmu: power-management@ff000000 {
 257		compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 258		reg = <0x0 0xff000000 0x0 0x1000>;
 259
 260		power: power-controller {
 261			compatible = "rockchip,px30-power-controller";
 262			#power-domain-cells = <1>;
 263			#address-cells = <1>;
 264			#size-cells = <0>;
 265
 266			/* These power domains are grouped by VD_LOGIC */
 267			power-domain@PX30_PD_USB {
 268				reg = <PX30_PD_USB>;
 269				clocks = <&cru HCLK_HOST>,
 270					 <&cru HCLK_OTG>,
 271					 <&cru SCLK_OTG_ADP>;
 272				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 273				#power-domain-cells = <0>;
 274			};
 275			power-domain@PX30_PD_SDCARD {
 276				reg = <PX30_PD_SDCARD>;
 277				clocks = <&cru HCLK_SDMMC>,
 278					 <&cru SCLK_SDMMC>;
 279				pm_qos = <&qos_sdmmc>;
 280				#power-domain-cells = <0>;
 281			};
 282			power-domain@PX30_PD_GMAC {
 283				reg = <PX30_PD_GMAC>;
 284				clocks = <&cru ACLK_GMAC>,
 285					 <&cru PCLK_GMAC>,
 286					 <&cru SCLK_MAC_REF>,
 287					 <&cru SCLK_GMAC_RX_TX>;
 288				pm_qos = <&qos_gmac>;
 289				#power-domain-cells = <0>;
 290			};
 291			power-domain@PX30_PD_MMC_NAND {
 292				reg = <PX30_PD_MMC_NAND>;
 293				clocks = <&cru HCLK_NANDC>,
 294					 <&cru HCLK_EMMC>,
 295					 <&cru HCLK_SDIO>,
 296					 <&cru HCLK_SFC>,
 297					 <&cru SCLK_EMMC>,
 298					 <&cru SCLK_NANDC>,
 299					 <&cru SCLK_SDIO>,
 300					 <&cru SCLK_SFC>;
 301				pm_qos = <&qos_emmc>, <&qos_nand>,
 302					 <&qos_sdio>, <&qos_sfc>;
 303				#power-domain-cells = <0>;
 304			};
 305			power-domain@PX30_PD_VPU {
 306				reg = <PX30_PD_VPU>;
 307				clocks = <&cru ACLK_VPU>,
 308					 <&cru HCLK_VPU>,
 309					 <&cru SCLK_CORE_VPU>;
 310				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 311				#power-domain-cells = <0>;
 312			};
 313			power-domain@PX30_PD_VO {
 314				reg = <PX30_PD_VO>;
 315				clocks = <&cru ACLK_RGA>,
 316					 <&cru ACLK_VOPB>,
 317					 <&cru ACLK_VOPL>,
 318					 <&cru DCLK_VOPB>,
 319					 <&cru DCLK_VOPL>,
 320					 <&cru HCLK_RGA>,
 321					 <&cru HCLK_VOPB>,
 322					 <&cru HCLK_VOPL>,
 323					 <&cru PCLK_MIPI_DSI>,
 324					 <&cru SCLK_RGA_CORE>,
 325					 <&cru SCLK_VOPB_PWM>;
 326				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 327					 <&qos_vop_m0>, <&qos_vop_m1>;
 328				#power-domain-cells = <0>;
 329			};
 330			power-domain@PX30_PD_VI {
 331				reg = <PX30_PD_VI>;
 332				clocks = <&cru ACLK_CIF>,
 333					 <&cru ACLK_ISP>,
 334					 <&cru HCLK_CIF>,
 335					 <&cru HCLK_ISP>,
 336					 <&cru SCLK_ISP>;
 337				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 338					 <&qos_isp_wr>, <&qos_isp_m1>,
 339					 <&qos_vip>;
 340				#power-domain-cells = <0>;
 341			};
 342			power-domain@PX30_PD_GPU {
 343				reg = <PX30_PD_GPU>;
 344				clocks = <&cru SCLK_GPU>;
 345				pm_qos = <&qos_gpu>;
 346				#power-domain-cells = <0>;
 347			};
 348		};
 349	};
 350
 351	pmugrf: syscon@ff010000 {
 352		compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 353		reg = <0x0 0xff010000 0x0 0x1000>;
 354
 355		pmu_io_domains: io-domains {
 356			compatible = "rockchip,px30-pmu-io-voltage-domain";
 357			status = "disabled";
 358		};
 359
 360		reboot-mode {
 361			compatible = "syscon-reboot-mode";
 362			offset = <0x200>;
 363			mode-bootloader = <BOOT_BL_DOWNLOAD>;
 364			mode-fastboot = <BOOT_FASTBOOT>;
 365			mode-loader = <BOOT_BL_DOWNLOAD>;
 366			mode-normal = <BOOT_NORMAL>;
 367			mode-recovery = <BOOT_RECOVERY>;
 368		};
 369	};
 370
 371	uart0: serial@ff030000 {
 372		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 373		reg = <0x0 0xff030000 0x0 0x100>;
 374		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 375		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 376		clock-names = "baudclk", "apb_pclk";
 377		dmas = <&dmac 0>, <&dmac 1>;
 378		dma-names = "tx", "rx";
 379		reg-shift = <2>;
 380		reg-io-width = <4>;
 381		pinctrl-names = "default";
 382		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 383		status = "disabled";
 384	};
 385
 386	i2s0_8ch: i2s@ff060000 {
 387		compatible = "rockchip,px30-i2s-tdm";
 388		reg = <0x0 0xff060000 0x0 0x1000>;
 389		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 390		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
 391		clock-names = "mclk_tx", "mclk_rx", "hclk";
 392		dmas = <&dmac 16>, <&dmac 17>;
 393		dma-names = "tx", "rx";
 394		rockchip,grf = <&grf>;
 395		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
 396		reset-names = "tx-m", "rx-m";
 397		pinctrl-names = "default";
 398		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
 399			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
 400			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
 401			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
 402			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
 403			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
 404		#sound-dai-cells = <0>;
 405		status = "disabled";
 406	};
 407
 408	i2s1_2ch: i2s@ff070000 {
 409		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 410		reg = <0x0 0xff070000 0x0 0x1000>;
 411		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 412		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 413		clock-names = "i2s_clk", "i2s_hclk";
 414		dmas = <&dmac 18>, <&dmac 19>;
 415		dma-names = "tx", "rx";
 416		pinctrl-names = "default";
 417		pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 418			     &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 419		#sound-dai-cells = <0>;
 420		status = "disabled";
 421	};
 422
 423	i2s2_2ch: i2s@ff080000 {
 424		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 425		reg = <0x0 0xff080000 0x0 0x1000>;
 426		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 427		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 428		clock-names = "i2s_clk", "i2s_hclk";
 429		dmas = <&dmac 20>, <&dmac 21>;
 430		dma-names = "tx", "rx";
 431		pinctrl-names = "default";
 432		pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 433			     &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 434		#sound-dai-cells = <0>;
 435		status = "disabled";
 436	};
 437
 438	gic: interrupt-controller@ff131000 {
 439		compatible = "arm,gic-400";
 440		#interrupt-cells = <3>;
 441		#address-cells = <0>;
 442		interrupt-controller;
 443		reg = <0x0 0xff131000 0 0x1000>,
 444		      <0x0 0xff132000 0 0x2000>,
 445		      <0x0 0xff134000 0 0x2000>,
 446		      <0x0 0xff136000 0 0x2000>;
 447		interrupts = <GIC_PPI 9
 448		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 449	};
 450
 451	grf: syscon@ff140000 {
 452		compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 453		reg = <0x0 0xff140000 0x0 0x1000>;
 454
 455		io_domains: io-domains {
 456			compatible = "rockchip,px30-io-voltage-domain";
 457			status = "disabled";
 458		};
 459
 460		lvds: lvds {
 461			compatible = "rockchip,px30-lvds";
 462			phys = <&dsi_dphy>;
 463			phy-names = "dphy";
 464			rockchip,grf = <&grf>;
 465			rockchip,output = "lvds";
 466			status = "disabled";
 467
 468			ports {
 469				#address-cells = <1>;
 470				#size-cells = <0>;
 471
 472				lvds_in: port@0 {
 473					reg = <0>;
 474					#address-cells = <1>;
 475					#size-cells = <0>;
 476
 477					lvds_vopb_in: endpoint@0 {
 478						reg = <0>;
 479						remote-endpoint = <&vopb_out_lvds>;
 480					};
 481
 482					lvds_vopl_in: endpoint@1 {
 483						reg = <1>;
 484						remote-endpoint = <&vopl_out_lvds>;
 485					};
 486				};
 487
 488				lvds_out: port@1 {
 489					reg = <1>;
 490				};
 491			};
 492		};
 493	};
 494
 495	uart1: serial@ff158000 {
 496		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 497		reg = <0x0 0xff158000 0x0 0x100>;
 498		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 499		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 500		clock-names = "baudclk", "apb_pclk";
 501		dmas = <&dmac 2>, <&dmac 3>;
 502		dma-names = "tx", "rx";
 503		reg-shift = <2>;
 504		reg-io-width = <4>;
 505		pinctrl-names = "default";
 506		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 507		status = "disabled";
 508	};
 509
 510	uart2: serial@ff160000 {
 511		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 512		reg = <0x0 0xff160000 0x0 0x100>;
 513		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 514		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 515		clock-names = "baudclk", "apb_pclk";
 516		dmas = <&dmac 4>, <&dmac 5>;
 517		dma-names = "tx", "rx";
 518		reg-shift = <2>;
 519		reg-io-width = <4>;
 520		pinctrl-names = "default";
 521		pinctrl-0 = <&uart2m0_xfer>;
 522		status = "disabled";
 523	};
 524
 525	uart3: serial@ff168000 {
 526		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 527		reg = <0x0 0xff168000 0x0 0x100>;
 528		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 529		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 530		clock-names = "baudclk", "apb_pclk";
 531		dmas = <&dmac 6>, <&dmac 7>;
 532		dma-names = "tx", "rx";
 533		reg-shift = <2>;
 534		reg-io-width = <4>;
 535		pinctrl-names = "default";
 536		pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 537		status = "disabled";
 538	};
 539
 540	uart4: serial@ff170000 {
 541		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 542		reg = <0x0 0xff170000 0x0 0x100>;
 543		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 544		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 545		clock-names = "baudclk", "apb_pclk";
 546		dmas = <&dmac 8>, <&dmac 9>;
 547		dma-names = "tx", "rx";
 548		reg-shift = <2>;
 549		reg-io-width = <4>;
 550		pinctrl-names = "default";
 551		pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 552		status = "disabled";
 553	};
 554
 555	uart5: serial@ff178000 {
 556		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 557		reg = <0x0 0xff178000 0x0 0x100>;
 558		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 559		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 560		clock-names = "baudclk", "apb_pclk";
 561		dmas = <&dmac 10>, <&dmac 11>;
 562		dma-names = "tx", "rx";
 563		reg-shift = <2>;
 564		reg-io-width = <4>;
 565		pinctrl-names = "default";
 566		pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 567		status = "disabled";
 568	};
 569
 570	i2c0: i2c@ff180000 {
 571		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 572		reg = <0x0 0xff180000 0x0 0x1000>;
 573		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 574		clock-names = "i2c", "pclk";
 575		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 576		pinctrl-names = "default";
 577		pinctrl-0 = <&i2c0_xfer>;
 578		#address-cells = <1>;
 579		#size-cells = <0>;
 580		status = "disabled";
 581	};
 582
 583	i2c1: i2c@ff190000 {
 584		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 585		reg = <0x0 0xff190000 0x0 0x1000>;
 586		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 587		clock-names = "i2c", "pclk";
 588		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 589		pinctrl-names = "default";
 590		pinctrl-0 = <&i2c1_xfer>;
 591		#address-cells = <1>;
 592		#size-cells = <0>;
 593		status = "disabled";
 594	};
 595
 596	i2c2: i2c@ff1a0000 {
 597		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 598		reg = <0x0 0xff1a0000 0x0 0x1000>;
 599		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 600		clock-names = "i2c", "pclk";
 601		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 602		pinctrl-names = "default";
 603		pinctrl-0 = <&i2c2_xfer>;
 604		#address-cells = <1>;
 605		#size-cells = <0>;
 606		status = "disabled";
 607	};
 608
 609	i2c3: i2c@ff1b0000 {
 610		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 611		reg = <0x0 0xff1b0000 0x0 0x1000>;
 612		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 613		clock-names = "i2c", "pclk";
 614		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 615		pinctrl-names = "default";
 616		pinctrl-0 = <&i2c3_xfer>;
 617		#address-cells = <1>;
 618		#size-cells = <0>;
 619		status = "disabled";
 620	};
 621
 622	spi0: spi@ff1d0000 {
 623		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 624		reg = <0x0 0xff1d0000 0x0 0x1000>;
 625		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 626		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 627		clock-names = "spiclk", "apb_pclk";
 628		dmas = <&dmac 12>, <&dmac 13>;
 629		dma-names = "tx", "rx";
 630		num-cs = <2>;
 631		pinctrl-names = "default";
 632		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 633		#address-cells = <1>;
 634		#size-cells = <0>;
 635		status = "disabled";
 636	};
 637
 638	spi1: spi@ff1d8000 {
 639		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 640		reg = <0x0 0xff1d8000 0x0 0x1000>;
 641		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 642		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 643		clock-names = "spiclk", "apb_pclk";
 644		dmas = <&dmac 14>, <&dmac 15>;
 645		dma-names = "tx", "rx";
 646		num-cs = <2>;
 647		pinctrl-names = "default";
 648		pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 649		#address-cells = <1>;
 650		#size-cells = <0>;
 651		status = "disabled";
 652	};
 653
 654	wdt: watchdog@ff1e0000 {
 655		compatible = "rockchip,px30-wdt", "snps,dw-wdt";
 656		reg = <0x0 0xff1e0000 0x0 0x100>;
 657		clocks = <&cru PCLK_WDT_NS>;
 658		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 659		status = "disabled";
 660	};
 661
 662	pwm0: pwm@ff200000 {
 663		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 664		reg = <0x0 0xff200000 0x0 0x10>;
 665		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 666		clock-names = "pwm", "pclk";
 667		pinctrl-names = "default";
 668		pinctrl-0 = <&pwm0_pin>;
 669		#pwm-cells = <3>;
 670		status = "disabled";
 671	};
 672
 673	pwm1: pwm@ff200010 {
 674		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 675		reg = <0x0 0xff200010 0x0 0x10>;
 676		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 677		clock-names = "pwm", "pclk";
 678		pinctrl-names = "default";
 679		pinctrl-0 = <&pwm1_pin>;
 680		#pwm-cells = <3>;
 681		status = "disabled";
 682	};
 683
 684	pwm2: pwm@ff200020 {
 685		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 686		reg = <0x0 0xff200020 0x0 0x10>;
 687		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 688		clock-names = "pwm", "pclk";
 689		pinctrl-names = "default";
 690		pinctrl-0 = <&pwm2_pin>;
 691		#pwm-cells = <3>;
 692		status = "disabled";
 693	};
 694
 695	pwm3: pwm@ff200030 {
 696		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 697		reg = <0x0 0xff200030 0x0 0x10>;
 698		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 699		clock-names = "pwm", "pclk";
 700		pinctrl-names = "default";
 701		pinctrl-0 = <&pwm3_pin>;
 702		#pwm-cells = <3>;
 703		status = "disabled";
 704	};
 705
 706	pwm4: pwm@ff208000 {
 707		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 708		reg = <0x0 0xff208000 0x0 0x10>;
 709		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 710		clock-names = "pwm", "pclk";
 711		pinctrl-names = "default";
 712		pinctrl-0 = <&pwm4_pin>;
 713		#pwm-cells = <3>;
 714		status = "disabled";
 715	};
 716
 717	pwm5: pwm@ff208010 {
 718		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 719		reg = <0x0 0xff208010 0x0 0x10>;
 720		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 721		clock-names = "pwm", "pclk";
 722		pinctrl-names = "default";
 723		pinctrl-0 = <&pwm5_pin>;
 724		#pwm-cells = <3>;
 725		status = "disabled";
 726	};
 727
 728	pwm6: pwm@ff208020 {
 729		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 730		reg = <0x0 0xff208020 0x0 0x10>;
 731		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 732		clock-names = "pwm", "pclk";
 733		pinctrl-names = "default";
 734		pinctrl-0 = <&pwm6_pin>;
 735		#pwm-cells = <3>;
 736		status = "disabled";
 737	};
 738
 739	pwm7: pwm@ff208030 {
 740		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 741		reg = <0x0 0xff208030 0x0 0x10>;
 742		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 743		clock-names = "pwm", "pclk";
 744		pinctrl-names = "default";
 745		pinctrl-0 = <&pwm7_pin>;
 746		#pwm-cells = <3>;
 747		status = "disabled";
 748	};
 749
 750	rktimer: timer@ff210000 {
 751		compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 752		reg = <0x0 0xff210000 0x0 0x1000>;
 753		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 754		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 755		clock-names = "pclk", "timer";
 756	};
 757
 758	dmac: dma-controller@ff240000 {
 759		compatible = "arm,pl330", "arm,primecell";
 760		reg = <0x0 0xff240000 0x0 0x4000>;
 761		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 762			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 763		arm,pl330-periph-burst;
 764		clocks = <&cru ACLK_DMAC>;
 765		clock-names = "apb_pclk";
 766		#dma-cells = <1>;
 767	};
 768
 769	tsadc: tsadc@ff280000 {
 770		compatible = "rockchip,px30-tsadc";
 771		reg = <0x0 0xff280000 0x0 0x100>;
 772		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 773		assigned-clocks = <&cru SCLK_TSADC>;
 774		assigned-clock-rates = <50000>;
 775		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 776		clock-names = "tsadc", "apb_pclk";
 777		resets = <&cru SRST_TSADC>;
 778		reset-names = "tsadc-apb";
 779		rockchip,grf = <&grf>;
 780		rockchip,hw-tshut-temp = <120000>;
 781		pinctrl-names = "init", "default", "sleep";
 782		pinctrl-0 = <&tsadc_otp_pin>;
 783		pinctrl-1 = <&tsadc_otp_out>;
 784		pinctrl-2 = <&tsadc_otp_pin>;
 785		#thermal-sensor-cells = <1>;
 786		status = "disabled";
 787	};
 788
 789	saradc: saradc@ff288000 {
 790		compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 791		reg = <0x0 0xff288000 0x0 0x100>;
 792		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 793		#io-channel-cells = <1>;
 794		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 795		clock-names = "saradc", "apb_pclk";
 796		resets = <&cru SRST_SARADC_P>;
 797		reset-names = "saradc-apb";
 798		status = "disabled";
 799	};
 800
 801	otp: nvmem@ff290000 {
 802		compatible = "rockchip,px30-otp";
 803		reg = <0x0 0xff290000 0x0 0x4000>;
 804		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
 805			 <&cru PCLK_OTP_PHY>;
 806		clock-names = "otp", "apb_pclk", "phy";
 807		resets = <&cru SRST_OTP_PHY>;
 808		reset-names = "phy";
 809		#address-cells = <1>;
 810		#size-cells = <1>;
 811
 812		/* Data cells */
 813		cpu_id: id@7 {
 814			reg = <0x07 0x10>;
 815		};
 816		cpu_leakage: cpu-leakage@17 {
 817			reg = <0x17 0x1>;
 818		};
 819		performance: performance@1e {
 820			reg = <0x1e 0x1>;
 821			bits = <4 3>;
 822		};
 823	};
 824
 825	cru: clock-controller@ff2b0000 {
 826		compatible = "rockchip,px30-cru";
 827		reg = <0x0 0xff2b0000 0x0 0x1000>;
 828		clocks = <&xin24m>, <&pmucru PLL_GPLL>;
 829		clock-names = "xin24m", "gpll";
 830		rockchip,grf = <&grf>;
 831		#clock-cells = <1>;
 832		#reset-cells = <1>;
 833
 834		assigned-clocks = <&cru PLL_NPLL>,
 835			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 836			<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
 837			<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
 838
 839		assigned-clock-rates = <1188000000>,
 840			<200000000>, <200000000>,
 841			<150000000>, <150000000>,
 842			<100000000>, <200000000>;
 843	};
 844
 845	pmucru: clock-controller@ff2bc000 {
 846		compatible = "rockchip,px30-pmucru";
 847		reg = <0x0 0xff2bc000 0x0 0x1000>;
 848		clocks = <&xin24m>;
 849		clock-names = "xin24m";
 850		rockchip,grf = <&grf>;
 851		#clock-cells = <1>;
 852		#reset-cells = <1>;
 853
 854		assigned-clocks =
 855			<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
 856			<&pmucru SCLK_WIFI_PMU>;
 857		assigned-clock-rates =
 858			<1200000000>, <100000000>,
 859			<26000000>;
 860	};
 861
 862	usb2phy_grf: syscon@ff2c0000 {
 863		compatible = "rockchip,px30-usb2phy-grf", "syscon",
 864			     "simple-mfd";
 865		reg = <0x0 0xff2c0000 0x0 0x10000>;
 866		#address-cells = <1>;
 867		#size-cells = <1>;
 868
 869		u2phy: usb2phy@100 {
 870			compatible = "rockchip,px30-usb2phy";
 871			reg = <0x100 0x20>;
 872			clocks = <&pmucru SCLK_USBPHY_REF>;
 873			clock-names = "phyclk";
 874			#clock-cells = <0>;
 875			assigned-clocks = <&cru USB480M>;
 876			assigned-clock-parents = <&u2phy>;
 877			clock-output-names = "usb480m_phy";
 878			status = "disabled";
 879
 880			u2phy_host: host-port {
 881				#phy-cells = <0>;
 882				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 883				interrupt-names = "linestate";
 884				status = "disabled";
 885			};
 886
 887			u2phy_otg: otg-port {
 888				#phy-cells = <0>;
 889				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 890					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 891					     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 892				interrupt-names = "otg-bvalid", "otg-id",
 893						  "linestate";
 894				status = "disabled";
 895			};
 896		};
 897	};
 898
 899	dsi_dphy: phy@ff2e0000 {
 900		compatible = "rockchip,px30-dsi-dphy";
 901		reg = <0x0 0xff2e0000 0x0 0x10000>;
 902		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
 903		clock-names = "ref", "pclk";
 904		resets = <&cru SRST_MIPIDSIPHY_P>;
 905		reset-names = "apb";
 906		#phy-cells = <0>;
 907		power-domains = <&power PX30_PD_VO>;
 908		status = "disabled";
 909	};
 910
 911	csi_dphy: phy@ff2f0000 {
 912		compatible = "rockchip,px30-csi-dphy";
 913		reg = <0x0 0xff2f0000 0x0 0x4000>;
 914		clocks = <&cru PCLK_MIPICSIPHY>;
 915		clock-names = "pclk";
 916		#phy-cells = <0>;
 917		power-domains = <&power PX30_PD_VI>;
 918		resets = <&cru SRST_MIPICSIPHY_P>;
 919		reset-names = "apb";
 920		rockchip,grf = <&grf>;
 921		status = "disabled";
 922	};
 923
 924	usb20_otg: usb@ff300000 {
 925		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 926			     "snps,dwc2";
 927		reg = <0x0 0xff300000 0x0 0x40000>;
 928		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 929		clocks = <&cru HCLK_OTG>;
 930		clock-names = "otg";
 931		dr_mode = "otg";
 932		g-np-tx-fifo-size = <16>;
 933		g-rx-fifo-size = <280>;
 934		g-tx-fifo-size = <256 128 128 64 32 16>;
 935		phys = <&u2phy_otg>;
 936		phy-names = "usb2-phy";
 937		power-domains = <&power PX30_PD_USB>;
 938		status = "disabled";
 939	};
 940
 941	usb_host0_ehci: usb@ff340000 {
 942		compatible = "generic-ehci";
 943		reg = <0x0 0xff340000 0x0 0x10000>;
 944		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 945		clocks = <&cru HCLK_HOST>;
 946		phys = <&u2phy_host>;
 947		phy-names = "usb";
 948		power-domains = <&power PX30_PD_USB>;
 949		status = "disabled";
 950	};
 951
 952	usb_host0_ohci: usb@ff350000 {
 953		compatible = "generic-ohci";
 954		reg = <0x0 0xff350000 0x0 0x10000>;
 955		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 956		clocks = <&cru HCLK_HOST>;
 957		phys = <&u2phy_host>;
 958		phy-names = "usb";
 959		power-domains = <&power PX30_PD_USB>;
 960		status = "disabled";
 961	};
 962
 963	gmac: ethernet@ff360000 {
 964		compatible = "rockchip,px30-gmac";
 965		reg = <0x0 0xff360000 0x0 0x10000>;
 966		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 967		interrupt-names = "macirq";
 968		clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 969			 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 970			 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 971			 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 972		clock-names = "stmmaceth", "mac_clk_rx",
 973			      "mac_clk_tx", "clk_mac_ref",
 974			      "clk_mac_refout", "aclk_mac",
 975			      "pclk_mac", "clk_mac_speed";
 976		rockchip,grf = <&grf>;
 977		phy-mode = "rmii";
 978		pinctrl-names = "default";
 979		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 980		power-domains = <&power PX30_PD_GMAC>;
 981		resets = <&cru SRST_GMAC_A>;
 982		reset-names = "stmmaceth";
 983		status = "disabled";
 984
 985		mdio: mdio {
 986			compatible = "snps,dwmac-mdio";
 987			#address-cells = <1>;
 988			#size-cells = <0>;
 989		};
 990	};
 991
 992	sdmmc: mmc@ff370000 {
 993		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 994		reg = <0x0 0xff370000 0x0 0x4000>;
 995		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 996		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 997			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 998		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 999		bus-width = <4>;
1000		fifo-depth = <0x100>;
1001		max-frequency = <150000000>;
1002		pinctrl-names = "default";
1003		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1004		power-domains = <&power PX30_PD_SDCARD>;
1005		status = "disabled";
1006	};
1007
1008	sdio: mmc@ff380000 {
1009		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1010		reg = <0x0 0xff380000 0x0 0x4000>;
1011		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1012		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1013			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1014		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1015		bus-width = <4>;
1016		fifo-depth = <0x100>;
1017		max-frequency = <150000000>;
1018		pinctrl-names = "default";
1019		pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1020		power-domains = <&power PX30_PD_MMC_NAND>;
1021		status = "disabled";
1022	};
1023
1024	emmc: mmc@ff390000 {
1025		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1026		reg = <0x0 0xff390000 0x0 0x4000>;
1027		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1028		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1029			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1030		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1031		bus-width = <8>;
1032		fifo-depth = <0x100>;
1033		max-frequency = <150000000>;
1034		pinctrl-names = "default";
1035		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1036		power-domains = <&power PX30_PD_MMC_NAND>;
1037		status = "disabled";
1038	};
1039
1040	sfc: spi@ff3a0000 {
1041		compatible = "rockchip,sfc";
1042		reg = <0x0 0xff3a0000 0x0 0x4000>;
1043		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1044		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1045		clock-names = "clk_sfc", "hclk_sfc";
1046		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1047		pinctrl-names = "default";
1048		power-domains = <&power PX30_PD_MMC_NAND>;
1049		status = "disabled";
1050	};
1051
1052	nfc: nand-controller@ff3b0000 {
1053		compatible = "rockchip,px30-nfc";
1054		reg = <0x0 0xff3b0000 0x0 0x4000>;
1055		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1056		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1057		clock-names = "ahb", "nfc";
1058		assigned-clocks = <&cru SCLK_NANDC>;
1059		assigned-clock-rates = <150000000>;
1060		pinctrl-names = "default";
1061		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1062			     &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1063		power-domains = <&power PX30_PD_MMC_NAND>;
1064		status = "disabled";
1065	};
1066
1067	gpu_opp_table: opp-table-1 {
1068		compatible = "operating-points-v2";
1069
1070		opp-200000000 {
1071			opp-hz = /bits/ 64 <200000000>;
1072			opp-microvolt = <950000>;
1073		};
1074		opp-300000000 {
1075			opp-hz = /bits/ 64 <300000000>;
1076			opp-microvolt = <975000>;
1077		};
1078		opp-400000000 {
1079			opp-hz = /bits/ 64 <400000000>;
1080			opp-microvolt = <1050000>;
1081		};
1082		opp-480000000 {
1083			opp-hz = /bits/ 64 <480000000>;
1084			opp-microvolt = <1125000>;
1085		};
1086	};
1087
1088	gpu: gpu@ff400000 {
1089		compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1090		reg = <0x0 0xff400000 0x0 0x4000>;
1091		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1092			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1093			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1094		interrupt-names = "job", "mmu", "gpu";
1095		clocks = <&cru SCLK_GPU>;
1096		#cooling-cells = <2>;
1097		power-domains = <&power PX30_PD_GPU>;
1098		operating-points-v2 = <&gpu_opp_table>;
1099		status = "disabled";
1100	};
1101
1102	vpu: video-codec@ff442000 {
1103		compatible = "rockchip,px30-vpu";
1104		reg = <0x0 0xff442000 0x0 0x800>;
1105		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1106			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1107		interrupt-names = "vepu", "vdpu";
1108		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1109		clock-names = "aclk", "hclk";
1110		iommus = <&vpu_mmu>;
1111		power-domains = <&power PX30_PD_VPU>;
1112	};
1113
1114	vpu_mmu: iommu@ff442800 {
1115		compatible = "rockchip,iommu";
1116		reg = <0x0 0xff442800 0x0 0x100>;
1117		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1118		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1119		clock-names = "aclk", "iface";
1120		#iommu-cells = <0>;
1121		power-domains = <&power PX30_PD_VPU>;
1122	};
1123
1124	dsi: dsi@ff450000 {
1125		compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1126		reg = <0x0 0xff450000 0x0 0x10000>;
1127		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1128		clocks = <&cru PCLK_MIPI_DSI>;
1129		clock-names = "pclk";
1130		phys = <&dsi_dphy>;
1131		phy-names = "dphy";
1132		power-domains = <&power PX30_PD_VO>;
1133		resets = <&cru SRST_MIPIDSI_HOST_P>;
1134		reset-names = "apb";
1135		rockchip,grf = <&grf>;
1136		status = "disabled";
1137
1138		ports {
1139			#address-cells = <1>;
1140			#size-cells = <0>;
1141
1142			dsi_in: port@0 {
1143				reg = <0>;
1144				#address-cells = <1>;
1145				#size-cells = <0>;
1146
1147				dsi_in_vopb: endpoint@0 {
1148					reg = <0>;
1149					remote-endpoint = <&vopb_out_dsi>;
1150				};
1151
1152				dsi_in_vopl: endpoint@1 {
1153					reg = <1>;
1154					remote-endpoint = <&vopl_out_dsi>;
1155				};
1156			};
1157
1158			dsi_out: port@1 {
1159				reg = <1>;
1160			};
1161		};
1162	};
1163
1164	vopb: vop@ff460000 {
1165		compatible = "rockchip,px30-vop-big";
1166		reg = <0x0 0xff460000 0x0 0xefc>;
1167		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168		clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169			 <&cru HCLK_VOPB>;
1170		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171		resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172		reset-names = "axi", "ahb", "dclk";
1173		iommus = <&vopb_mmu>;
1174		power-domains = <&power PX30_PD_VO>;
1175		status = "disabled";
1176
1177		vopb_out: port {
1178			#address-cells = <1>;
1179			#size-cells = <0>;
1180
1181			vopb_out_dsi: endpoint@0 {
1182				reg = <0>;
1183				remote-endpoint = <&dsi_in_vopb>;
1184			};
1185
1186			vopb_out_lvds: endpoint@1 {
1187				reg = <1>;
1188				remote-endpoint = <&lvds_vopb_in>;
1189			};
1190		};
1191	};
1192
1193	vopb_mmu: iommu@ff460f00 {
1194		compatible = "rockchip,iommu";
1195		reg = <0x0 0xff460f00 0x0 0x100>;
1196		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1197		clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198		clock-names = "aclk", "iface";
1199		power-domains = <&power PX30_PD_VO>;
1200		#iommu-cells = <0>;
1201		status = "disabled";
1202	};
1203
1204	vopl: vop@ff470000 {
1205		compatible = "rockchip,px30-vop-lit";
1206		reg = <0x0 0xff470000 0x0 0xefc>;
1207		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209			 <&cru HCLK_VOPL>;
1210		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211		resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212		reset-names = "axi", "ahb", "dclk";
1213		iommus = <&vopl_mmu>;
1214		power-domains = <&power PX30_PD_VO>;
1215		status = "disabled";
1216
1217		vopl_out: port {
1218			#address-cells = <1>;
1219			#size-cells = <0>;
1220
1221			vopl_out_dsi: endpoint@0 {
1222				reg = <0>;
1223				remote-endpoint = <&dsi_in_vopl>;
1224			};
1225
1226			vopl_out_lvds: endpoint@1 {
1227				reg = <1>;
1228				remote-endpoint = <&lvds_vopl_in>;
1229			};
1230		};
1231	};
1232
1233	vopl_mmu: iommu@ff470f00 {
1234		compatible = "rockchip,iommu";
1235		reg = <0x0 0xff470f00 0x0 0x100>;
1236		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237		clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238		clock-names = "aclk", "iface";
1239		power-domains = <&power PX30_PD_VO>;
1240		#iommu-cells = <0>;
1241		status = "disabled";
1242	};
1243
1244	cif: video-capture@ff490000 {
1245		compatible = "rockchip,px30-vip";
1246		reg = <0x0 0xff490000 0x0 0x200>;
1247		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1248		clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>;
1249		clock-names = "aclk", "hclk", "pclk";
1250		power-domains = <&power PX30_PD_VI>;
1251		resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
1252		reset-names = "axi", "ahb", "pclkin";
1253		status = "disabled";
1254	};
1255
1256	isp: isp@ff4a0000 {
1257		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1258		reg = <0x0 0xff4a0000 0x0 0x8000>;
1259		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1260			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1261			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1262		interrupt-names = "isp", "mi", "mipi";
1263		clocks = <&cru SCLK_ISP>,
1264			 <&cru ACLK_ISP>,
1265			 <&cru HCLK_ISP>,
1266			 <&cru PCLK_ISP>;
1267		clock-names = "isp", "aclk", "hclk", "pclk";
1268		iommus = <&isp_mmu>;
1269		phys = <&csi_dphy>;
1270		phy-names = "dphy";
1271		power-domains = <&power PX30_PD_VI>;
1272		status = "disabled";
1273
1274		ports {
1275			#address-cells = <1>;
1276			#size-cells = <0>;
1277
1278			isp_in: port@0 {
1279				reg = <0>;
1280			};
1281		};
1282	};
1283
1284	isp_mmu: iommu@ff4a8000 {
1285		compatible = "rockchip,iommu";
1286		reg = <0x0 0xff4a8000 0x0 0x100>;
1287		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1288		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1289		clock-names = "aclk", "iface";
1290		power-domains = <&power PX30_PD_VI>;
1291		rockchip,disable-mmu-reset;
1292		#iommu-cells = <0>;
1293	};
1294
1295	qos_gmac: qos@ff518000 {
1296		compatible = "rockchip,px30-qos", "syscon";
1297		reg = <0x0 0xff518000 0x0 0x20>;
1298	};
1299
1300	qos_gpu: qos@ff520000 {
1301		compatible = "rockchip,px30-qos", "syscon";
1302		reg = <0x0 0xff520000 0x0 0x20>;
1303	};
1304
1305	qos_sdmmc: qos@ff52c000 {
1306		compatible = "rockchip,px30-qos", "syscon";
1307		reg = <0x0 0xff52c000 0x0 0x20>;
1308	};
1309
1310	qos_emmc: qos@ff538000 {
1311		compatible = "rockchip,px30-qos", "syscon";
1312		reg = <0x0 0xff538000 0x0 0x20>;
1313	};
1314
1315	qos_nand: qos@ff538080 {
1316		compatible = "rockchip,px30-qos", "syscon";
1317		reg = <0x0 0xff538080 0x0 0x20>;
1318	};
1319
1320	qos_sdio: qos@ff538100 {
1321		compatible = "rockchip,px30-qos", "syscon";
1322		reg = <0x0 0xff538100 0x0 0x20>;
1323	};
1324
1325	qos_sfc: qos@ff538180 {
1326		compatible = "rockchip,px30-qos", "syscon";
1327		reg = <0x0 0xff538180 0x0 0x20>;
1328	};
1329
1330	qos_usb_host: qos@ff540000 {
1331		compatible = "rockchip,px30-qos", "syscon";
1332		reg = <0x0 0xff540000 0x0 0x20>;
1333	};
1334
1335	qos_usb_otg: qos@ff540080 {
1336		compatible = "rockchip,px30-qos", "syscon";
1337		reg = <0x0 0xff540080 0x0 0x20>;
1338	};
1339
1340	qos_isp_128: qos@ff548000 {
1341		compatible = "rockchip,px30-qos", "syscon";
1342		reg = <0x0 0xff548000 0x0 0x20>;
1343	};
1344
1345	qos_isp_rd: qos@ff548080 {
1346		compatible = "rockchip,px30-qos", "syscon";
1347		reg = <0x0 0xff548080 0x0 0x20>;
1348	};
1349
1350	qos_isp_wr: qos@ff548100 {
1351		compatible = "rockchip,px30-qos", "syscon";
1352		reg = <0x0 0xff548100 0x0 0x20>;
1353	};
1354
1355	qos_isp_m1: qos@ff548180 {
1356		compatible = "rockchip,px30-qos", "syscon";
1357		reg = <0x0 0xff548180 0x0 0x20>;
1358	};
1359
1360	qos_vip: qos@ff548200 {
1361		compatible = "rockchip,px30-qos", "syscon";
1362		reg = <0x0 0xff548200 0x0 0x20>;
1363	};
1364
1365	qos_rga_rd: qos@ff550000 {
1366		compatible = "rockchip,px30-qos", "syscon";
1367		reg = <0x0 0xff550000 0x0 0x20>;
1368	};
1369
1370	qos_rga_wr: qos@ff550080 {
1371		compatible = "rockchip,px30-qos", "syscon";
1372		reg = <0x0 0xff550080 0x0 0x20>;
1373	};
1374
1375	qos_vop_m0: qos@ff550100 {
1376		compatible = "rockchip,px30-qos", "syscon";
1377		reg = <0x0 0xff550100 0x0 0x20>;
1378	};
1379
1380	qos_vop_m1: qos@ff550180 {
1381		compatible = "rockchip,px30-qos", "syscon";
1382		reg = <0x0 0xff550180 0x0 0x20>;
1383	};
1384
1385	qos_vpu: qos@ff558000 {
1386		compatible = "rockchip,px30-qos", "syscon";
1387		reg = <0x0 0xff558000 0x0 0x20>;
1388	};
1389
1390	qos_vpu_r128: qos@ff558080 {
1391		compatible = "rockchip,px30-qos", "syscon";
1392		reg = <0x0 0xff558080 0x0 0x20>;
1393	};
1394
1395	pinctrl: pinctrl {
1396		compatible = "rockchip,px30-pinctrl";
1397		rockchip,grf = <&grf>;
1398		rockchip,pmu = <&pmugrf>;
1399		#address-cells = <2>;
1400		#size-cells = <2>;
1401		ranges;
1402
1403		gpio0: gpio@ff040000 {
1404			compatible = "rockchip,gpio-bank";
1405			reg = <0x0 0xff040000 0x0 0x100>;
1406			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1407			clocks = <&pmucru PCLK_GPIO0_PMU>;
1408			gpio-controller;
1409			#gpio-cells = <2>;
1410
1411			interrupt-controller;
1412			#interrupt-cells = <2>;
1413		};
1414
1415		gpio1: gpio@ff250000 {
1416			compatible = "rockchip,gpio-bank";
1417			reg = <0x0 0xff250000 0x0 0x100>;
1418			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1419			clocks = <&cru PCLK_GPIO1>;
1420			gpio-controller;
1421			#gpio-cells = <2>;
1422
1423			interrupt-controller;
1424			#interrupt-cells = <2>;
1425		};
1426
1427		gpio2: gpio@ff260000 {
1428			compatible = "rockchip,gpio-bank";
1429			reg = <0x0 0xff260000 0x0 0x100>;
1430			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1431			clocks = <&cru PCLK_GPIO2>;
1432			gpio-controller;
1433			#gpio-cells = <2>;
1434
1435			interrupt-controller;
1436			#interrupt-cells = <2>;
1437		};
1438
1439		gpio3: gpio@ff270000 {
1440			compatible = "rockchip,gpio-bank";
1441			reg = <0x0 0xff270000 0x0 0x100>;
1442			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1443			clocks = <&cru PCLK_GPIO3>;
1444			gpio-controller;
1445			#gpio-cells = <2>;
1446
1447			interrupt-controller;
1448			#interrupt-cells = <2>;
1449		};
1450
1451		pcfg_pull_up: pcfg-pull-up {
1452			bias-pull-up;
1453		};
1454
1455		pcfg_pull_down: pcfg-pull-down {
1456			bias-pull-down;
1457		};
1458
1459		pcfg_pull_none: pcfg-pull-none {
1460			bias-disable;
1461		};
1462
1463		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1464			bias-disable;
1465			drive-strength = <2>;
1466		};
1467
1468		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1469			bias-pull-up;
1470			drive-strength = <2>;
1471		};
1472
1473		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1474			bias-pull-up;
1475			drive-strength = <4>;
1476		};
1477
1478		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1479			bias-disable;
1480			drive-strength = <4>;
1481		};
1482
1483		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1484			bias-pull-down;
1485			drive-strength = <4>;
1486		};
1487
1488		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1489			bias-disable;
1490			drive-strength = <8>;
1491		};
1492
1493		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1494			bias-pull-up;
1495			drive-strength = <8>;
1496		};
1497
1498		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1499			bias-disable;
1500			drive-strength = <12>;
1501		};
1502
1503		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1504			bias-pull-up;
1505			drive-strength = <12>;
1506		};
1507
1508		pcfg_pull_none_smt: pcfg-pull-none-smt {
1509			bias-disable;
1510			input-schmitt-enable;
1511		};
1512
1513		pcfg_output_high: pcfg-output-high {
1514			output-high;
1515		};
1516
1517		pcfg_output_low: pcfg-output-low {
1518			output-low;
1519		};
1520
1521		pcfg_input_high: pcfg-input-high {
1522			bias-pull-up;
1523			input-enable;
1524		};
1525
1526		pcfg_input: pcfg-input {
1527			input-enable;
1528		};
1529
1530		i2c0 {
1531			i2c0_xfer: i2c0-xfer {
1532				rockchip,pins =
1533					<0 RK_PB0 1 &pcfg_pull_none_smt>,
1534					<0 RK_PB1 1 &pcfg_pull_none_smt>;
1535			};
1536		};
1537
1538		i2c1 {
1539			i2c1_xfer: i2c1-xfer {
1540				rockchip,pins =
1541					<0 RK_PC2 1 &pcfg_pull_none_smt>,
1542					<0 RK_PC3 1 &pcfg_pull_none_smt>;
1543			};
1544		};
1545
1546		i2c2 {
1547			i2c2_xfer: i2c2-xfer {
1548				rockchip,pins =
1549					<2 RK_PB7 2 &pcfg_pull_none_smt>,
1550					<2 RK_PC0 2 &pcfg_pull_none_smt>;
1551			};
1552		};
1553
1554		i2c3 {
1555			i2c3_xfer: i2c3-xfer {
1556				rockchip,pins =
1557					<1 RK_PB4 4 &pcfg_pull_none_smt>,
1558					<1 RK_PB5 4 &pcfg_pull_none_smt>;
1559			};
1560		};
1561
1562		tsadc {
1563			tsadc_otp_pin: tsadc-otp-pin {
1564				rockchip,pins =
1565					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1566			};
1567
1568			tsadc_otp_out: tsadc-otp-out {
1569				rockchip,pins =
1570					<0 RK_PA6 1 &pcfg_pull_none>;
1571			};
1572		};
1573
1574		uart0 {
1575			uart0_xfer: uart0-xfer {
1576				rockchip,pins =
1577					<0 RK_PB2 1 &pcfg_pull_up>,
1578					<0 RK_PB3 1 &pcfg_pull_up>;
1579			};
1580
1581			uart0_cts: uart0-cts {
1582				rockchip,pins =
1583					<0 RK_PB4 1 &pcfg_pull_none>;
1584			};
1585
1586			uart0_rts: uart0-rts {
1587				rockchip,pins =
1588					<0 RK_PB5 1 &pcfg_pull_none>;
1589			};
1590		};
1591
1592		uart1 {
1593			uart1_xfer: uart1-xfer {
1594				rockchip,pins =
1595					<1 RK_PC1 1 &pcfg_pull_up>,
1596					<1 RK_PC0 1 &pcfg_pull_up>;
1597			};
1598
1599			uart1_cts: uart1-cts {
1600				rockchip,pins =
1601					<1 RK_PC2 1 &pcfg_pull_none>;
1602			};
1603
1604			uart1_rts: uart1-rts {
1605				rockchip,pins =
1606					<1 RK_PC3 1 &pcfg_pull_none>;
1607			};
1608		};
1609
1610		uart2-m0 {
1611			uart2m0_xfer: uart2m0-xfer {
1612				rockchip,pins =
1613					<1 RK_PD2 2 &pcfg_pull_up>,
1614					<1 RK_PD3 2 &pcfg_pull_up>;
1615			};
1616		};
1617
1618		uart2-m1 {
1619			uart2m1_xfer: uart2m1-xfer {
1620				rockchip,pins =
1621					<2 RK_PB4 2 &pcfg_pull_up>,
1622					<2 RK_PB6 2 &pcfg_pull_up>;
1623			};
1624		};
1625
1626		uart3-m0 {
1627			uart3m0_xfer: uart3m0-xfer {
1628				rockchip,pins =
1629					<0 RK_PC0 2 &pcfg_pull_up>,
1630					<0 RK_PC1 2 &pcfg_pull_up>;
1631			};
1632
1633			uart3m0_cts: uart3m0-cts {
1634				rockchip,pins =
1635					<0 RK_PC2 2 &pcfg_pull_none>;
1636			};
1637
1638			uart3m0_rts: uart3m0-rts {
1639				rockchip,pins =
1640					<0 RK_PC3 2 &pcfg_pull_none>;
1641			};
1642		};
1643
1644		uart3-m1 {
1645			uart3m1_xfer: uart3m1-xfer {
1646				rockchip,pins =
1647					<1 RK_PB6 2 &pcfg_pull_up>,
1648					<1 RK_PB7 2 &pcfg_pull_up>;
1649			};
1650
1651			uart3m1_cts: uart3m1-cts {
1652				rockchip,pins =
1653					<1 RK_PB4 2 &pcfg_pull_none>;
1654			};
1655
1656			uart3m1_rts: uart3m1-rts {
1657				rockchip,pins =
1658					<1 RK_PB5 2 &pcfg_pull_none>;
1659			};
1660		};
1661
1662		uart4 {
1663			uart4_xfer: uart4-xfer {
1664				rockchip,pins =
1665					<1 RK_PD4 2 &pcfg_pull_up>,
1666					<1 RK_PD5 2 &pcfg_pull_up>;
1667			};
1668
1669			uart4_cts: uart4-cts {
1670				rockchip,pins =
1671					<1 RK_PD6 2 &pcfg_pull_none>;
1672			};
1673
1674			uart4_rts: uart4-rts {
1675				rockchip,pins =
1676					<1 RK_PD7 2 &pcfg_pull_none>;
1677			};
1678		};
1679
1680		uart5 {
1681			uart5_xfer: uart5-xfer {
1682				rockchip,pins =
1683					<3 RK_PA2 4 &pcfg_pull_up>,
1684					<3 RK_PA1 4 &pcfg_pull_up>;
1685			};
1686
1687			uart5_cts: uart5-cts {
1688				rockchip,pins =
1689					<3 RK_PA3 4 &pcfg_pull_none>;
1690			};
1691
1692			uart5_rts: uart5-rts {
1693				rockchip,pins =
1694					<3 RK_PA5 4 &pcfg_pull_none>;
1695			};
1696		};
1697
1698		spi0 {
1699			spi0_clk: spi0-clk {
1700				rockchip,pins =
1701					<1 RK_PB7 3 &pcfg_pull_up_4ma>;
1702			};
1703
1704			spi0_csn: spi0-csn {
1705				rockchip,pins =
1706					<1 RK_PB6 3 &pcfg_pull_up_4ma>;
1707			};
1708
1709			spi0_miso: spi0-miso {
1710				rockchip,pins =
1711					<1 RK_PB5 3 &pcfg_pull_up_4ma>;
1712			};
1713
1714			spi0_mosi: spi0-mosi {
1715				rockchip,pins =
1716					<1 RK_PB4 3 &pcfg_pull_up_4ma>;
1717			};
1718
1719			spi0_clk_hs: spi0-clk-hs {
1720				rockchip,pins =
1721					<1 RK_PB7 3 &pcfg_pull_up_8ma>;
1722			};
1723
1724			spi0_miso_hs: spi0-miso-hs {
1725				rockchip,pins =
1726					<1 RK_PB5 3 &pcfg_pull_up_8ma>;
1727			};
1728
1729			spi0_mosi_hs: spi0-mosi-hs {
1730				rockchip,pins =
1731					<1 RK_PB4 3 &pcfg_pull_up_8ma>;
1732			};
1733		};
1734
1735		spi1 {
1736			spi1_clk: spi1-clk {
1737				rockchip,pins =
1738					<3 RK_PB7 4 &pcfg_pull_up_4ma>;
1739			};
1740
1741			spi1_csn0: spi1-csn0 {
1742				rockchip,pins =
1743					<3 RK_PB1 4 &pcfg_pull_up_4ma>;
1744			};
1745
1746			spi1_csn1: spi1-csn1 {
1747				rockchip,pins =
1748					<3 RK_PB2 2 &pcfg_pull_up_4ma>;
1749			};
1750
1751			spi1_miso: spi1-miso {
1752				rockchip,pins =
1753					<3 RK_PB6 4 &pcfg_pull_up_4ma>;
1754			};
1755
1756			spi1_mosi: spi1-mosi {
1757				rockchip,pins =
1758					<3 RK_PB4 4 &pcfg_pull_up_4ma>;
1759			};
1760
1761			spi1_clk_hs: spi1-clk-hs {
1762				rockchip,pins =
1763					<3 RK_PB7 4 &pcfg_pull_up_8ma>;
1764			};
1765
1766			spi1_miso_hs: spi1-miso-hs {
1767				rockchip,pins =
1768					<3 RK_PB6 4 &pcfg_pull_up_8ma>;
1769			};
1770
1771			spi1_mosi_hs: spi1-mosi-hs {
1772				rockchip,pins =
1773					<3 RK_PB4 4 &pcfg_pull_up_8ma>;
1774			};
1775		};
1776
1777		pdm {
1778			pdm_clk0m0: pdm-clk0m0 {
1779				rockchip,pins =
1780					<3 RK_PC6 2 &pcfg_pull_none>;
1781			};
1782
1783			pdm_clk0m1: pdm-clk0m1 {
1784				rockchip,pins =
1785					<2 RK_PC6 1 &pcfg_pull_none>;
1786			};
1787
1788			pdm_clk1: pdm-clk1 {
1789				rockchip,pins =
1790					<3 RK_PC7 2 &pcfg_pull_none>;
1791			};
1792
1793			pdm_sdi0m0: pdm-sdi0m0 {
1794				rockchip,pins =
1795					<3 RK_PD3 2 &pcfg_pull_none>;
1796			};
1797
1798			pdm_sdi0m1: pdm-sdi0m1 {
1799				rockchip,pins =
1800					<2 RK_PC5 2 &pcfg_pull_none>;
1801			};
1802
1803			pdm_sdi1: pdm-sdi1 {
1804				rockchip,pins =
1805					<3 RK_PD0 2 &pcfg_pull_none>;
1806			};
1807
1808			pdm_sdi2: pdm-sdi2 {
1809				rockchip,pins =
1810					<3 RK_PD1 2 &pcfg_pull_none>;
1811			};
1812
1813			pdm_sdi3: pdm-sdi3 {
1814				rockchip,pins =
1815					<3 RK_PD2 2 &pcfg_pull_none>;
1816			};
1817
1818			pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1819				rockchip,pins =
1820					<3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1821			};
1822
1823			pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1824				rockchip,pins =
1825					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1826			};
1827
1828			pdm_clk1_sleep: pdm-clk1-sleep {
1829				rockchip,pins =
1830					<3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1831			};
1832
1833			pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1834				rockchip,pins =
1835					<3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1836			};
1837
1838			pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1839				rockchip,pins =
1840					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1841			};
1842
1843			pdm_sdi1_sleep: pdm-sdi1-sleep {
1844				rockchip,pins =
1845					<3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1846			};
1847
1848			pdm_sdi2_sleep: pdm-sdi2-sleep {
1849				rockchip,pins =
1850					<3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1851			};
1852
1853			pdm_sdi3_sleep: pdm-sdi3-sleep {
1854				rockchip,pins =
1855					<3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1856			};
1857		};
1858
1859		i2s0 {
1860			i2s0_8ch_mclk: i2s0-8ch-mclk {
1861				rockchip,pins =
1862					<3 RK_PC1 2 &pcfg_pull_none>;
1863			};
1864
1865			i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1866				rockchip,pins =
1867					<3 RK_PC3 2 &pcfg_pull_none>;
1868			};
1869
1870			i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1871				rockchip,pins =
1872					<3 RK_PB4 2 &pcfg_pull_none>;
1873			};
1874
1875			i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1876				rockchip,pins =
1877					<3 RK_PC2 2 &pcfg_pull_none>;
1878			};
1879
1880			i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1881				rockchip,pins =
1882					<3 RK_PB5 2 &pcfg_pull_none>;
1883			};
1884
1885			i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1886				rockchip,pins =
1887					<3 RK_PC4 2 &pcfg_pull_none>;
1888			};
1889
1890			i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1891				rockchip,pins =
1892					<3 RK_PC0 2 &pcfg_pull_none>;
1893			};
1894
1895			i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1896				rockchip,pins =
1897					<3 RK_PB7 2 &pcfg_pull_none>;
1898			};
1899
1900			i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1901				rockchip,pins =
1902					<3 RK_PB6 2 &pcfg_pull_none>;
1903			};
1904
1905			i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1906				rockchip,pins =
1907					<3 RK_PC5 2 &pcfg_pull_none>;
1908			};
1909
1910			i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1911				rockchip,pins =
1912					<3 RK_PB3 2 &pcfg_pull_none>;
1913			};
1914
1915			i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1916				rockchip,pins =
1917					<3 RK_PB1 2 &pcfg_pull_none>;
1918			};
1919
1920			i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1921				rockchip,pins =
1922					<3 RK_PB0 2 &pcfg_pull_none>;
1923			};
1924		};
1925
1926		i2s1 {
1927			i2s1_2ch_mclk: i2s1-2ch-mclk {
1928				rockchip,pins =
1929					<2 RK_PC3 1 &pcfg_pull_none>;
1930			};
1931
1932			i2s1_2ch_sclk: i2s1-2ch-sclk {
1933				rockchip,pins =
1934					<2 RK_PC2 1 &pcfg_pull_none>;
1935			};
1936
1937			i2s1_2ch_lrck: i2s1-2ch-lrck {
1938				rockchip,pins =
1939					<2 RK_PC1 1 &pcfg_pull_none>;
1940			};
1941
1942			i2s1_2ch_sdi: i2s1-2ch-sdi {
1943				rockchip,pins =
1944					<2 RK_PC5 1 &pcfg_pull_none>;
1945			};
1946
1947			i2s1_2ch_sdo: i2s1-2ch-sdo {
1948				rockchip,pins =
1949					<2 RK_PC4 1 &pcfg_pull_none>;
1950			};
1951		};
1952
1953		i2s2 {
1954			i2s2_2ch_mclk: i2s2-2ch-mclk {
1955				rockchip,pins =
1956					<3 RK_PA1 2 &pcfg_pull_none>;
1957			};
1958
1959			i2s2_2ch_sclk: i2s2-2ch-sclk {
1960				rockchip,pins =
1961					<3 RK_PA2 2 &pcfg_pull_none>;
1962			};
1963
1964			i2s2_2ch_lrck: i2s2-2ch-lrck {
1965				rockchip,pins =
1966					<3 RK_PA3 2 &pcfg_pull_none>;
1967			};
1968
1969			i2s2_2ch_sdi: i2s2-2ch-sdi {
1970				rockchip,pins =
1971					<3 RK_PA5 2 &pcfg_pull_none>;
1972			};
1973
1974			i2s2_2ch_sdo: i2s2-2ch-sdo {
1975				rockchip,pins =
1976					<3 RK_PA7 2 &pcfg_pull_none>;
1977			};
1978		};
1979
1980		sdmmc {
1981			sdmmc_clk: sdmmc-clk {
1982				rockchip,pins =
1983					<1 RK_PD6 1 &pcfg_pull_none_8ma>;
1984			};
1985
1986			sdmmc_cmd: sdmmc-cmd {
1987				rockchip,pins =
1988					<1 RK_PD7 1 &pcfg_pull_up_8ma>;
1989			};
1990
1991			sdmmc_det: sdmmc-det {
1992				rockchip,pins =
1993					<0 RK_PA3 1 &pcfg_pull_up_8ma>;
1994			};
1995
1996			sdmmc_bus1: sdmmc-bus1 {
1997				rockchip,pins =
1998					<1 RK_PD2 1 &pcfg_pull_up_8ma>;
1999			};
2000
2001			sdmmc_bus4: sdmmc-bus4 {
2002				rockchip,pins =
2003					<1 RK_PD2 1 &pcfg_pull_up_8ma>,
2004					<1 RK_PD3 1 &pcfg_pull_up_8ma>,
2005					<1 RK_PD4 1 &pcfg_pull_up_8ma>,
2006					<1 RK_PD5 1 &pcfg_pull_up_8ma>;
2007			};
2008		};
2009
2010		sdio {
2011			sdio_clk: sdio-clk {
2012				rockchip,pins =
2013					<1 RK_PC5 1 &pcfg_pull_none>;
2014			};
2015
2016			sdio_cmd: sdio-cmd {
2017				rockchip,pins =
2018					<1 RK_PC4 1 &pcfg_pull_up>;
2019			};
2020
2021			sdio_bus4: sdio-bus4 {
2022				rockchip,pins =
2023					<1 RK_PC6 1 &pcfg_pull_up>,
2024					<1 RK_PC7 1 &pcfg_pull_up>,
2025					<1 RK_PD0 1 &pcfg_pull_up>,
2026					<1 RK_PD1 1 &pcfg_pull_up>;
2027			};
2028		};
2029
2030		emmc {
2031			emmc_clk: emmc-clk {
2032				rockchip,pins =
2033					<1 RK_PB1 2 &pcfg_pull_none_8ma>;
2034			};
2035
2036			emmc_cmd: emmc-cmd {
2037				rockchip,pins =
2038					<1 RK_PB2 2 &pcfg_pull_up_8ma>;
2039			};
2040
2041			emmc_rstnout: emmc-rstnout {
2042				rockchip,pins =
2043					<1 RK_PB3 2 &pcfg_pull_none>;
2044			};
2045
2046			emmc_bus1: emmc-bus1 {
2047				rockchip,pins =
2048					<1 RK_PA0 2 &pcfg_pull_up_8ma>;
2049			};
2050
2051			emmc_bus4: emmc-bus4 {
2052				rockchip,pins =
2053					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
2054					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
2055					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
2056					<1 RK_PA3 2 &pcfg_pull_up_8ma>;
2057			};
2058
2059			emmc_bus8: emmc-bus8 {
2060				rockchip,pins =
2061					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
2062					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
2063					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
2064					<1 RK_PA3 2 &pcfg_pull_up_8ma>,
2065					<1 RK_PA4 2 &pcfg_pull_up_8ma>,
2066					<1 RK_PA5 2 &pcfg_pull_up_8ma>,
2067					<1 RK_PA6 2 &pcfg_pull_up_8ma>,
2068					<1 RK_PA7 2 &pcfg_pull_up_8ma>;
2069			};
2070		};
2071
2072		flash {
2073			flash_cs0: flash-cs0 {
2074				rockchip,pins =
2075					<1 RK_PB0 1 &pcfg_pull_none>;
2076			};
2077
2078			flash_rdy: flash-rdy {
2079				rockchip,pins =
2080					<1 RK_PB1 1 &pcfg_pull_none>;
2081			};
2082
2083			flash_dqs: flash-dqs {
2084				rockchip,pins =
2085					<1 RK_PB2 1 &pcfg_pull_none>;
2086			};
2087
2088			flash_ale: flash-ale {
2089				rockchip,pins =
2090					<1 RK_PB3 1 &pcfg_pull_none>;
2091			};
2092
2093			flash_cle: flash-cle {
2094				rockchip,pins =
2095					<1 RK_PB4 1 &pcfg_pull_none>;
2096			};
2097
2098			flash_wrn: flash-wrn {
2099				rockchip,pins =
2100					<1 RK_PB5 1 &pcfg_pull_none>;
2101			};
2102
2103			flash_csl: flash-csl {
2104				rockchip,pins =
2105					<1 RK_PB6 1 &pcfg_pull_none>;
2106			};
2107
2108			flash_rdn: flash-rdn {
2109				rockchip,pins =
2110					<1 RK_PB7 1 &pcfg_pull_none>;
2111			};
2112
2113			flash_bus8: flash-bus8 {
2114				rockchip,pins =
2115					<1 RK_PA0 1 &pcfg_pull_up_12ma>,
2116					<1 RK_PA1 1 &pcfg_pull_up_12ma>,
2117					<1 RK_PA2 1 &pcfg_pull_up_12ma>,
2118					<1 RK_PA3 1 &pcfg_pull_up_12ma>,
2119					<1 RK_PA4 1 &pcfg_pull_up_12ma>,
2120					<1 RK_PA5 1 &pcfg_pull_up_12ma>,
2121					<1 RK_PA6 1 &pcfg_pull_up_12ma>,
2122					<1 RK_PA7 1 &pcfg_pull_up_12ma>;
2123			};
2124		};
2125
2126		sfc {
2127			sfc_bus4: sfc-bus4 {
2128				rockchip,pins =
2129					<1 RK_PA0 3 &pcfg_pull_none>,
2130					<1 RK_PA1 3 &pcfg_pull_none>,
2131					<1 RK_PA2 3 &pcfg_pull_none>,
2132					<1 RK_PA3 3 &pcfg_pull_none>;
2133			};
2134
2135			sfc_bus2: sfc-bus2 {
2136				rockchip,pins =
2137					<1 RK_PA0 3 &pcfg_pull_none>,
2138					<1 RK_PA1 3 &pcfg_pull_none>;
2139			};
2140
2141			sfc_cs0: sfc-cs0 {
2142				rockchip,pins =
2143					<1 RK_PA4 3 &pcfg_pull_none>;
2144			};
2145
2146			sfc_clk: sfc-clk {
2147				rockchip,pins =
2148					<1 RK_PB1 3 &pcfg_pull_none>;
2149			};
2150		};
2151
2152		lcdc {
2153			lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2154				rockchip,pins =
2155					<3 RK_PA0 1 &pcfg_pull_none_12ma>;
2156			};
2157
2158			lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2159				rockchip,pins =
2160					<3 RK_PA1 1 &pcfg_pull_none_12ma>;
2161			};
2162
2163			lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2164				rockchip,pins =
2165					<3 RK_PA2 1 &pcfg_pull_none_12ma>;
2166			};
2167
2168			lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2169				rockchip,pins =
2170					<3 RK_PA3 1 &pcfg_pull_none_12ma>;
2171			};
2172
2173			lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2174				rockchip,pins =
2175					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2176					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2177					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2178					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2179					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2180					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2181					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2182					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2183					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2184					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2185					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2186					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2187					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2188					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2189					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2190					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2191					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2192					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2193					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2194					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2195					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2196					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2197					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2198					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2199			};
2200
2201			lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2202				rockchip,pins =
2203					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2204					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2205					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2206					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2207					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2208					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2209					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2210					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2211					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2212					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2213					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2214					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2215					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2216					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2217					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2218					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2219					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2220					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2221			};
2222
2223			lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2224				rockchip,pins =
2225					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2226					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2227					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2228					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2229					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2230					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2231					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2232					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2233					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2234					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2235					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2236					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2237					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2238					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2239					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2240					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2241			};
2242
2243			lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2244				rockchip,pins =
2245					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2246					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2247					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2248					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2249					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2250					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2251					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2252					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2253					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2254					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2255					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2256					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2257					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2258					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2259					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2260					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2261					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2262			};
2263
2264			lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2265				rockchip,pins =
2266					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2267					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2268					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2269					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2270					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2271					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2272					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2273					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2274					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2275					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2276					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2277			};
2278
2279			lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2280				rockchip,pins =
2281					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2282					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2283					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2284					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2285					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2286					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2287					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2288					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2289					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2290			};
2291		};
2292
2293		pwm0 {
2294			pwm0_pin: pwm0-pin {
2295				rockchip,pins =
2296					<0 RK_PB7 1 &pcfg_pull_none>;
2297			};
2298		};
2299
2300		pwm1 {
2301			pwm1_pin: pwm1-pin {
2302				rockchip,pins =
2303					<0 RK_PC0 1 &pcfg_pull_none>;
2304			};
2305		};
2306
2307		pwm2 {
2308			pwm2_pin: pwm2-pin {
2309				rockchip,pins =
2310					<2 RK_PB5 1 &pcfg_pull_none>;
2311			};
2312		};
2313
2314		pwm3 {
2315			pwm3_pin: pwm3-pin {
2316				rockchip,pins =
2317					<0 RK_PC1 1 &pcfg_pull_none>;
2318			};
2319		};
2320
2321		pwm4 {
2322			pwm4_pin: pwm4-pin {
2323				rockchip,pins =
2324					<3 RK_PC2 3 &pcfg_pull_none>;
2325			};
2326		};
2327
2328		pwm5 {
2329			pwm5_pin: pwm5-pin {
2330				rockchip,pins =
2331					<3 RK_PC3 3 &pcfg_pull_none>;
2332			};
2333		};
2334
2335		pwm6 {
2336			pwm6_pin: pwm6-pin {
2337				rockchip,pins =
2338					<3 RK_PC4 3 &pcfg_pull_none>;
2339			};
2340		};
2341
2342		pwm7 {
2343			pwm7_pin: pwm7-pin {
2344				rockchip,pins =
2345					<3 RK_PC5 3 &pcfg_pull_none>;
2346			};
2347		};
2348
2349		gmac {
2350			rmii_pins: rmii-pins {
2351				rockchip,pins =
2352					<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2353					<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2354					<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2355					<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2356					<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2357					<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2358					<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2359					<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2360					<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2361			};
2362
2363			mac_refclk_12ma: mac-refclk-12ma {
2364				rockchip,pins =
2365					<2 RK_PB2 2 &pcfg_pull_none_12ma>;
2366			};
2367
2368			mac_refclk: mac-refclk {
2369				rockchip,pins =
2370					<2 RK_PB2 2 &pcfg_pull_none>;
2371			};
2372		};
2373
2374		cif-m0 {
2375			cif_clkout_m0: cif-clkout-m0 {
2376				rockchip,pins =
2377					<2 RK_PB3 1 &pcfg_pull_none>;
2378			};
2379
2380			dvp_d2d9_m0: dvp-d2d9-m0 {
2381				rockchip,pins =
2382					<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2383					<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2384					<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2385					<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2386					<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2387					<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2388					<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2389					<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2390					<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2391					<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2392					<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2393					<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2394			};
2395
2396			dvp_d0d1_m0: dvp-d0d1-m0 {
2397				rockchip,pins =
2398					<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2399					<2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2400			};
2401
2402			dvp_d10d11_m0:d10-d11-m0 {
2403				rockchip,pins =
2404					<2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2405					<2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2406			};
2407		};
2408
2409		cif-m1 {
2410			cif_clkout_m1: cif-clkout-m1 {
2411				rockchip,pins =
2412					<3 RK_PD0 3 &pcfg_pull_none>;
2413			};
2414
2415			dvp_d2d9_m1: dvp-d2d9-m1 {
2416				rockchip,pins =
2417					<3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2418					<3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2419					<3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2420					<3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2421					<3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2422					<3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2423					<3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2424					<3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2425					<3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2426					<3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2427					<3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2428					<3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2429			};
2430
2431			dvp_d0d1_m1: dvp-d0d1-m1 {
2432				rockchip,pins =
2433					<3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2434					<3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2435			};
2436
2437			dvp_d10d11_m1:d10-d11-m1 {
2438				rockchip,pins =
2439					<3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2440					<3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2441			};
2442		};
2443
2444		isp {
2445			isp_prelight: isp-prelight {
2446				rockchip,pins =
2447					<3 RK_PD1 4 &pcfg_pull_none>;
2448			};
2449		};
2450	};
2451};