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rzg3s-smarc-som.dtsi

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linux-6.19.14/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi DEVICETREE 
  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2/*
  3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
  4 *
  5 * Copyright (C) 2023 Renesas Electronics Corp.
  6 */
  7
  8#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
  9#include <dt-bindings/gpio/gpio.h>
 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 11
 12#include "rzg3s-smarc-switches.h"
 13
 14/ {
 15	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
 16
 17	aliases {
 18		i2c1 = &i2c1;
 19		mmc0 = &sdhi0;
 20#if SW_CONFIG3 == SW_OFF
 21		mmc2 = &sdhi2;
 22#else
 23		ethernet0 = &eth0;
 24		ethernet1 = &eth1;
 25#endif
 26	};
 27
 28	memory@48000000 {
 29		device_type = "memory";
 30		/* First 128MB is reserved for secure area. */
 31		reg = <0x0 0x48000000 0x0 0x38000000>;
 32	};
 33
 34	vcc_sdhi0: regulator0 {
 35		compatible = "regulator-fixed";
 36		regulator-name = "SDHI0 Vcc";
 37		regulator-min-microvolt = <3300000>;
 38		regulator-max-microvolt = <3300000>;
 39		gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
 40		enable-active-high;
 41	};
 42
 43	vccq_sdhi0: regulator1 {
 44		compatible = "regulator-gpio";
 45		regulator-name = "SDHI0 VccQ";
 46		regulator-min-microvolt = <1800000>;
 47		regulator-max-microvolt = <3300000>;
 48		gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
 49		gpios-states = <1>;
 50		states = <3300000 1>, <1800000 0>;
 51	};
 52
 53	reg_1p8v: regulator2 {
 54		compatible = "regulator-fixed";
 55		regulator-name = "fixed-1.8V";
 56		regulator-min-microvolt = <1800000>;
 57		regulator-max-microvolt = <1800000>;
 58		regulator-boot-on;
 59		regulator-always-on;
 60	};
 61
 62	reg_3p3v: regulator3 {
 63		compatible = "regulator-fixed";
 64		regulator-name = "fixed-3.3V";
 65		regulator-min-microvolt = <3300000>;
 66		regulator-max-microvolt = <3300000>;
 67		regulator-boot-on;
 68		regulator-always-on;
 69	};
 70
 71	vcc_sdhi2: regulator4 {
 72		compatible = "regulator-fixed";
 73		regulator-name = "SDHI2 Vcc";
 74		regulator-min-microvolt = <3300000>;
 75		regulator-max-microvolt = <3300000>;
 76		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
 77		enable-active-high;
 78	};
 79
 80	x3_clk: x3-clock {
 81		compatible = "fixed-clock";
 82		#clock-cells = <0>;
 83		clock-frequency = <24000000>;
 84	};
 85};
 86
 87#if SW_CONFIG3 == SW_ON
 88&eth0 {
 89	pinctrl-0 = <&eth0_pins>;
 90	pinctrl-names = "default";
 91	phy-handle = <&phy0>;
 92	phy-mode = "rgmii-id";
 93	status = "okay";
 94
 95	phy0: ethernet-phy@7 {
 96		reg = <7>;
 97		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
 98		rxc-skew-psec = <0>;
 99		txc-skew-psec = <0>;
100		rxdv-skew-psec = <0>;
101		txen-skew-psec = <0>;
102		rxd0-skew-psec = <0>;
103		rxd1-skew-psec = <0>;
104		rxd2-skew-psec = <0>;
105		rxd3-skew-psec = <0>;
106		txd0-skew-psec = <0>;
107		txd1-skew-psec = <0>;
108		txd2-skew-psec = <0>;
109		txd3-skew-psec = <0>;
110	};
111};
112
113&eth1 {
114	pinctrl-0 = <&eth1_pins>;
115	pinctrl-names = "default";
116	phy-handle = <&phy1>;
117	phy-mode = "rgmii-id";
118	status = "okay";
119
120	phy1: ethernet-phy@7 {
121		reg = <7>;
122		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
123		rxc-skew-psec = <0>;
124		txc-skew-psec = <0>;
125		rxdv-skew-psec = <0>;
126		txen-skew-psec = <0>;
127		rxd0-skew-psec = <0>;
128		rxd1-skew-psec = <0>;
129		rxd2-skew-psec = <0>;
130		rxd3-skew-psec = <0>;
131		txd0-skew-psec = <0>;
132		txd1-skew-psec = <0>;
133		txd2-skew-psec = <0>;
134		txd3-skew-psec = <0>;
135	};
136};
137#endif
138
139&extal_clk {
140	clock-frequency = <24000000>;
141};
142
143&i2c1 {
144	status = "okay";
145
146	versa3: clock-generator@68 {
147		compatible = "renesas,5l35023";
148		reg = <0x68>;
149		clocks = <&x3_clk>;
150		#clock-cells = <1>;
151		assigned-clocks = <&versa3 0>,
152				  <&versa3 1>,
153				  <&versa3 2>,
154				  <&versa3 3>,
155				  <&versa3 4>,
156				  <&versa3 5>;
157		assigned-clock-rates = <24000000>,
158				       <12288000>,
159				       <11289600>,
160				       <25000000>,
161				       <100000000>,
162				       <100000000>;
163		renesas,settings = [
164		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
165		  00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
166		  a0 80 30 30 9c
167		];
168	};
169};
170
171#if SW_CONFIG2 == SW_ON
172/* SD0 slot */
173&sdhi0 {
174	pinctrl-0 = <&sdhi0_pins>;
175	pinctrl-1 = <&sdhi0_uhs_pins>;
176	pinctrl-names = "default", "state_uhs";
177	vmmc-supply = <&vcc_sdhi0>;
178	vqmmc-supply = <&vccq_sdhi0>;
179	bus-width = <4>;
180	sd-uhs-sdr50;
181	sd-uhs-sdr104;
182	max-frequency = <125000000>;
183	status = "okay";
184};
185#else
186/* eMMC */
187&sdhi0 {
188	pinctrl-0 = <&sdhi0_emmc_pins>;
189	pinctrl-1 = <&sdhi0_emmc_pins>;
190	pinctrl-names = "default", "state_uhs";
191	vmmc-supply = <&vcc_sdhi0>;
192	vqmmc-supply = <&reg_1p8v>;
193	bus-width = <8>;
194	mmc-hs200-1_8v;
195	non-removable;
196	fixed-emmc-driver-type = <1>;
197	max-frequency = <125000000>;
198	status = "okay";
199};
200#endif
201
202#if SW_CONFIG3 == SW_OFF
203&sdhi2 {
204	pinctrl-0 = <&sdhi2_pins>;
205	pinctrl-names = "default";
206	vmmc-supply = <&vcc_sdhi2>;
207	bus-width = <4>;
208	max-frequency = <50000000>;
209	status = "okay";
210};
211#endif
212
213&pinctrl {
214#if SW_CONFIG3 == SW_ON
215	eth0-phy-irq-hog {
216		gpio-hog;
217		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
218		input;
219		line-name = "eth0-phy-irq";
220	};
221#endif
222
223	eth0_pins: eth0 {
224		txc {
225			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
226			power-source = <1800>;
227			output-enable;
228			input-enable;
229			drive-strength-microamp = <5200>;
230		};
231
232		tx_ctl {
233			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
234			power-source = <1800>;
235			output-enable;
236			drive-strength-microamp = <5200>;
237		};
238
239		mux {
240			pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,	/* ET0_TXD0 */
241				 <RZG2L_PORT_PINMUX(1, 3, 1)>,	/* ET0_TXD1 */
242				 <RZG2L_PORT_PINMUX(1, 4, 1)>,	/* ET0_TXD2 */
243				 <RZG2L_PORT_PINMUX(2, 0, 1)>,	/* ET0_TXD3 */
244				 <RZG2L_PORT_PINMUX(3, 0, 1)>,	/* ET0_RXC */
245				 <RZG2L_PORT_PINMUX(3, 1, 1)>,	/* ET0_RX_CTL */
246				 <RZG2L_PORT_PINMUX(3, 2, 1)>,	/* ET0_RXD0 */
247				 <RZG2L_PORT_PINMUX(3, 3, 1)>,	/* ET0_RXD1 */
248				 <RZG2L_PORT_PINMUX(4, 0, 1)>,	/* ET0_RXD2 */
249				 <RZG2L_PORT_PINMUX(4, 1, 1)>,	/* ET0_RXD3 */
250				 <RZG2L_PORT_PINMUX(4, 3, 1)>,	/* ET0_MDC */
251				 <RZG2L_PORT_PINMUX(4, 4, 1)>,	/* ET0_MDIO */
252				 <RZG2L_PORT_PINMUX(4, 5, 1)>;	/* ET0_LINKSTA */
253			power-source = <1800>;
254		};
255	};
256
257#if SW_CONFIG3 == SW_ON
258	eth1-phy-irq-hog {
259		gpio-hog;
260		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
261		input;
262		line-name = "eth1-phy-irq";
263	};
264#endif
265
266	eth1_pins: eth1 {
267		txc {
268			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;	/* ET1_TXC */
269			power-source = <1800>;
270			output-enable;
271			input-enable;
272			drive-strength-microamp = <5200>;
273		};
274
275		tx_ctl {
276			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;	/* ET1_TX_CTL */
277			power-source = <1800>;
278			output-enable;
279			drive-strength-microamp = <5200>;
280		};
281
282		mux {
283			pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,	/* ET1_TXD0 */
284				 <RZG2L_PORT_PINMUX(7, 3, 1)>,	/* ET1_TXD1 */
285				 <RZG2L_PORT_PINMUX(7, 4, 1)>,	/* ET1_TXD2 */
286				 <RZG2L_PORT_PINMUX(8, 0, 1)>,	/* ET1_TXD3 */
287				 <RZG2L_PORT_PINMUX(8, 4, 1)>,	/* ET1_RXC */
288				 <RZG2L_PORT_PINMUX(9, 0, 1)>,	/* ET1_RX_CTL */
289				 <RZG2L_PORT_PINMUX(9, 1, 1)>,	/* ET1_RXD0 */
290				 <RZG2L_PORT_PINMUX(9, 2, 1)>,	/* ET1_RXD1 */
291				 <RZG2L_PORT_PINMUX(9, 3, 1)>,	/* ET1_RXD2 */
292				 <RZG2L_PORT_PINMUX(10, 0, 1)>,	/* ET1_RXD3 */
293				 <RZG2L_PORT_PINMUX(10, 2, 1)>,	/* ET1_MDC */
294				 <RZG2L_PORT_PINMUX(10, 3, 1)>,	/* ET1_MDIO */
295				 <RZG2L_PORT_PINMUX(10, 4, 1)>;	/* ET1_LINKSTA */
296			power-source = <1800>;
297		};
298	};
299
300	sdhi0_pins: sd0 {
301		data {
302			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
303			power-source = <3300>;
304		};
305
306		ctrl {
307			pins = "SD0_CLK", "SD0_CMD";
308			power-source = <3300>;
309		};
310
311		cd {
312			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
313		};
314	};
315
316	sdhi0_uhs_pins: sd0-uhs {
317		data {
318			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
319			power-source = <1800>;
320		};
321
322		ctrl {
323			pins = "SD0_CLK", "SD0_CMD";
324			power-source = <1800>;
325		};
326
327		cd {
328			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
329		};
330	};
331
332	sdhi0_emmc_pins: sd0-emmc {
333		pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
334		       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
335		       "SD0_CLK", "SD0_CMD", "SD0_RST#";
336		power-source = <1800>;
337	};
338
339	sdhi2_pins: sd2 {
340		data {
341			pins = "P11_2", "P11_3", "P12_0", "P12_1";
342			input-enable;
343		};
344
345		ctrl {
346			pins = "P11_1";
347			input-enable;
348		};
349
350		mux {
351			pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
352				 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
353				 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
354				 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
355				 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
356				 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
357				 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
358		};
359	};
360};
361
362&rtc {
363	status = "okay";
364};
365
366&vbattb {
367	assigned-clocks = <&vbattb VBATTB_MUX>;
368	assigned-clock-parents = <&vbattb VBATTB_XC>;
369	quartz-load-femtofarads = <12500>;
370	status = "okay";
371};
372
373&vbattb_xtal {
374	clock-frequency = <32768>;
375};
376
377&wdt0 {
378	timeout-sec = <60>;
379	status = "okay";
380};
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