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rzg3e-smarc-som.dtsi

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linux-6.19.14/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi DEVICETREE 
  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2/*
  3 * Device Tree Source for the R9A09G047E57 SMARC SoM board.
  4 *
  5 * Copyright (C) 2024 Renesas Electronics Corp.
  6 */
  7
  8/*
  9 * Please set the below switch position on the SoM and the corresponding macro
 10 * on the board DTS:
 11 *
 12 * Switch position SYS.1, Macro SW_SD0_DEV_SEL:
 13 *      0 - SD0 is connected to eMMC (default)
 14 *      1 - SD0 is connected to uSD0 card
 15 *
 16 * Switch position SYS.5, Macro SW_LCD_EN:
 17 *      0 - Select Misc. Signals routing
 18 *      1 - Select LCD
 19 *
 20 * Switch position BOOT.6, Macro SW_PDM_EN:
 21 *      0 - Select CAN routing
 22 *      1 - Select PDM
 23 */
 24
 25/ {
 26	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
 27
 28	aliases {
 29		ethernet0 = &eth0;
 30		ethernet1 = &eth1;
 31		i2c2 = &i2c2;
 32		mmc0 = &sdhi0;
 33		mmc2 = &sdhi2;
 34	};
 35
 36	memory@48000000 {
 37		device_type = "memory";
 38		/* First 128MB is reserved for secure area. */
 39		reg = <0x0 0x48000000 0x0 0xf8000000>;
 40	};
 41
 42	reg_1p8v: regulator-1p8v {
 43		compatible = "regulator-fixed";
 44		regulator-name = "fixed-1.8V";
 45		regulator-min-microvolt = <1800000>;
 46		regulator-max-microvolt = <1800000>;
 47		regulator-boot-on;
 48		regulator-always-on;
 49	};
 50
 51	reg_3p3v: regulator-3p3v {
 52		compatible = "regulator-fixed";
 53		regulator-name = "fixed-3.3V";
 54		regulator-min-microvolt = <3300000>;
 55		regulator-max-microvolt = <3300000>;
 56		regulator-boot-on;
 57		regulator-always-on;
 58	};
 59
 60	reg_vdd0p8v_others: regulator-vdd0p8v-others {
 61		compatible = "regulator-fixed";
 62
 63		regulator-name = "fixed-0.8V";
 64		regulator-min-microvolt = <800000>;
 65		regulator-max-microvolt = <800000>;
 66		regulator-boot-on;
 67		regulator-always-on;
 68	};
 69
 70	/* 32.768kHz crystal */
 71	x3: x3-clock {
 72		compatible = "fixed-clock";
 73		#clock-cells = <0>;
 74		clock-frequency = <32768>;
 75	};
 76};
 77
 78&audio_extal_clk {
 79	clock-frequency = <48000000>;
 80};
 81
 82&eth0 {
 83	phy-handle = <&phy0>;
 84	phy-mode = "rgmii-id";
 85
 86	pinctrl-0 = <&eth0_pins>;
 87	pinctrl-names = "default";
 88	status = "okay";
 89};
 90
 91&eth1 {
 92	phy-handle = <&phy1>;
 93	phy-mode = "rgmii-id";
 94
 95	pinctrl-0 = <&eth1_pins>;
 96	pinctrl-names = "default";
 97	status = "okay";
 98};
 99
100&gpu {
101	status = "okay";
102	mali-supply = <&reg_vdd0p8v_others>;
103};
104
105&i2c2 {
106	pinctrl-0 = <&i2c2_pins>;
107	pinctrl-names = "default";
108	clock-frequency = <400000>;
109	status = "okay";
110
111	raa215300: pmic@12 {
112		compatible = "renesas,raa215300";
113		reg = <0x12>, <0x6f>;
114		reg-names = "main", "rtc";
115		clocks = <&x3>;
116		clock-names = "xin";
117
118		pinctrl-0 = <&rtc_irq_pin>;
119		pinctrl-names = "default";
120
121		interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
122	};
123};
124
125&mdio0 {
126	phy0: ethernet-phy@7 {
127		compatible = "ethernet-phy-id0022.1640",
128			     "ethernet-phy-ieee802.3-c22";
129		reg = <7>;
130		interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
131		rxc-skew-psec = <1400>;
132		txc-skew-psec = <1400>;
133		rxdv-skew-psec = <0>;
134		txdv-skew-psec = <0>;
135		rxd0-skew-psec = <0>;
136		rxd1-skew-psec = <0>;
137		rxd2-skew-psec = <0>;
138		rxd3-skew-psec = <0>;
139		txd0-skew-psec = <0>;
140		txd1-skew-psec = <0>;
141		txd2-skew-psec = <0>;
142		txd3-skew-psec = <0>;
143	};
144};
145
146&mdio1 {
147	phy1: ethernet-phy@7 {
148		compatible = "ethernet-phy-id0022.1640",
149			     "ethernet-phy-ieee802.3-c22";
150		reg = <7>;
151		interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
152		rxc-skew-psec = <1400>;
153		txc-skew-psec = <1400>;
154		rxdv-skew-psec = <0>;
155		txdv-skew-psec = <0>;
156		rxd0-skew-psec = <0>;
157		rxd1-skew-psec = <0>;
158		rxd2-skew-psec = <0>;
159		rxd3-skew-psec = <0>;
160		txd0-skew-psec = <0>;
161		txd1-skew-psec = <0>;
162		txd2-skew-psec = <0>;
163		txd3-skew-psec = <0>;
164	};
165};
166
167&pinctrl {
168	eth0_pins: eth0 {
169		clk {
170			pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
171			output-enable;
172		};
173
174		ctrl {
175			pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
176				 <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
177				 <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
178				 <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
179				 <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
180				 <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
181				 <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
182				 <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
183				 <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
184				 <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
185				 <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
186				 <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
187				 <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
188				 <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
189		};
190	};
191
192	eth1_pins: eth1 {
193		clk {
194			pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
195			output-enable;
196		};
197
198		ctrl {
199
200			pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
201				 <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
202				 <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
203				 <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
204				 <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
205				 <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
206				 <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
207				 <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
208				 <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
209				 <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
210				 <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
211				 <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
212				 <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
213				 <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
214		};
215	};
216
217	i2c2_pins: i2c {
218		pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
219			 <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
220	};
221
222	rtc_irq_pin: rtc-irq {
223		pins = "PS1";
224		bias-pull-up;
225	};
226
227	sdhi0_emmc_pins: sd0-emmc {
228		sd0-ctrl {
229			pins = "SD0CLK", "SD0CMD";
230			renesas,output-impedance = <3>;
231		};
232
233		sd0-data {
234			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
235			       "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
236			renesas,output-impedance = <3>;
237		};
238
239		sd0-rst {
240			pins = "SD0RSTN";
241			renesas,output-impedance = <3>;
242		};
243	};
244
245	sdhi0_usd_pins: sd0-usd {
246		sd0-cd {
247			pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
248		};
249
250		sd0-ctrl {
251			pins = "SD0CLK", "SD0CMD";
252			renesas,output-impedance = <3>;
253		};
254
255		sd0-data {
256			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
257			renesas,output-impedance = <3>;
258		};
259
260		sd0-iovs {
261			pins = "SD0IOVS";
262			renesas,output-impedance = <3>;
263		};
264
265		sd0-pwen {
266			pins = "SD0PWEN";
267			renesas,output-impedance = <3>;
268		};
269	};
270
271	sdhi2_pins: sd2 {
272		sd2-cd {
273			pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
274		};
275
276		sd2-ctrl {
277			pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
278				 <RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
279		};
280
281		sd2-data {
282			pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
283				 <RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
284				 <RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
285				 <RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
286		};
287
288		sd2-iovs {
289			pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
290		};
291
292		sd2-pwen {
293			pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
294		};
295	};
296
297	xspi_pins: xspi0 {
298		pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
299			 <RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */
300			 <RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */
301			 <RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */
302			 <RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */
303			 <RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */
304	};
305};
306
307&qextal_clk {
308	clock-frequency = <24000000>;
309};
310
311&rtxin_clk {
312	clock-frequency = <32768>;
313};
314
315#if (SW_SD0_DEV_SEL)
316&sdhi0 {
317	pinctrl-0 = <&sdhi0_usd_pins>;
318	pinctrl-1 = <&sdhi0_usd_pins>;
319	pinctrl-names = "default", "state_uhs";
320
321	vmmc-supply = <&reg_3p3v>;
322	vqmmc-supply = <&sdhi0_vqmmc>;
323	bus-width = <4>;
324	sd-uhs-sdr50;
325	sd-uhs-sdr104;
326	status = "okay";
327};
328
329&sdhi0_vqmmc {
330	status = "okay";
331};
332#else
333&sdhi0 {
334	pinctrl-0 = <&sdhi0_emmc_pins>;
335	pinctrl-1 = <&sdhi0_emmc_pins>;
336	pinctrl-names = "default", "state_uhs";
337
338	vmmc-supply = <&reg_3p3v>;
339	vqmmc-supply = <&reg_1p8v>;
340	bus-width = <8>;
341	mmc-hs200-1_8v;
342	non-removable;
343	fixed-emmc-driver-type = <1>;
344	status = "okay";
345};
346#endif
347
348&sdhi2 {
349	pinctrl-0 = <&sdhi2_pins>;
350	pinctrl-1 = <&sdhi2_pins>;
351	pinctrl-names = "default", "state_uhs";
352
353	vmmc-supply = <&reg_3p3v>;
354	vqmmc-supply = <&sdhi2_vqmmc>;
355	bus-width = <4>;
356	sd-uhs-sdr50;
357	sd-uhs-sdr104;
358	status = "okay";
359};
360
361&sdhi2_vqmmc {
362	status = "okay";
363};
364
365&wdt1 {
366	status = "okay";
367};
368
369&xspi {
370	pinctrl-0 = <&xspi_pins>;
371	pinctrl-names = "default";
372	status = "okay";
373
374	flash@0 {
375		compatible = "jedec,spi-nor";
376		reg = <0>;
377		vcc-supply = <&reg_1p8v>;
378		m25p,fast-read;
379		spi-max-frequency = <50000000>;
380		spi-tx-bus-width = <4>;
381		spi-rx-bus-width = <4>;
382
383		partitions {
384			compatible = "fixed-partitions";
385			#address-cells = <1>;
386			#size-cells = <1>;
387
388			partition@0 {
389				label = "bl2";
390				reg = <0x00000000 0x00060000>;
391			};
392
393			partition@60000 {
394				label = "fip";
395				reg = <0x00060000 0x007a0000>;
396			};
397
398			partition@800000 {
399				label = "user";
400				reg = <0x800000 0x800000>;
401			};
402		};
403	};
404};
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