rzg2l-smarc-pinfunction.dtsi

  1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2/*
  3 * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
  4 *
  5 * Copyright (C) 2021 Renesas Electronics Corp.
  6 */
  7
  8#include <dt-bindings/gpio/gpio.h>
  9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 10
 11&pinctrl {
 12	pinctrl-0 = <&sound_clk_pins>;
 13	pinctrl-names = "default";
 14
 15	can0_pins: can0 {
 16		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
 17			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
 18	};
 19
 20	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
 21	can0-stb-hog {
 22		gpio-hog;
 23		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
 24		output-low;
 25		line-name = "can0_stb";
 26	};
 27
 28	can1_pins: can1 {
 29		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
 30			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
 31	};
 32
 33	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
 34	can1-stb-hog {
 35		gpio-hog;
 36		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
 37		output-low;
 38		line-name = "can1_stb";
 39	};
 40
 41	gpt_pins: gpt {
 42		pinmux = <RZG2L_PORT_PINMUX(43, 0, 2)>, /* GTIOC4A */
 43			 <RZG2L_PORT_PINMUX(43, 1, 2)>; /* GTIOC4B */
 44	};
 45
 46	i2c0_pins: i2c0 {
 47		pins = "RIIC0_SDA", "RIIC0_SCL";
 48		input-enable;
 49	};
 50
 51	i2c1_pins: i2c1 {
 52		pins = "RIIC1_SDA", "RIIC1_SCL";
 53		input-enable;
 54	};
 55
 56	i2c3_pins: i2c3 {
 57		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
 58			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
 59	};
 60
 61	mtu3_pins: mtu3 {
 62		mtu3-ext-clk-input-pin {
 63			pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
 64				 <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */
 65		};
 66
 67		mtu3-pwm {
 68			pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
 69				 <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
 70				 <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
 71				 <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
 72		};
 73
 74#if MTU3_COUNTER_Z_PHASE_SIGNAL
 75		mtu3-zphase-clk {
 76			pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */
 77		};
 78#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
 79	};
 80
 81	scif0_pins: scif0 {
 82		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
 83			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
 84	};
 85
 86	scif2_pins: scif2 {
 87		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
 88			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
 89			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
 90			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
 91	};
 92
 93	sd1-pwr-en-hog {
 94		gpio-hog;
 95		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
 96		output-high;
 97		line-name = "sd1_pwr_en";
 98	};
 99
100	sdhi1_pins: sd1 {
101		sd1_data {
102			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
103			power-source = <3300>;
104		};
105
106		sd1_ctrl {
107			pins = "SD1_CLK", "SD1_CMD";
108			power-source = <3300>;
109		};
110
111		sd1_mux {
112			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
113		};
114	};
115
116	sdhi1_pins_uhs: sd1_uhs {
117		sd1_data_uhs {
118			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
119			power-source = <1800>;
120		};
121
122		sd1_ctrl_uhs {
123			pins = "SD1_CLK", "SD1_CMD";
124			power-source = <1800>;
125		};
126
127		sd1_mux_uhs {
128			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
129		};
130	};
131
132	sound_clk_pins: sound_clk {
133		pins = "AUDIO_CLK1", "AUDIO_CLK2";
134		input-enable;
135	};
136
137	spi1_pins: spi1 {
138		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
139			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
140			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
141			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
142	};
143
144	ssi0_pins: ssi0 {
145		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
146			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
147			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
148			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
149	};
150
151	ssi1_pins: ssi1 {
152		pinmux = <RZG2L_PORT_PINMUX(46, 0, 1)>, /* BCK */
153			 <RZG2L_PORT_PINMUX(46, 1, 1)>, /* RCK */
154			 <RZG2L_PORT_PINMUX(46, 2, 1)>; /* TXD */
155	};
156
157	usb0_pins: usb0 {
158		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
159			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
160			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
161	};
162
163	usb1_pins: usb1 {
164		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
165			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
166	};
167};
168